2015-03-02 10:00:42 +01:00
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# Copyright (c) 2012-2013, 2015 ARM Limited
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2012-02-13 12:43:09 +01:00
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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2008-02-06 05:44:13 +01:00
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# Copyright (c) 2005-2008 The Regents of The University of Michigan
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2011-02-07 07:14:17 +01:00
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# Copyright (c) 2011 Regents of the University of California
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2007-05-28 04:21:17 +02:00
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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2011-02-07 07:14:17 +01:00
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# Rick Strong
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2012-02-13 12:43:09 +01:00
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# Andreas Hansson
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2007-05-28 04:21:17 +02:00
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2009-09-23 00:24:16 +02:00
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import sys
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from m5.defines import buildEnv
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2006-09-05 02:14:07 +02:00
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from m5.params import *
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from m5.proxy import *
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2009-09-23 00:24:16 +02:00
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2015-03-02 10:00:47 +01:00
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from XBar import L2XBar
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2007-07-29 05:30:43 +02:00
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from InstTracer import InstTracer
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2015-01-25 13:22:17 +01:00
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from CPUTracers import ExeTracer
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2009-09-23 00:24:16 +02:00
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from MemObject import MemObject
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sim: Add the notion of clock domains to all ClockedObjects
This patch adds the notion of source- and derived-clock domains to the
ClockedObjects. As such, all clock information is moved to the clock
domain, and the ClockedObjects are grouped into domains.
The clock domains are either source domains, with a specific clock
period, or derived domains that have a parent domain and a divider
(potentially chained). For piece of logic that runs at a derived clock
(a ratio of the clock its parent is running at) the necessary derived
clock domain is created from its corresponding parent clock
domain. For now, the derived clock domain only supports a divider,
thus ensuring a lower speed compared to its parent. Multiplier
functionality implies a PLL logic that has not been modelled yet
(create a separate clock instead).
The clock domains should be used as a mechanism to provide a
controllable clock source that affects clock for every clocked object
lying beneath it. The clock of the domain can (in a future patch) be
controlled by a handler responsible for dynamic frequency scaling of
the respective clock domains.
All the config scripts have been retro-fitted with clock domains. For
the System a default SrcClockDomain is created. For CPUs that run at a
different speed than the system, there is a seperate clock domain
created. This domain incorporates the CPU and the associated
caches. As before, Ruby runs under its own clock domain.
The clock period of all domains are pre-computed, such that no virtual
functions or multiplications are needed when calling
clockPeriod. Instead, the clock period is pre-computed when any
changes occur. For this to be possible, each clock domain tracks its
children.
2013-06-27 11:49:49 +02:00
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from ClockDomain import *
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2006-06-10 05:01:31 +02:00
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2007-07-29 05:30:43 +02:00
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default_tracer = ExeTracer()
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2009-09-23 00:24:16 +02:00
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if buildEnv['TARGET_ISA'] == 'alpha':
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2009-04-09 07:21:27 +02:00
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from AlphaTLB import AlphaDTB, AlphaITB
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2011-10-09 09:15:50 +02:00
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from AlphaInterrupts import AlphaInterrupts
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2013-01-07 19:05:35 +01:00
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from AlphaISA import AlphaISA
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isa_class = AlphaISA
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2009-09-23 00:24:16 +02:00
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elif buildEnv['TARGET_ISA'] == 'sparc':
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2009-04-09 07:21:27 +02:00
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from SparcTLB import SparcTLB
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2011-10-09 09:15:50 +02:00
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from SparcInterrupts import SparcInterrupts
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2013-01-07 19:05:35 +01:00
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from SparcISA import SparcISA
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isa_class = SparcISA
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2009-09-23 00:24:16 +02:00
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elif buildEnv['TARGET_ISA'] == 'x86':
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2009-04-09 07:21:27 +02:00
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from X86TLB import X86TLB
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2011-10-09 09:15:50 +02:00
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from X86LocalApic import X86LocalApic
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2013-01-07 19:05:35 +01:00
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from X86ISA import X86ISA
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isa_class = X86ISA
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2009-09-23 00:24:16 +02:00
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elif buildEnv['TARGET_ISA'] == 'mips':
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2009-04-09 07:21:27 +02:00
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from MipsTLB import MipsTLB
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2011-10-09 09:15:50 +02:00
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from MipsInterrupts import MipsInterrupts
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2013-01-07 19:05:35 +01:00
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from MipsISA import MipsISA
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isa_class = MipsISA
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2009-09-23 00:24:16 +02:00
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elif buildEnv['TARGET_ISA'] == 'arm':
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arm: Add support for ARMv8 (AArch64 & AArch32)
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.
Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.
Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black
2014-01-24 22:29:34 +01:00
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from ArmTLB import ArmTLB, ArmStage2IMMU, ArmStage2DMMU
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2011-10-09 09:15:50 +02:00
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from ArmInterrupts import ArmInterrupts
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2013-01-07 19:05:35 +01:00
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from ArmISA import ArmISA
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isa_class = ArmISA
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2009-10-27 17:24:39 +01:00
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elif buildEnv['TARGET_ISA'] == 'power':
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from PowerTLB import PowerTLB
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2011-10-09 09:15:50 +02:00
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from PowerInterrupts import PowerInterrupts
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2013-01-07 19:05:35 +01:00
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from PowerISA import PowerISA
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isa_class = PowerISA
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arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
[Fix some minor formatting mistakes.]
Signed-off by: Alec Roelke
Signed-off by: Jason Lowe-Power <jason@lowepower.com>
2016-11-30 23:10:28 +01:00
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elif buildEnv['TARGET_ISA'] == 'riscv':
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from RiscvTLB import RiscvTLB
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from RiscvInterrupts import RiscvInterrupts
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from RiscvISA import RiscvISA
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isa_class = RiscvISA
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2007-05-28 04:21:17 +02:00
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2008-08-11 21:22:16 +02:00
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class BaseCPU(MemObject):
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2005-02-03 03:13:01 +01:00
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type = 'BaseCPU'
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2005-01-15 10:12:25 +01:00
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abstract = True
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2012-11-02 17:32:01 +01:00
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cxx_header = "cpu/base.hh"
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2012-09-25 18:49:40 +02:00
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@classmethod
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def export_methods(cls, code):
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code('''
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void switchOut();
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void takeOverFrom(BaseCPU *cpu);
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2013-01-07 19:05:44 +01:00
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bool switchedOut();
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2013-01-07 19:05:48 +01:00
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void flushTLBs();
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2013-04-22 19:20:31 +02:00
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Counter totalInsts();
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2013-06-11 09:18:25 +02:00
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void scheduleInstStop(ThreadID tid, Counter insts, const char *cause);
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void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause);
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2016-04-05 12:29:02 +02:00
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uint64_t getCurrentInstCount(ThreadID tid);
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2012-09-25 18:49:40 +02:00
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''')
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2013-02-15 23:40:08 +01:00
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@classmethod
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def memory_mode(cls):
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"""Which memory mode does this CPU require?"""
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return 'invalid'
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@classmethod
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def require_caches(cls):
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"""Does the CPU model require caches?
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Some CPU models might make assumptions that require them to
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have caches.
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"""
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return False
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@classmethod
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def support_take_over(cls):
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"""Does the CPU model support CPU takeOverFrom?"""
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return False
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2012-09-25 18:49:40 +02:00
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def takeOverFrom(self, old_cpu):
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self._ccObject.takeOverFrom(old_cpu._ccObject)
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2006-07-13 02:22:07 +02:00
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system = Param.System(Parent.any, "system object")
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2008-11-03 03:56:57 +01:00
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cpu_id = Param.Int(-1, "CPU identifier")
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2014-05-10 00:58:46 +02:00
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socket_id = Param.Unsigned(0, "Physical Socket identifier")
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2008-08-11 21:22:16 +02:00
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numThreads = Param.Unsigned(1, "number of HW thread contexts")
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function_trace = Param.Bool(False, "Enable function trace")
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2012-08-21 11:49:43 +02:00
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function_trace_start = Param.Tick(0, "Tick to start function trace")
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2008-08-11 21:22:16 +02:00
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2009-01-31 01:08:13 +01:00
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checker = Param.BaseCPU(NULL, "checker CPU")
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2006-10-08 19:53:24 +02:00
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2008-12-17 18:51:18 +01:00
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do_checkpoint_insts = Param.Bool(True,
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"enable checkpoint pseudo instructions")
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do_statistics_insts = Param.Bool(True,
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"enable statistics pseudo instructions")
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2011-11-02 10:11:14 +01:00
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profile = Param.Latency('0ns', "trace the kernel stack")
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do_quiesce = Param.Bool(True, "enable quiesce instructions")
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2011-11-18 10:33:28 +01:00
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workload = VectorParam.Process([], "processes to run")
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2005-01-15 10:12:25 +01:00
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2009-09-23 00:24:16 +02:00
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if buildEnv['TARGET_ISA'] == 'sparc':
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2009-04-09 07:21:27 +02:00
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dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
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itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
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2015-09-30 18:14:19 +02:00
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interrupts = VectorParam.SparcInterrupts(
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[], "Interrupt Controller")
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2013-01-07 19:05:35 +01:00
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isa = VectorParam.SparcISA([ isa_class() ], "ISA instance")
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2009-09-23 00:24:16 +02:00
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elif buildEnv['TARGET_ISA'] == 'alpha':
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2009-04-09 07:21:27 +02:00
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dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
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itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
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2015-09-30 18:14:19 +02:00
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interrupts = VectorParam.AlphaInterrupts(
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[], "Interrupt Controller")
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2013-01-07 19:05:35 +01:00
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isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance")
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2009-09-23 00:24:16 +02:00
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elif buildEnv['TARGET_ISA'] == 'x86':
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2009-04-09 07:21:27 +02:00
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dtb = Param.X86TLB(X86TLB(), "Data TLB")
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itb = Param.X86TLB(X86TLB(), "Instruction TLB")
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2015-09-30 18:14:19 +02:00
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interrupts = VectorParam.X86LocalApic([], "Interrupt Controller")
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2013-01-07 19:05:35 +01:00
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isa = VectorParam.X86ISA([ isa_class() ], "ISA instance")
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2009-09-23 00:24:16 +02:00
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elif buildEnv['TARGET_ISA'] == 'mips':
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2009-04-09 07:21:27 +02:00
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dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
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itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
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2015-09-30 18:14:19 +02:00
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interrupts = VectorParam.MipsInterrupts(
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[], "Interrupt Controller")
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2013-01-07 19:05:35 +01:00
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isa = VectorParam.MipsISA([ isa_class() ], "ISA instance")
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2009-09-23 00:24:16 +02:00
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elif buildEnv['TARGET_ISA'] == 'arm':
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2009-04-22 00:40:25 +02:00
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dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
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itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
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arm: Add support for ARMv8 (AArch64 & AArch32)
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.
Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.
Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black
2014-01-24 22:29:34 +01:00
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istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans")
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dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans")
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2015-09-30 18:14:19 +02:00
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interrupts = VectorParam.ArmInterrupts(
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[], "Interrupt Controller")
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2013-01-07 19:05:35 +01:00
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isa = VectorParam.ArmISA([ isa_class() ], "ISA instance")
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2009-10-27 17:24:39 +01:00
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elif buildEnv['TARGET_ISA'] == 'power':
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UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
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dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
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itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
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2015-09-30 18:14:19 +02:00
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interrupts = VectorParam.PowerInterrupts(
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[], "Interrupt Controller")
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2013-01-07 19:05:35 +01:00
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isa = VectorParam.PowerISA([ isa_class() ], "ISA instance")
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arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
[Fix some minor formatting mistakes.]
Signed-off by: Alec Roelke
Signed-off by: Jason Lowe-Power <jason@lowepower.com>
2016-11-30 23:10:28 +01:00
|
|
|
elif buildEnv['TARGET_ISA'] == 'riscv':
|
|
|
|
|
dtb = Param.RiscvTLB(RiscvTLB(), "Data TLB")
|
|
|
|
|
itb = Param.RiscvTLB(RiscvTLB(), "Instruction TLB")
|
|
|
|
|
interrupts = VectorParam.RiscvInterrupts(
|
|
|
|
|
[], "Interrupt Controller")
|
|
|
|
|
isa = VectorParam.RiscvISA([ isa_class() ], "ISA instance")
|
2007-08-27 05:24:18 +02:00
|
|
|
else:
|
|
|
|
|
print "Don't know what TLB to use for ISA %s" % \
|
2009-09-23 00:24:16 +02:00
|
|
|
buildEnv['TARGET_ISA']
|
2007-08-27 05:24:18 +02:00
|
|
|
sys.exit(1)
|
|
|
|
|
|
2005-01-15 10:12:25 +01:00
|
|
|
max_insts_all_threads = Param.Counter(0,
|
|
|
|
|
"terminate when all threads have reached this inst count")
|
|
|
|
|
max_insts_any_thread = Param.Counter(0,
|
|
|
|
|
"terminate when any thread reaches this inst count")
|
2013-04-22 19:20:31 +02:00
|
|
|
simpoint_start_insts = VectorParam.Counter([],
|
|
|
|
|
"starting instruction counts of simpoints")
|
2005-01-15 10:12:25 +01:00
|
|
|
max_loads_all_threads = Param.Counter(0,
|
|
|
|
|
"terminate when all threads have reached this load count")
|
|
|
|
|
max_loads_any_thread = Param.Counter(0,
|
|
|
|
|
"terminate when any thread reaches this load count")
|
2012-08-28 20:30:33 +02:00
|
|
|
progress_interval = Param.Frequency('0Hz',
|
|
|
|
|
"frequency to print out the progress message")
|
2005-01-15 10:12:25 +01:00
|
|
|
|
2013-01-07 19:05:45 +01:00
|
|
|
switched_out = Param.Bool(False,
|
|
|
|
|
"Leave the CPU switched out after startup (used when switching " \
|
|
|
|
|
"between CPU models)")
|
Make the notion of a global event tick independent of the actual
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 21:32:06 +02:00
|
|
|
|
2007-07-29 05:30:43 +02:00
|
|
|
tracer = Param.InstTracer(default_tracer, "Instruction tracer")
|
|
|
|
|
|
2012-02-13 12:43:09 +01:00
|
|
|
icache_port = MasterPort("Instruction Port")
|
|
|
|
|
dcache_port = MasterPort("Data Port")
|
2012-01-17 19:55:08 +01:00
|
|
|
_cached_ports = ['icache_port', 'dcache_port']
|
|
|
|
|
|
2011-10-16 14:06:38 +02:00
|
|
|
if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
|
2012-01-17 19:55:08 +01:00
|
|
|
_cached_ports += ["itb.walker.port", "dtb.walker.port"]
|
2011-02-04 05:23:00 +01:00
|
|
|
|
2012-02-13 12:43:09 +01:00
|
|
|
_uncached_slave_ports = []
|
|
|
|
|
_uncached_master_ports = []
|
2011-10-09 09:15:50 +02:00
|
|
|
if buildEnv['TARGET_ISA'] == 'x86':
|
2015-09-30 18:14:19 +02:00
|
|
|
_uncached_slave_ports += ["interrupts[0].pio",
|
|
|
|
|
"interrupts[0].int_slave"]
|
|
|
|
|
_uncached_master_ports += ["interrupts[0].int_master"]
|
2011-02-04 05:23:00 +01:00
|
|
|
|
2012-03-01 18:37:02 +01:00
|
|
|
def createInterruptController(self):
|
|
|
|
|
if buildEnv['TARGET_ISA'] == 'sparc':
|
2015-09-30 18:14:19 +02:00
|
|
|
self.interrupts = [SparcInterrupts() for i in xrange(self.numThreads)]
|
2012-03-01 18:37:02 +01:00
|
|
|
elif buildEnv['TARGET_ISA'] == 'alpha':
|
2015-09-30 18:14:19 +02:00
|
|
|
self.interrupts = [AlphaInterrupts() for i in xrange(self.numThreads)]
|
2012-03-01 18:37:02 +01:00
|
|
|
elif buildEnv['TARGET_ISA'] == 'x86':
|
sim: Add the notion of clock domains to all ClockedObjects
This patch adds the notion of source- and derived-clock domains to the
ClockedObjects. As such, all clock information is moved to the clock
domain, and the ClockedObjects are grouped into domains.
The clock domains are either source domains, with a specific clock
period, or derived domains that have a parent domain and a divider
(potentially chained). For piece of logic that runs at a derived clock
(a ratio of the clock its parent is running at) the necessary derived
clock domain is created from its corresponding parent clock
domain. For now, the derived clock domain only supports a divider,
thus ensuring a lower speed compared to its parent. Multiplier
functionality implies a PLL logic that has not been modelled yet
(create a separate clock instead).
The clock domains should be used as a mechanism to provide a
controllable clock source that affects clock for every clocked object
lying beneath it. The clock of the domain can (in a future patch) be
controlled by a handler responsible for dynamic frequency scaling of
the respective clock domains.
All the config scripts have been retro-fitted with clock domains. For
the System a default SrcClockDomain is created. For CPUs that run at a
different speed than the system, there is a seperate clock domain
created. This domain incorporates the CPU and the associated
caches. As before, Ruby runs under its own clock domain.
The clock period of all domains are pre-computed, such that no virtual
functions or multiplications are needed when calling
clockPeriod. Instead, the clock period is pre-computed when any
changes occur. For this to be possible, each clock domain tracks its
children.
2013-06-27 11:49:49 +02:00
|
|
|
self.apic_clk_domain = DerivedClockDomain(clk_domain =
|
|
|
|
|
Parent.clk_domain,
|
|
|
|
|
clk_divider = 16)
|
2015-09-30 18:14:19 +02:00
|
|
|
self.interrupts = [X86LocalApic(clk_domain = self.apic_clk_domain,
|
2013-02-19 11:56:06 +01:00
|
|
|
pio_addr=0x2000000000000000)
|
2015-09-30 18:14:19 +02:00
|
|
|
for i in xrange(self.numThreads)]
|
2013-02-19 11:56:06 +01:00
|
|
|
_localApic = self.interrupts
|
2012-03-01 18:37:02 +01:00
|
|
|
elif buildEnv['TARGET_ISA'] == 'mips':
|
2015-09-30 18:14:19 +02:00
|
|
|
self.interrupts = [MipsInterrupts() for i in xrange(self.numThreads)]
|
2012-03-01 18:37:02 +01:00
|
|
|
elif buildEnv['TARGET_ISA'] == 'arm':
|
2015-09-30 18:14:19 +02:00
|
|
|
self.interrupts = [ArmInterrupts() for i in xrange(self.numThreads)]
|
2012-03-01 18:37:02 +01:00
|
|
|
elif buildEnv['TARGET_ISA'] == 'power':
|
2015-09-30 18:14:19 +02:00
|
|
|
self.interrupts = [PowerInterrupts() for i in xrange(self.numThreads)]
|
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
[Fix some minor formatting mistakes.]
Signed-off by: Alec Roelke
Signed-off by: Jason Lowe-Power <jason@lowepower.com>
2016-11-30 23:10:28 +01:00
|
|
|
elif buildEnv['TARGET_ISA'] == 'riscv':
|
|
|
|
|
self.interrupts = \
|
|
|
|
|
[RiscvInterrupts() for i in xrange(self.numThreads)]
|
2012-03-01 18:37:02 +01:00
|
|
|
else:
|
|
|
|
|
print "Don't know what Interrupt Controller to use for ISA %s" % \
|
|
|
|
|
buildEnv['TARGET_ISA']
|
|
|
|
|
sys.exit(1)
|
|
|
|
|
|
2011-02-04 05:23:00 +01:00
|
|
|
def connectCachedPorts(self, bus):
|
|
|
|
|
for p in self._cached_ports:
|
2012-02-13 12:43:09 +01:00
|
|
|
exec('self.%s = bus.slave' % p)
|
2006-08-16 18:52:05 +02:00
|
|
|
|
2011-02-04 05:23:00 +01:00
|
|
|
def connectUncachedPorts(self, bus):
|
2012-02-13 12:43:09 +01:00
|
|
|
for p in self._uncached_slave_ports:
|
|
|
|
|
exec('self.%s = bus.master' % p)
|
|
|
|
|
for p in self._uncached_master_ports:
|
|
|
|
|
exec('self.%s = bus.slave' % p)
|
2010-06-02 19:58:16 +02:00
|
|
|
|
2011-02-04 05:23:00 +01:00
|
|
|
def connectAllPorts(self, cached_bus, uncached_bus = None):
|
|
|
|
|
self.connectCachedPorts(cached_bus)
|
|
|
|
|
if not uncached_bus:
|
|
|
|
|
uncached_bus = cached_bus
|
|
|
|
|
self.connectUncachedPorts(uncached_bus)
|
2006-08-16 18:52:05 +02:00
|
|
|
|
2011-02-02 03:28:41 +01:00
|
|
|
def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
|
2006-08-16 18:52:05 +02:00
|
|
|
self.icache = ic
|
|
|
|
|
self.dcache = dc
|
|
|
|
|
self.icache_port = ic.cpu_side
|
|
|
|
|
self.dcache_port = dc.cpu_side
|
2011-02-04 05:23:00 +01:00
|
|
|
self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
|
2012-01-07 11:15:35 +01:00
|
|
|
if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
|
|
|
|
|
if iwc and dwc:
|
|
|
|
|
self.itb_walker_cache = iwc
|
|
|
|
|
self.dtb_walker_cache = dwc
|
2015-03-02 10:00:42 +01:00
|
|
|
self.itb.walker.port = iwc.cpu_side
|
|
|
|
|
self.dtb.walker.port = dwc.cpu_side
|
2012-01-07 11:15:35 +01:00
|
|
|
self._cached_ports += ["itb_walker_cache.mem_side", \
|
|
|
|
|
"dtb_walker_cache.mem_side"]
|
|
|
|
|
else:
|
|
|
|
|
self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
|
2012-03-09 15:59:27 +01:00
|
|
|
|
2012-02-01 07:40:08 +01:00
|
|
|
# Checker doesn't need its own tlb caches because it does
|
|
|
|
|
# functional accesses only
|
2012-03-09 15:59:27 +01:00
|
|
|
if self.checker != NULL:
|
2012-02-01 07:40:08 +01:00
|
|
|
self._cached_ports += ["checker.itb.walker.port", \
|
|
|
|
|
"checker.dtb.walker.port"]
|
2006-08-16 18:52:05 +02:00
|
|
|
|
2011-02-02 03:28:41 +01:00
|
|
|
def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
|
|
|
|
|
self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
|
2015-03-02 10:00:47 +01:00
|
|
|
self.toL2Bus = L2XBar()
|
2011-02-04 05:23:00 +01:00
|
|
|
self.connectCachedPorts(self.toL2Bus)
|
2006-08-16 18:52:05 +02:00
|
|
|
self.l2cache = l2c
|
2012-02-13 12:43:09 +01:00
|
|
|
self.toL2Bus.master = self.l2cache.cpu_side
|
2011-02-04 05:23:00 +01:00
|
|
|
self._cached_ports = ['l2cache.mem_side']
|
2012-03-09 15:59:27 +01:00
|
|
|
|
2013-01-07 19:05:35 +01:00
|
|
|
def createThreads(self):
|
|
|
|
|
self.isa = [ isa_class() for i in xrange(self.numThreads) ]
|
|
|
|
|
if self.checker != NULL:
|
|
|
|
|
self.checker.createThreads()
|
|
|
|
|
|
2012-03-09 15:59:27 +01:00
|
|
|
def addCheckerCpu(self):
|
|
|
|
|
pass
|
