cpu: Put all CPU instruction tracers in a single file
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parent
6c4a23c1c6
commit
0bd986015b
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@ -28,7 +28,7 @@
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from m5.SimObject import SimObject
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from m5.params import *
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from NativeTrace import NativeTrace
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from CPUTracers import NativeTrace
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class ArmNativeTrace(NativeTrace):
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type = 'ArmNativeTrace'
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@ -28,7 +28,7 @@
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from m5.SimObject import SimObject
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from m5.params import *
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from NativeTrace import NativeTrace
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from CPUTracers import NativeTrace
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class SparcNativeTrace(NativeTrace):
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type = 'SparcNativeTrace'
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@ -28,7 +28,7 @@
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from m5.SimObject import SimObject
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from m5.params import *
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from NativeTrace import NativeTrace
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from CPUTracers import NativeTrace
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class X86NativeTrace(NativeTrace):
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type = 'X86NativeTrace'
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@ -49,7 +49,7 @@ from m5.proxy import *
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from XBar import CoherentXBar
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from InstTracer import InstTracer
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from ExeTracer import ExeTracer
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from CPUTracers import ExeTracer
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from MemObject import MemObject
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from ClockDomain import *
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@ -30,7 +30,19 @@ from m5.SimObject import SimObject
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from m5.params import *
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from InstTracer import InstTracer
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class ExeTracer(InstTracer):
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type = 'ExeTracer'
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cxx_class = 'Trace::ExeTracer'
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cxx_header = "cpu/exetrace.hh"
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class IntelTrace(InstTracer):
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type = 'IntelTrace'
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cxx_class = 'Trace::IntelTrace'
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cxx_header = "cpu/inteltrace.hh"
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class NativeTrace(ExeTracer):
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abstract = True
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type = 'NativeTrace'
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cxx_class = 'Trace::NativeTrace'
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cxx_header = 'cpu/nativetrace.hh'
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@ -1,36 +0,0 @@
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# Copyright (c) 2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Gabe Black
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from m5.SimObject import SimObject
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from m5.params import *
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from InstTracer import InstTracer
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class ExeTracer(InstTracer):
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type = 'ExeTracer'
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cxx_class = 'Trace::ExeTracer'
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cxx_header = "cpu/exetrace.hh"
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@ -1,37 +0,0 @@
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# Copyright (c) 2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Gabe Black
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from m5.SimObject import SimObject
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from m5.params import *
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from ExeTracer import ExeTracer
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class NativeTrace(ExeTracer):
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abstract = True
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type = 'NativeTrace'
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cxx_class = 'Trace::NativeTrace'
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cxx_header = "cpu/nativetrace.hh"
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@ -38,11 +38,9 @@ if env['TARGET_ISA'] == 'null':
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SimObject('CheckerCPU.py')
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SimObject('BaseCPU.py')
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SimObject('CPUTracers.py')
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SimObject('FuncUnit.py')
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SimObject('ExeTracer.py')
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SimObject('IntelTrace.py')
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SimObject('IntrControl.py')
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SimObject('NativeTrace.py')
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SimObject('TimingExpr.py')
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Source('activity.cc')
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