Update config file language to take simobj and no longer use siminst
objects/AlphaConsole.mpy:
objects/AlphaTLB.mpy:
objects/BadDevice.mpy:
objects/BaseCPU.mpy:
objects/BaseCache.mpy:
objects/BaseSystem.mpy:
objects/Bus.mpy:
objects/CoherenceProtocol.mpy:
objects/Device.mpy:
objects/DiskImage.mpy:
objects/Ethernet.mpy:
objects/Ide.mpy:
objects/IntrControl.mpy:
objects/MemTest.mpy:
objects/Pci.mpy:
objects/PhysicalMemory.mpy:
objects/Platform.mpy:
objects/Process.mpy:
objects/Repl.mpy:
objects/Root.mpy:
objects/SimConsole.mpy:
objects/SimpleDisk.mpy:
objects/Tsunami.mpy:
objects/Uart.mpy:
simobj now requires a type= line if it is actually intended
to be a type
sim/pyconfig/SConscript:
keep track of the filename of embedded files for better
error messages.
sim/pyconfig/m5config.py:
Add support for the trickery done with the compiler to get the
simobj language feature added to the importer.
fix the bug that gave objects the wrong name in error messages.
test/genini.py:
Globals have been fixed and use execfile
--HG--
extra : convert_revision : b74495fd6f3479a87ecea7f1234ebb6731279b2b
This commit is contained in:
Nathan Binkert
parent
45bb2bf14d
commit
a736a8fab6
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@ -1,8 +1,9 @@
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from Device import PioDevice
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simobj AlphaConsole(PioDevice):
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type = 'AlphaConsole'
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cpu = Param.BaseCPU(Super, "Processor")
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disk = Param.SimpleDisk("Simple Disk")
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num_cpus = Param.Int(1, "Number of CPU's")
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num_cpus = Param.Int(1, "Number of CPUs")
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sim_console = Param.SimConsole(Super, "The Simulator Console")
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system = Param.BaseSystem(Super, "system object")
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@ -1,9 +1,12 @@
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simobj AlphaTLB(SimObject):
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type = 'AlphaTLB'
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abstract = True
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size = Param.Int("TLB size")
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simobj AlphaDTB(AlphaTLB):
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type = 'AlphaDTB'
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size = 64
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simobj AlphaITB(AlphaTLB):
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type = 'AlphaITB'
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size = 48
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@ -1,4 +1,5 @@
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from Device import PioDevice
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simobj BadDevice(PioDevice):
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type = 'BadDevice'
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devicename = Param.String("Name of device to error on")
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@ -1,4 +1,5 @@
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simobj BaseCPU(SimObject):
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type = 'BaseCPU'
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abstract = True
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icache = Param.BaseMem(NULL, "L1 instruction cache object")
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dcache = Param.BaseMem(NULL, "L1 data cache object")
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@ -1,6 +1,7 @@
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from BaseMem import BaseMem
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simobj BaseCache(BaseMem):
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type = 'BaseCache'
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adaptive_compression = Param.Bool(false,
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"Use an adaptive compression scheme")
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assoc = Param.Int("associativity")
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@ -1,4 +1,5 @@
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simobj BaseSystem(SimObject):
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type = 'BaseSystem'
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abstract = True
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memctrl = Param.MemoryController(Super, "memory controller")
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physmem = Param.PhysicalMemory(Super, "phsyical memory")
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@ -1,5 +1,6 @@
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from BaseHier import BaseHier
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simobj Bus(BaseHier):
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type = 'Bus'
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clock_ratio = Param.Int("ratio of CPU to bus frequency")
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width = Param.Int("bus width in bytes")
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@ -1,5 +1,6 @@
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Coherence = Enum('uni', 'msi', 'mesi', 'mosi', 'moesi')
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simobj CoherenceProtocol(SimObject):
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type = 'CoherenceProtocol'
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do_upgrades = Param.Bool(true, "use upgrade transactions?")
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protocol = Param.Coherence("name of coherence protocol")
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@ -11,21 +11,23 @@ from FunctionalMemory import FunctionalMemory
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# initialization phase at which point all SimObject pointers will be
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# valid.
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simobj FooPioDevice(FunctionalMemory):
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abstract = True
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type = 'PioDevice'
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abstract = True
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addr = Param.Addr("Device Address")
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mmu = Param.MemoryController(Super, "Memory Controller")
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io_bus = Param.Bus(NULL, "The IO Bus to attach to")
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pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles")
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simobj FooDmaDevice(FooPioDevice):
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abstract = True
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type = 'DmaDevice'
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abstract = True
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simobj PioDevice(FooPioDevice):
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type = 'PioDevice'
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abstract = True
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platform = Param.Platform(Super, "Platform")
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simobj DmaDevice(PioDevice):
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type = 'DmaDevice'
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abstract = True
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@ -1,12 +1,14 @@
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simobj DiskImage(SimObject):
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type = 'DiskImage'
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abstract = True
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image_file = Param.String("disk image file")
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read_only = Param.Bool(false, "read only image")
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simobj RawDiskImage(DiskImage):
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pass
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type = 'RawDiskImage'
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simobj CowDiskImage(DiskImage):
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type = 'CowDiskImage'
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child = Param.DiskImage("child image")
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table_size = Param.Int(65536, "initial table size")
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image_file = ''
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@ -2,10 +2,12 @@ from Device import DmaDevice
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from Pci import PciDevice
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simobj EtherInt(SimObject):
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type = 'EtherInt'
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abstract = True
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peer = Param.EtherInt(NULL, "peer interface")
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simobj EtherLink(SimObject):
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type = 'EtherLink'
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int1 = Param.EtherInt("interface 1")
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int2 = Param.EtherInt("interface 2")
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delay = Param.Tick(0, "transmit delay of packets in us")
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@ -13,20 +15,24 @@ simobj EtherLink(SimObject):
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dump = Param.EtherDump(NULL, "dump object")
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simobj EtherBus(SimObject):
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type = 'EtherBus'
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loopback = Param.Bool(true,
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"send packet back to the interface from which it came")
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dump = Param.EtherDump(NULL, "dump object")
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speed = Param.UInt64(100000000, "bus speed in bits per second")
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simobj EtherTap(EtherInt):
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type = 'EtherTap'
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bufsz = Param.Int(10000, "tap buffer size")
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dump = Param.EtherDump(NULL, "dump object")
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port = Param.UInt16(3500, "tap port")
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simobj EtherDump(SimObject):
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type = 'EtherDump'
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file = Param.String("dump file")
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simobj EtherDev(DmaDevice):
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type = 'EtherDev'
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hardware_address = Param.EthernetAddr(NextEthernetAddr,
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"Ethernet Hardware Address")
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@ -47,6 +53,7 @@ simobj EtherDev(DmaDevice):
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tlaser = Param.Turbolaser(Super, "Turbolaser")
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simobj NSGigE(PciDevice):
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type = 'NSGigE'
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hardware_address = Param.EthernetAddr(NextEthernetAddr,
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"Ethernet Hardware Address")
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@ -69,9 +76,11 @@ simobj NSGigE(PciDevice):
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physmem = Param.PhysicalMemory(Super, "Physical Memory")
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simobj EtherDevInt(EtherInt):
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type = 'EtherDevInt'
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device = Param.EtherDev("Ethernet device of this interface")
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simobj NSGigEInt(EtherInt):
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type = 'NSGigEInt'
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device = Param.NSGigE("Ethernet device of this interface")
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@ -3,10 +3,12 @@ from Pci import PciDevice
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IdeID = Enum('master', 'slave')
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simobj IdeDisk(SimObject):
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type = 'IdeDisk'
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delay = Param.Tick(1, "Fixed disk delay in microseconds")
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driveID = Param.IdeID('master', "Drive ID")
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image = Param.DiskImage("Disk image")
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physmem = Param.PhysicalMemory(Super, "Physical memory")
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simobj IdeController(PciDevice):
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type = 'IdeController'
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disks = VectorParam.IdeDisk("IDE disks attached to this controller")
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@ -1,2 +1,3 @@
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simobj IntrControl(SimObject):
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type = 'IntrControl'
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cpu = Param.BaseCPU(Super, "the cpu")
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@ -1,4 +1,5 @@
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simobj MemTest(SimObject):
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type = 'MemTest'
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cache = Param.BaseCache("L1 cache")
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check_mem = Param.FunctionalMemory("check memory")
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main_mem = Param.FunctionalMemory("hierarchical memory")
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@ -1,6 +1,7 @@
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from Device import FooPioDevice, DmaDevice
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simobj PciConfigData(FooPioDevice):
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type = 'PciConfigData'
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addr = 0xffffffffffffffffL
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VendorID = Param.UInt16("Vendor ID")
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DeviceID = Param.UInt16("Device ID")
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@ -38,9 +39,10 @@ simobj PciConfigData(FooPioDevice):
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MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
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simobj PciConfigAll(FooPioDevice):
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pass
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type = 'PciConfigAll'
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simobj PciDevice(DmaDevice):
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type = 'PciDevice'
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abstract = True
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pci_bus = Param.Int("PCI bus")
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pci_dev = Param.Int("PCI device number")
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@ -1,6 +1,7 @@
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from FunctionalMemory import FunctionalMemory
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simobj PhysicalMemory(FunctionalMemory):
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type = 'PhysicalMemory'
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range = Param.AddrRange("Device Address")
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file = Param.String('', "memory mapped file")
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mmu = Param.MemoryController(Super, "Memory Controller")
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@ -1,4 +1,5 @@
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simobj Platform(SimObject):
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type = 'Platform'
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abstract = True
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interrupt_frequency = Param.Tick(1200, "frequency of interrupts")
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intrctrl = Param.IntrControl(Super, "interrupt controller")
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@ -1,12 +1,15 @@
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simobj Process(SimObject):
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type = 'Process'
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abstract = True
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output = Param.String('cout', 'filename for stdout/stderr')
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simobj LiveProcess(Process):
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type = 'LiveProcess'
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cmd = VectorParam.String("command line (executable plus arguments)")
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env = VectorParam.String('', "environment settings")
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input = Param.String('cin', "filename for stdin")
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simobj EioProcess(Process):
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type = 'EioProcess'
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chkpt = Param.String('', "EIO checkpoint file name (optional)")
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file = Param.String("EIO trace file name")
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@ -1,7 +1,9 @@
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simobj Repl(SimObject):
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type = 'Repl'
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abstract = True
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simobj GenRepl(Repl):
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type = 'GenRepl'
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fresh_res = Param.Int("associativity")
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num_pools = Param.Int("capacity in bytes")
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pool_res = Param.Int("block size in bytes")
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@ -1,5 +1,6 @@
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from HierParams import HierParams
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simobj Root(SimObject):
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type = 'Root'
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frequency = Param.Tick(200000000, "tick frequency")
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output_dir = Param.String('.', "directory to output data to")
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output_file = Param.String('cout', "file to dump simulator output to")
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@ -1,9 +1,11 @@
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simobj ConsoleListener(SimObject):
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type = 'ConsoleListener'
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port = Param.UInt16(3456, "listen port")
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simobj SimConsole(SimObject):
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type = 'SimConsole'
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append_name = Param.Bool(true, "append name() to filename")
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intr_control = Param.IntrControl(Super, "interrupt controller")
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listener = Param.ConsoleListener("console listener")
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number = Param.Int(0, "console number")
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output = Param.String("", "file to dump output to")
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output = Param.String('', "file to dump output to")
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@ -1,3 +1,4 @@
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simobj SimpleDisk(SimObject):
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type = 'SimpleDisk'
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disk = Param.DiskImage("Disk Image")
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physmem = Param.PhysicalMemory(Super, "Physical Memory")
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@ -2,20 +2,24 @@ from Device import FooPioDevice
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from Platform import Platform
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simobj Tsunami(Platform):
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type = 'Tsunami'
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pciconfig = Param.PciConfigAll("PCI configuration")
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system = Param.BaseSystem(Super, "system")
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interrupt_frequency = Param.Int(1024, "frequency of interrupts")
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simobj TsunamiCChip(FooPioDevice):
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type = 'TsunamiCChip'
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tsunami = Param.Tsunami(Super, "Tsunami")
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simobj TsunamiFake(FooPioDevice):
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pass
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type = 'TsunamiFake'
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simobj TsunamiIO(FooPioDevice):
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type = 'TsunamiIO'
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time = Param.UInt64(1136073600,
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"System time to use (0 for actual time, default is 1/1/06)")
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tsunami = Param.Tsunami(Super, "Tsunami")
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simobj TsunamiPChip(FooPioDevice):
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type = 'TsunamiPChip'
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tsunami = Param.Tsunami(Super, "Tsunami")
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@ -1,5 +1,6 @@
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from Device import PioDevice
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simobj Uart(PioDevice):
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type = 'Uart'
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console = Param.SimConsole(Super, "The console")
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size = Param.Addr(0x8, "Device size")
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@ -28,14 +28,15 @@
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import os, os.path, re
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def WriteEmbeddedPyFile(target, source, path, name, ext):
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def WriteEmbeddedPyFile(target, source, path, name, ext, filename):
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if isinstance(source, str):
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source = file(source, 'r')
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if isinstance(target, str):
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target = file(target, 'w')
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print >>target, "AddModule(%s, %s, %s, '''\\" % (`path`, `name`, `ext`)
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print >>target, "AddModule(%s, %s, %s, %s, '''\\" % \
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(`path`, `name`, `ext`, `filename`)
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for line in source:
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line = line
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@ -105,7 +106,7 @@ def MakeEmbeddedPyFile(target, source, env):
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name,ext = pyfile.split('.')
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if name == '__init__':
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node['.hasinit'] = True
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node[pyfile] = (src,name,ext)
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node[pyfile] = (src,name,ext,src)
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done = False
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while not done:
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@ -136,12 +137,12 @@ def MakeEmbeddedPyFile(target, source, env):
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raise NameError, 'package directory missing __init__.py'
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populate(entry, path + [ name ])
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else:
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pyfile,name,ext = entry
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files.append((pyfile, path, name, ext))
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pyfile,name,ext,filename = entry
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files.append((pyfile, path, name, ext, filename))
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populate(tree)
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for pyfile, path, name, ext in files:
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WriteEmbeddedPyFile(target, pyfile, path, name, ext)
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for pyfile, path, name, ext, filename in files:
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WriteEmbeddedPyFile(target, pyfile, path, name, ext, filename)
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CFileCounter = 0
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def MakePythonCFile(target, source, env):
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@ -221,6 +221,10 @@ def isParamContext(value):
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return False
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class_decorator = '_M5M5_SIMOBJECT_'
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expr_decorator = '_M5M5_EXPRESSION_'
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dot_decorator = '_M5M5_DOT_'
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# The metaclass for ConfigNode (and thus for everything that derives
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# from ConfigNode, including SimObject). This class controls how new
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# classes that derive from ConfigNode are instantiated, and provides
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@ -230,7 +234,6 @@ def isParamContext(value):
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class MetaConfigNode(type):
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keywords = { 'abstract' : types.BooleanType,
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'check' : types.FunctionType,
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'_init' : types.FunctionType,
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'type' : (types.NoneType, types.StringType) }
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# __new__ is called before __init__, and is where the statements
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@ -246,6 +249,11 @@ class MetaConfigNode(type):
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'_disable' : {} }
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for key,val in dict.items():
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del dict[key]
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if key.startswith(expr_decorator):
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key = key[len(expr_decorator):]
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if mcls.keywords.has_key(key):
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if not isinstance(val, mcls.keywords[key]):
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raise TypeError, \
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@ -255,11 +263,9 @@ class MetaConfigNode(type):
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if isinstance(val, types.FunctionType):
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val = classmethod(val)
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priv[key] = val
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del dict[key]
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||||
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elif key.startswith('_'):
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priv[key] = val
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del dict[key]
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elif not isNullPointer(val) and isConfigNode(val):
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dict[key] = val()
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@ -267,19 +273,22 @@ class MetaConfigNode(type):
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elif isSimObjSequence(val):
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dict[key] = [ v() for v in val ]
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else:
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dict[key] = val
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# If your parent has a value in it that's a config node, clone it.
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for base in bases:
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if not isConfigNode(base):
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continue
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for name,value in base._values.iteritems():
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if dict.has_key(name):
|
||||
for key,value in base._values.iteritems():
|
||||
if dict.has_key(key):
|
||||
continue
|
||||
|
||||
if isConfigNode(value):
|
||||
priv['_values'][name] = value()
|
||||
priv['_values'][key] = value()
|
||||
elif isSimObjSequence(value):
|
||||
priv['_values'][name] = [ val() for val in value ]
|
||||
priv['_values'][key] = [ val() for val in value ]
|
||||
|
||||
# entries left in dict will get passed to __init__, where we'll
|
||||
# deal with them as params.
|
||||
|
|
@ -293,12 +302,12 @@ class MetaConfigNode(type):
|
|||
cls._bases = [c for c in cls.__mro__ if isConfigNode(c)]
|
||||
|
||||
# initialize attributes with values from class definition
|
||||
for pname,value in dict.iteritems():
|
||||
setattr(cls, pname, value)
|
||||
|
||||
if hasattr(cls, '_init'):
|
||||
cls._init()
|
||||
del cls._init
|
||||
for key,value in dict.iteritems():
|
||||
key = key.split(dot_decorator)
|
||||
c = cls
|
||||
for item in key[:-1]:
|
||||
c = getattr(c, item)
|
||||
setattr(c, key[-1], value)
|
||||
|
||||
def _isvalue(cls, name):
|
||||
for c in cls._bases:
|
||||
|
|
@ -390,7 +399,6 @@ class MetaConfigNode(type):
|
|||
raise AttributeError, \
|
||||
"object '%s' has no attribute '%s'" % (cls.__name__, cls)
|
||||
|
||||
|
||||
# Set attribute (called on foo.attr = value when foo is an
|
||||
# instance of class cls).
|
||||
def __setattr__(cls, attr, value):
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ sys.path.append('..')
|
|||
sys.path.append('../configs/kernel')
|
||||
sys.path.append('../sim/pyconfig')
|
||||
|
||||
from importer import mpy_exec, AddToPath
|
||||
from importer import mpy_exec, mpy_execfile, AddToPath
|
||||
from m5config import *
|
||||
|
||||
try:
|
||||
|
|
@ -51,7 +51,7 @@ except getopt.GetoptError:
|
|||
|
||||
for arg in args:
|
||||
AddToPath(os.path.dirname(arg))
|
||||
mpy_exec(file(arg, 'r'), globals())
|
||||
mpy_execfile(arg)
|
||||
|
||||
if globals().has_key('root') and isinstance(root, type) \
|
||||
and issubclass(root, Root):
|
||||
|
|
|
|||
Loading…
Reference in a new issue