diff --git a/objects/AlphaConsole.mpy b/objects/AlphaConsole.mpy index bcb47bf8b..79918a01e 100644 --- a/objects/AlphaConsole.mpy +++ b/objects/AlphaConsole.mpy @@ -1,8 +1,9 @@ from Device import PioDevice simobj AlphaConsole(PioDevice): + type = 'AlphaConsole' cpu = Param.BaseCPU(Super, "Processor") disk = Param.SimpleDisk("Simple Disk") - num_cpus = Param.Int(1, "Number of CPU's") + num_cpus = Param.Int(1, "Number of CPUs") sim_console = Param.SimConsole(Super, "The Simulator Console") system = Param.BaseSystem(Super, "system object") diff --git a/objects/AlphaTLB.mpy b/objects/AlphaTLB.mpy index 571b98374..8e7cd62cc 100644 --- a/objects/AlphaTLB.mpy +++ b/objects/AlphaTLB.mpy @@ -1,9 +1,12 @@ simobj AlphaTLB(SimObject): + type = 'AlphaTLB' abstract = True size = Param.Int("TLB size") simobj AlphaDTB(AlphaTLB): + type = 'AlphaDTB' size = 64 simobj AlphaITB(AlphaTLB): + type = 'AlphaITB' size = 48 diff --git a/objects/BadDevice.mpy b/objects/BadDevice.mpy index 5c56b8036..35a12e0bf 100644 --- a/objects/BadDevice.mpy +++ b/objects/BadDevice.mpy @@ -1,4 +1,5 @@ from Device import PioDevice simobj BadDevice(PioDevice): + type = 'BadDevice' devicename = Param.String("Name of device to error on") diff --git a/objects/BaseCPU.mpy b/objects/BaseCPU.mpy index 2aca9120d..516509c1e 100644 --- a/objects/BaseCPU.mpy +++ b/objects/BaseCPU.mpy @@ -1,4 +1,5 @@ simobj BaseCPU(SimObject): + type = 'BaseCPU' abstract = True icache = Param.BaseMem(NULL, "L1 instruction cache object") dcache = Param.BaseMem(NULL, "L1 data cache object") diff --git a/objects/BaseCache.mpy b/objects/BaseCache.mpy index 5f22a344a..95a7f0b35 100644 --- a/objects/BaseCache.mpy +++ b/objects/BaseCache.mpy @@ -1,6 +1,7 @@ from BaseMem import BaseMem simobj BaseCache(BaseMem): + type = 'BaseCache' adaptive_compression = Param.Bool(false, "Use an adaptive compression scheme") assoc = Param.Int("associativity") diff --git a/objects/BaseSystem.mpy b/objects/BaseSystem.mpy index 2a8b98338..460bce736 100644 --- a/objects/BaseSystem.mpy +++ b/objects/BaseSystem.mpy @@ -1,4 +1,5 @@ simobj BaseSystem(SimObject): + type = 'BaseSystem' abstract = True memctrl = Param.MemoryController(Super, "memory controller") physmem = Param.PhysicalMemory(Super, "phsyical memory") diff --git a/objects/Bus.mpy b/objects/Bus.mpy index 9e112bfe6..025d69785 100644 --- a/objects/Bus.mpy +++ b/objects/Bus.mpy @@ -1,5 +1,6 @@ from BaseHier import BaseHier simobj Bus(BaseHier): + type = 'Bus' clock_ratio = Param.Int("ratio of CPU to bus frequency") width = Param.Int("bus width in bytes") diff --git a/objects/CoherenceProtocol.mpy b/objects/CoherenceProtocol.mpy index a2518bf39..c77348f0a 100644 --- a/objects/CoherenceProtocol.mpy +++ b/objects/CoherenceProtocol.mpy @@ -1,5 +1,6 @@ Coherence = Enum('uni', 'msi', 'mesi', 'mosi', 'moesi') simobj CoherenceProtocol(SimObject): + type = 'CoherenceProtocol' do_upgrades = Param.Bool(true, "use upgrade transactions?") protocol = Param.Coherence("name of coherence protocol") diff --git a/objects/Device.mpy b/objects/Device.mpy index babc8aa9d..47f8db1cb 100644 --- a/objects/Device.mpy +++ b/objects/Device.mpy @@ -11,21 +11,23 @@ from FunctionalMemory import FunctionalMemory # initialization phase at which point all SimObject pointers will be # valid. simobj FooPioDevice(FunctionalMemory): - abstract = True type = 'PioDevice' + abstract = True addr = Param.Addr("Device Address") mmu = Param.MemoryController(Super, "Memory Controller") io_bus = Param.Bus(NULL, "The IO Bus to attach to") pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles") simobj FooDmaDevice(FooPioDevice): - abstract = True type = 'DmaDevice' + abstract = True simobj PioDevice(FooPioDevice): + type = 'PioDevice' abstract = True platform = Param.Platform(Super, "Platform") simobj DmaDevice(PioDevice): + type = 'DmaDevice' abstract = True diff --git a/objects/DiskImage.mpy b/objects/DiskImage.mpy index bea2e56a8..908805ba0 100644 --- a/objects/DiskImage.mpy +++ b/objects/DiskImage.mpy @@ -1,12 +1,14 @@ simobj DiskImage(SimObject): + type = 'DiskImage' abstract = True image_file = Param.String("disk image file") read_only = Param.Bool(false, "read only image") simobj RawDiskImage(DiskImage): - pass + type = 'RawDiskImage' simobj CowDiskImage(DiskImage): + type = 'CowDiskImage' child = Param.DiskImage("child image") table_size = Param.Int(65536, "initial table size") image_file = '' diff --git a/objects/Ethernet.mpy b/objects/Ethernet.mpy index 64eab00a3..f9479a5c2 100644 --- a/objects/Ethernet.mpy +++ b/objects/Ethernet.mpy @@ -2,10 +2,12 @@ from Device import DmaDevice from Pci import PciDevice simobj EtherInt(SimObject): + type = 'EtherInt' abstract = True peer = Param.EtherInt(NULL, "peer interface") simobj EtherLink(SimObject): + type = 'EtherLink' int1 = Param.EtherInt("interface 1") int2 = Param.EtherInt("interface 2") delay = Param.Tick(0, "transmit delay of packets in us") @@ -13,20 +15,24 @@ simobj EtherLink(SimObject): dump = Param.EtherDump(NULL, "dump object") simobj EtherBus(SimObject): + type = 'EtherBus' loopback = Param.Bool(true, "send packet back to the interface from which it came") dump = Param.EtherDump(NULL, "dump object") speed = Param.UInt64(100000000, "bus speed in bits per second") simobj EtherTap(EtherInt): + type = 'EtherTap' bufsz = Param.Int(10000, "tap buffer size") dump = Param.EtherDump(NULL, "dump object") port = Param.UInt16(3500, "tap port") simobj EtherDump(SimObject): + type = 'EtherDump' file = Param.String("dump file") simobj EtherDev(DmaDevice): + type = 'EtherDev' hardware_address = Param.EthernetAddr(NextEthernetAddr, "Ethernet Hardware Address") @@ -47,6 +53,7 @@ simobj EtherDev(DmaDevice): tlaser = Param.Turbolaser(Super, "Turbolaser") simobj NSGigE(PciDevice): + type = 'NSGigE' hardware_address = Param.EthernetAddr(NextEthernetAddr, "Ethernet Hardware Address") @@ -69,9 +76,11 @@ simobj NSGigE(PciDevice): physmem = Param.PhysicalMemory(Super, "Physical Memory") simobj EtherDevInt(EtherInt): + type = 'EtherDevInt' device = Param.EtherDev("Ethernet device of this interface") simobj NSGigEInt(EtherInt): + type = 'NSGigEInt' device = Param.NSGigE("Ethernet device of this interface") diff --git a/objects/Ide.mpy b/objects/Ide.mpy index 816b33c8c..c4aa2aca0 100644 --- a/objects/Ide.mpy +++ b/objects/Ide.mpy @@ -3,10 +3,12 @@ from Pci import PciDevice IdeID = Enum('master', 'slave') simobj IdeDisk(SimObject): + type = 'IdeDisk' delay = Param.Tick(1, "Fixed disk delay in microseconds") driveID = Param.IdeID('master', "Drive ID") image = Param.DiskImage("Disk image") physmem = Param.PhysicalMemory(Super, "Physical memory") simobj IdeController(PciDevice): + type = 'IdeController' disks = VectorParam.IdeDisk("IDE disks attached to this controller") diff --git a/objects/IntrControl.mpy b/objects/IntrControl.mpy index 7c97746ff..1ef5a17ee 100644 --- a/objects/IntrControl.mpy +++ b/objects/IntrControl.mpy @@ -1,2 +1,3 @@ simobj IntrControl(SimObject): + type = 'IntrControl' cpu = Param.BaseCPU(Super, "the cpu") diff --git a/objects/MemTest.mpy b/objects/MemTest.mpy index 49319e163..1ec33a30c 100644 --- a/objects/MemTest.mpy +++ b/objects/MemTest.mpy @@ -1,4 +1,5 @@ simobj MemTest(SimObject): + type = 'MemTest' cache = Param.BaseCache("L1 cache") check_mem = Param.FunctionalMemory("check memory") main_mem = Param.FunctionalMemory("hierarchical memory") diff --git a/objects/Pci.mpy b/objects/Pci.mpy index a7763139f..caa3c52ff 100644 --- a/objects/Pci.mpy +++ b/objects/Pci.mpy @@ -1,6 +1,7 @@ from Device import FooPioDevice, DmaDevice simobj PciConfigData(FooPioDevice): + type = 'PciConfigData' addr = 0xffffffffffffffffL VendorID = Param.UInt16("Vendor ID") DeviceID = Param.UInt16("Device ID") @@ -38,9 +39,10 @@ simobj PciConfigData(FooPioDevice): MinimumGrant = Param.UInt8(0x00, "Minimum Grant") simobj PciConfigAll(FooPioDevice): - pass + type = 'PciConfigAll' simobj PciDevice(DmaDevice): + type = 'PciDevice' abstract = True pci_bus = Param.Int("PCI bus") pci_dev = Param.Int("PCI device number") diff --git a/objects/PhysicalMemory.mpy b/objects/PhysicalMemory.mpy index 9644c503a..d1e4ad4b4 100644 --- a/objects/PhysicalMemory.mpy +++ b/objects/PhysicalMemory.mpy @@ -1,6 +1,7 @@ from FunctionalMemory import FunctionalMemory simobj PhysicalMemory(FunctionalMemory): + type = 'PhysicalMemory' range = Param.AddrRange("Device Address") file = Param.String('', "memory mapped file") mmu = Param.MemoryController(Super, "Memory Controller") diff --git a/objects/Platform.mpy b/objects/Platform.mpy index 870026259..d0510eaf8 100644 --- a/objects/Platform.mpy +++ b/objects/Platform.mpy @@ -1,4 +1,5 @@ simobj Platform(SimObject): + type = 'Platform' abstract = True interrupt_frequency = Param.Tick(1200, "frequency of interrupts") intrctrl = Param.IntrControl(Super, "interrupt controller") diff --git a/objects/Process.mpy b/objects/Process.mpy index 4f5c4a674..6a91c09c2 100644 --- a/objects/Process.mpy +++ b/objects/Process.mpy @@ -1,12 +1,15 @@ simobj Process(SimObject): + type = 'Process' abstract = True output = Param.String('cout', 'filename for stdout/stderr') simobj LiveProcess(Process): + type = 'LiveProcess' cmd = VectorParam.String("command line (executable plus arguments)") env = VectorParam.String('', "environment settings") input = Param.String('cin', "filename for stdin") simobj EioProcess(Process): + type = 'EioProcess' chkpt = Param.String('', "EIO checkpoint file name (optional)") file = Param.String("EIO trace file name") diff --git a/objects/Repl.mpy b/objects/Repl.mpy index 87e7bfb7d..fff5a2a02 100644 --- a/objects/Repl.mpy +++ b/objects/Repl.mpy @@ -1,7 +1,9 @@ simobj Repl(SimObject): + type = 'Repl' abstract = True simobj GenRepl(Repl): + type = 'GenRepl' fresh_res = Param.Int("associativity") num_pools = Param.Int("capacity in bytes") pool_res = Param.Int("block size in bytes") diff --git a/objects/Root.mpy b/objects/Root.mpy index b12771689..5806ec826 100644 --- a/objects/Root.mpy +++ b/objects/Root.mpy @@ -1,5 +1,6 @@ from HierParams import HierParams simobj Root(SimObject): + type = 'Root' frequency = Param.Tick(200000000, "tick frequency") output_dir = Param.String('.', "directory to output data to") output_file = Param.String('cout', "file to dump simulator output to") diff --git a/objects/SimConsole.mpy b/objects/SimConsole.mpy index 0676738f9..1231e81dc 100644 --- a/objects/SimConsole.mpy +++ b/objects/SimConsole.mpy @@ -1,9 +1,11 @@ simobj ConsoleListener(SimObject): + type = 'ConsoleListener' port = Param.UInt16(3456, "listen port") simobj SimConsole(SimObject): + type = 'SimConsole' append_name = Param.Bool(true, "append name() to filename") intr_control = Param.IntrControl(Super, "interrupt controller") listener = Param.ConsoleListener("console listener") number = Param.Int(0, "console number") - output = Param.String("", "file to dump output to") + output = Param.String('', "file to dump output to") diff --git a/objects/SimpleDisk.mpy b/objects/SimpleDisk.mpy index 46bbdb8fd..c4dd5435b 100644 --- a/objects/SimpleDisk.mpy +++ b/objects/SimpleDisk.mpy @@ -1,3 +1,4 @@ simobj SimpleDisk(SimObject): + type = 'SimpleDisk' disk = Param.DiskImage("Disk Image") physmem = Param.PhysicalMemory(Super, "Physical Memory") diff --git a/objects/Tsunami.mpy b/objects/Tsunami.mpy index 6f9555d49..cfe23977e 100644 --- a/objects/Tsunami.mpy +++ b/objects/Tsunami.mpy @@ -2,20 +2,24 @@ from Device import FooPioDevice from Platform import Platform simobj Tsunami(Platform): + type = 'Tsunami' pciconfig = Param.PciConfigAll("PCI configuration") system = Param.BaseSystem(Super, "system") interrupt_frequency = Param.Int(1024, "frequency of interrupts") simobj TsunamiCChip(FooPioDevice): + type = 'TsunamiCChip' tsunami = Param.Tsunami(Super, "Tsunami") simobj TsunamiFake(FooPioDevice): - pass + type = 'TsunamiFake' simobj TsunamiIO(FooPioDevice): + type = 'TsunamiIO' time = Param.UInt64(1136073600, "System time to use (0 for actual time, default is 1/1/06)") tsunami = Param.Tsunami(Super, "Tsunami") simobj TsunamiPChip(FooPioDevice): + type = 'TsunamiPChip' tsunami = Param.Tsunami(Super, "Tsunami") diff --git a/objects/Uart.mpy b/objects/Uart.mpy index a54e19dcd..76ee8805f 100644 --- a/objects/Uart.mpy +++ b/objects/Uart.mpy @@ -1,5 +1,6 @@ from Device import PioDevice simobj Uart(PioDevice): + type = 'Uart' console = Param.SimConsole(Super, "The console") size = Param.Addr(0x8, "Device size") diff --git a/sim/pyconfig/SConscript b/sim/pyconfig/SConscript index 127b0efae..5708ac9a8 100644 --- a/sim/pyconfig/SConscript +++ b/sim/pyconfig/SConscript @@ -28,14 +28,15 @@ import os, os.path, re -def WriteEmbeddedPyFile(target, source, path, name, ext): +def WriteEmbeddedPyFile(target, source, path, name, ext, filename): if isinstance(source, str): source = file(source, 'r') if isinstance(target, str): target = file(target, 'w') - print >>target, "AddModule(%s, %s, %s, '''\\" % (`path`, `name`, `ext`) + print >>target, "AddModule(%s, %s, %s, %s, '''\\" % \ + (`path`, `name`, `ext`, `filename`) for line in source: line = line @@ -105,7 +106,7 @@ def MakeEmbeddedPyFile(target, source, env): name,ext = pyfile.split('.') if name == '__init__': node['.hasinit'] = True - node[pyfile] = (src,name,ext) + node[pyfile] = (src,name,ext,src) done = False while not done: @@ -136,12 +137,12 @@ def MakeEmbeddedPyFile(target, source, env): raise NameError, 'package directory missing __init__.py' populate(entry, path + [ name ]) else: - pyfile,name,ext = entry - files.append((pyfile, path, name, ext)) + pyfile,name,ext,filename = entry + files.append((pyfile, path, name, ext, filename)) populate(tree) - for pyfile, path, name, ext in files: - WriteEmbeddedPyFile(target, pyfile, path, name, ext) + for pyfile, path, name, ext, filename in files: + WriteEmbeddedPyFile(target, pyfile, path, name, ext, filename) CFileCounter = 0 def MakePythonCFile(target, source, env): diff --git a/sim/pyconfig/m5config.py b/sim/pyconfig/m5config.py index 4c5fc3bf9..5ba7542a0 100644 --- a/sim/pyconfig/m5config.py +++ b/sim/pyconfig/m5config.py @@ -221,6 +221,10 @@ def isParamContext(value): return False +class_decorator = '_M5M5_SIMOBJECT_' +expr_decorator = '_M5M5_EXPRESSION_' +dot_decorator = '_M5M5_DOT_' + # The metaclass for ConfigNode (and thus for everything that derives # from ConfigNode, including SimObject). This class controls how new # classes that derive from ConfigNode are instantiated, and provides @@ -230,7 +234,6 @@ def isParamContext(value): class MetaConfigNode(type): keywords = { 'abstract' : types.BooleanType, 'check' : types.FunctionType, - '_init' : types.FunctionType, 'type' : (types.NoneType, types.StringType) } # __new__ is called before __init__, and is where the statements @@ -246,6 +249,11 @@ class MetaConfigNode(type): '_disable' : {} } for key,val in dict.items(): + del dict[key] + + if key.startswith(expr_decorator): + key = key[len(expr_decorator):] + if mcls.keywords.has_key(key): if not isinstance(val, mcls.keywords[key]): raise TypeError, \ @@ -255,11 +263,9 @@ class MetaConfigNode(type): if isinstance(val, types.FunctionType): val = classmethod(val) priv[key] = val - del dict[key] elif key.startswith('_'): priv[key] = val - del dict[key] elif not isNullPointer(val) and isConfigNode(val): dict[key] = val() @@ -267,19 +273,22 @@ class MetaConfigNode(type): elif isSimObjSequence(val): dict[key] = [ v() for v in val ] + else: + dict[key] = val + # If your parent has a value in it that's a config node, clone it. for base in bases: if not isConfigNode(base): continue - for name,value in base._values.iteritems(): - if dict.has_key(name): + for key,value in base._values.iteritems(): + if dict.has_key(key): continue if isConfigNode(value): - priv['_values'][name] = value() + priv['_values'][key] = value() elif isSimObjSequence(value): - priv['_values'][name] = [ val() for val in value ] + priv['_values'][key] = [ val() for val in value ] # entries left in dict will get passed to __init__, where we'll # deal with them as params. @@ -293,12 +302,12 @@ class MetaConfigNode(type): cls._bases = [c for c in cls.__mro__ if isConfigNode(c)] # initialize attributes with values from class definition - for pname,value in dict.iteritems(): - setattr(cls, pname, value) - - if hasattr(cls, '_init'): - cls._init() - del cls._init + for key,value in dict.iteritems(): + key = key.split(dot_decorator) + c = cls + for item in key[:-1]: + c = getattr(c, item) + setattr(c, key[-1], value) def _isvalue(cls, name): for c in cls._bases: @@ -390,7 +399,6 @@ class MetaConfigNode(type): raise AttributeError, \ "object '%s' has no attribute '%s'" % (cls.__name__, cls) - # Set attribute (called on foo.attr = value when foo is an # instance of class cls). def __setattr__(cls, attr, value): diff --git a/test/genini.py b/test/genini.py index e96d7069c..db1a7a5b0 100644 --- a/test/genini.py +++ b/test/genini.py @@ -31,7 +31,7 @@ sys.path.append('..') sys.path.append('../configs/kernel') sys.path.append('../sim/pyconfig') -from importer import mpy_exec, AddToPath +from importer import mpy_exec, mpy_execfile, AddToPath from m5config import * try: @@ -51,7 +51,7 @@ except getopt.GetoptError: for arg in args: AddToPath(os.path.dirname(arg)) - mpy_exec(file(arg, 'r'), globals()) + mpy_execfile(arg) if globals().has_key('root') and isinstance(root, type) \ and issubclass(root, Root):