2006-09-05 02:14:07 +02:00
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from m5.SimObject import SimObject
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from m5.params import *
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from m5.proxy import *
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2006-06-10 05:01:31 +02:00
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from m5 import build_env
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2006-08-16 18:52:05 +02:00
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from AlphaTLB import AlphaDTB, AlphaITB
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from Bus import Bus
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2006-06-10 05:01:31 +02:00
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2005-05-29 07:14:50 +02:00
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class BaseCPU(SimObject):
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2005-02-03 03:13:01 +01:00
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type = 'BaseCPU'
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2005-01-15 10:12:25 +01:00
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abstract = True
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2006-08-18 06:17:21 +02:00
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mem = Param.MemObject("memory")
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2005-01-15 10:12:25 +01:00
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2006-07-13 02:22:07 +02:00
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system = Param.System(Parent.any, "system object")
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2005-03-14 13:46:26 +01:00
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if build_env['FULL_SYSTEM']:
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2006-08-16 18:52:05 +02:00
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dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
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itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
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2005-06-29 07:20:41 +02:00
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cpu_id = Param.Int(-1, "CPU identifier")
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2005-03-09 20:42:30 +01:00
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else:
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workload = VectorParam.Process("processes to run")
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2005-01-15 10:12:25 +01:00
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max_insts_all_threads = Param.Counter(0,
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"terminate when all threads have reached this inst count")
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max_insts_any_thread = Param.Counter(0,
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"terminate when any thread reaches this inst count")
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max_loads_all_threads = Param.Counter(0,
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"terminate when all threads have reached this load count")
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max_loads_any_thread = Param.Counter(0,
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"terminate when any thread reaches this load count")
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2006-10-01 05:43:23 +02:00
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progress_interval = Param.Tick(0, "interval to print out the progress message")
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2005-01-15 10:12:25 +01:00
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2005-02-03 23:04:54 +01:00
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defer_registration = Param.Bool(False,
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2005-01-15 10:12:25 +01:00
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"defer registration with system (for sampling)")
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Make the notion of a global event tick independent of the actual
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 21:32:06 +02:00
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2005-06-02 03:44:00 +02:00
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clock = Param.Clock(Parent.clock, "clock speed")
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2006-08-16 18:52:05 +02:00
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_mem_ports = []
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def connectMemPorts(self, bus):
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for p in self._mem_ports:
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exec('self.%s = bus.port' % p)
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def addPrivateSplitL1Caches(self, ic, dc):
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assert(len(self._mem_ports) == 2)
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self.icache = ic
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self.dcache = dc
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self.icache_port = ic.cpu_side
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self.dcache_port = dc.cpu_side
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self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
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2006-08-17 05:46:54 +02:00
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# self.mem = dc
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2006-08-16 18:52:05 +02:00
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def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
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self.addPrivateSplitL1Caches(ic, dc)
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self.toL2Bus = Bus()
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self.connectMemPorts(self.toL2Bus)
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self.l2cache = l2c
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2006-08-16 23:16:52 +02:00
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self.l2cache.cpu_side = self.toL2Bus.port
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2006-08-16 18:52:05 +02:00
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self._mem_ports = ['l2cache.mem_side']
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