Minor regression fixes.

src/python/m5/objects/BaseCPU.py:
    bug fix
tests/SConscript:
    fix up diff ignore strings to reflect changes
    in m5 output

--HG--
extra : convert_revision : b8e4acee34599ddd431b69fc9d40b6f6e440d128

src/python/m5/objects/BaseCPU.py

@@ -49,5 +49,5 @@ class BaseCPU(SimObject):
         self.toL2Bus = Bus()
         self.connectMemPorts(self.toL2Bus)
         self.l2cache = l2c
-        self.l2cache.cpu_side = toL2Bus.port
+        self.l2cache.cpu_side = self.toL2Bus.port
         self._mem_ports = ['l2cache.mem_side']

tests/SConscript

@@ -61,8 +61,9 @@ def check_test(target, source, env):
     # Exclude m5stats.txt since we will use diff-out on that.
     Execute(env.subst('diff -ubr ${SOURCES[0].dir} ${SOURCES[1].dir} ' +
                       '-I "^command line:" ' +		# for stdout file
-                      '-I "^M5 compiled on" ' +		# for stderr file
-                      '-I "^M5 simulation started" ' +	# for stderr file
+                      '-I "^M5 compiled " ' +		# for stderr file
+                      '-I "^M5 started " ' +		# for stderr file
+                      '-I "^M5 executing on " ' +	# for stderr file
                       '-I "^Simulation complete at" ' +	# for stderr file
                       '-I "^Listening for" ' +		# for stderr file
                       '--exclude=m5stats.txt --exclude=SCCS ' +