318 lines
13 KiB
Python
318 lines
13 KiB
Python
# Copyright (c) 2012-2013, 2015 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2005-2008 The Regents of The University of Michigan
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# Copyright (c) 2011 Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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# Rick Strong
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# Andreas Hansson
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import sys
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from m5.defines import buildEnv
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from m5.params import *
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from m5.proxy import *
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from XBar import L2XBar
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from InstTracer import InstTracer
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from CPUTracers import ExeTracer
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from MemObject import MemObject
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from ClockDomain import *
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default_tracer = ExeTracer()
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if buildEnv['TARGET_ISA'] == 'alpha':
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from AlphaTLB import AlphaDTB, AlphaITB
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from AlphaInterrupts import AlphaInterrupts
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from AlphaISA import AlphaISA
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isa_class = AlphaISA
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elif buildEnv['TARGET_ISA'] == 'sparc':
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from SparcTLB import SparcTLB
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from SparcInterrupts import SparcInterrupts
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from SparcISA import SparcISA
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isa_class = SparcISA
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elif buildEnv['TARGET_ISA'] == 'x86':
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from X86TLB import X86TLB
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from X86LocalApic import X86LocalApic
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from X86ISA import X86ISA
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isa_class = X86ISA
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elif buildEnv['TARGET_ISA'] == 'mips':
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from MipsTLB import MipsTLB
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from MipsInterrupts import MipsInterrupts
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from MipsISA import MipsISA
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isa_class = MipsISA
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elif buildEnv['TARGET_ISA'] == 'arm':
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from ArmTLB import ArmTLB, ArmStage2IMMU, ArmStage2DMMU
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from ArmInterrupts import ArmInterrupts
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from ArmISA import ArmISA
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isa_class = ArmISA
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elif buildEnv['TARGET_ISA'] == 'power':
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from PowerTLB import PowerTLB
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from PowerInterrupts import PowerInterrupts
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from PowerISA import PowerISA
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isa_class = PowerISA
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elif buildEnv['TARGET_ISA'] == 'riscv':
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from RiscvTLB import RiscvTLB
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from RiscvInterrupts import RiscvInterrupts
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from RiscvISA import RiscvISA
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isa_class = RiscvISA
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class BaseCPU(MemObject):
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type = 'BaseCPU'
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abstract = True
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cxx_header = "cpu/base.hh"
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@classmethod
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def export_methods(cls, code):
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code('''
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void switchOut();
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void takeOverFrom(BaseCPU *cpu);
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bool switchedOut();
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void flushTLBs();
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Counter totalInsts();
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void scheduleInstStop(ThreadID tid, Counter insts, const char *cause);
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void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause);
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uint64_t getCurrentInstCount(ThreadID tid);
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''')
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@classmethod
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def memory_mode(cls):
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"""Which memory mode does this CPU require?"""
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return 'invalid'
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@classmethod
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def require_caches(cls):
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"""Does the CPU model require caches?
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Some CPU models might make assumptions that require them to
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have caches.
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"""
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return False
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@classmethod
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def support_take_over(cls):
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"""Does the CPU model support CPU takeOverFrom?"""
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return False
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def takeOverFrom(self, old_cpu):
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self._ccObject.takeOverFrom(old_cpu._ccObject)
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system = Param.System(Parent.any, "system object")
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cpu_id = Param.Int(-1, "CPU identifier")
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socket_id = Param.Unsigned(0, "Physical Socket identifier")
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numThreads = Param.Unsigned(1, "number of HW thread contexts")
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function_trace = Param.Bool(False, "Enable function trace")
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function_trace_start = Param.Tick(0, "Tick to start function trace")
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checker = Param.BaseCPU(NULL, "checker CPU")
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do_checkpoint_insts = Param.Bool(True,
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"enable checkpoint pseudo instructions")
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do_statistics_insts = Param.Bool(True,
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"enable statistics pseudo instructions")
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profile = Param.Latency('0ns', "trace the kernel stack")
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do_quiesce = Param.Bool(True, "enable quiesce instructions")
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workload = VectorParam.Process([], "processes to run")
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if buildEnv['TARGET_ISA'] == 'sparc':
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dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
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itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
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interrupts = VectorParam.SparcInterrupts(
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[], "Interrupt Controller")
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isa = VectorParam.SparcISA([ isa_class() ], "ISA instance")
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elif buildEnv['TARGET_ISA'] == 'alpha':
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dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
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itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
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interrupts = VectorParam.AlphaInterrupts(
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[], "Interrupt Controller")
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isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance")
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elif buildEnv['TARGET_ISA'] == 'x86':
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dtb = Param.X86TLB(X86TLB(), "Data TLB")
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itb = Param.X86TLB(X86TLB(), "Instruction TLB")
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interrupts = VectorParam.X86LocalApic([], "Interrupt Controller")
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isa = VectorParam.X86ISA([ isa_class() ], "ISA instance")
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elif buildEnv['TARGET_ISA'] == 'mips':
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dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
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itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
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interrupts = VectorParam.MipsInterrupts(
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[], "Interrupt Controller")
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isa = VectorParam.MipsISA([ isa_class() ], "ISA instance")
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elif buildEnv['TARGET_ISA'] == 'arm':
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dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
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itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
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istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans")
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dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans")
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interrupts = VectorParam.ArmInterrupts(
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[], "Interrupt Controller")
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isa = VectorParam.ArmISA([ isa_class() ], "ISA instance")
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elif buildEnv['TARGET_ISA'] == 'power':
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UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
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dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
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itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
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interrupts = VectorParam.PowerInterrupts(
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[], "Interrupt Controller")
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isa = VectorParam.PowerISA([ isa_class() ], "ISA instance")
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elif buildEnv['TARGET_ISA'] == 'riscv':
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dtb = Param.RiscvTLB(RiscvTLB(), "Data TLB")
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itb = Param.RiscvTLB(RiscvTLB(), "Instruction TLB")
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interrupts = VectorParam.RiscvInterrupts(
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[], "Interrupt Controller")
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isa = VectorParam.RiscvISA([ isa_class() ], "ISA instance")
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else:
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print "Don't know what TLB to use for ISA %s" % \
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buildEnv['TARGET_ISA']
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sys.exit(1)
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max_insts_all_threads = Param.Counter(0,
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"terminate when all threads have reached this inst count")
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max_insts_any_thread = Param.Counter(0,
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"terminate when any thread reaches this inst count")
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simpoint_start_insts = VectorParam.Counter([],
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"starting instruction counts of simpoints")
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max_loads_all_threads = Param.Counter(0,
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"terminate when all threads have reached this load count")
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max_loads_any_thread = Param.Counter(0,
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"terminate when any thread reaches this load count")
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progress_interval = Param.Frequency('0Hz',
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"frequency to print out the progress message")
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switched_out = Param.Bool(False,
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"Leave the CPU switched out after startup (used when switching " \
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"between CPU models)")
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tracer = Param.InstTracer(default_tracer, "Instruction tracer")
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icache_port = MasterPort("Instruction Port")
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dcache_port = MasterPort("Data Port")
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_cached_ports = ['icache_port', 'dcache_port']
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if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
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_cached_ports += ["itb.walker.port", "dtb.walker.port"]
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_uncached_slave_ports = []
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_uncached_master_ports = []
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if buildEnv['TARGET_ISA'] == 'x86':
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_uncached_slave_ports += ["interrupts[0].pio",
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"interrupts[0].int_slave"]
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_uncached_master_ports += ["interrupts[0].int_master"]
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def createInterruptController(self):
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if buildEnv['TARGET_ISA'] == 'sparc':
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self.interrupts = [SparcInterrupts() for i in xrange(self.numThreads)]
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elif buildEnv['TARGET_ISA'] == 'alpha':
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self.interrupts = [AlphaInterrupts() for i in xrange(self.numThreads)]
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elif buildEnv['TARGET_ISA'] == 'x86':
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self.apic_clk_domain = DerivedClockDomain(clk_domain =
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Parent.clk_domain,
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clk_divider = 16)
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self.interrupts = [X86LocalApic(clk_domain = self.apic_clk_domain,
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pio_addr=0x2000000000000000)
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for i in xrange(self.numThreads)]
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_localApic = self.interrupts
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elif buildEnv['TARGET_ISA'] == 'mips':
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self.interrupts = [MipsInterrupts() for i in xrange(self.numThreads)]
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elif buildEnv['TARGET_ISA'] == 'arm':
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self.interrupts = [ArmInterrupts() for i in xrange(self.numThreads)]
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elif buildEnv['TARGET_ISA'] == 'power':
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self.interrupts = [PowerInterrupts() for i in xrange(self.numThreads)]
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elif buildEnv['TARGET_ISA'] == 'riscv':
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self.interrupts = \
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[RiscvInterrupts() for i in xrange(self.numThreads)]
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else:
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print "Don't know what Interrupt Controller to use for ISA %s" % \
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buildEnv['TARGET_ISA']
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sys.exit(1)
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def connectCachedPorts(self, bus):
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for p in self._cached_ports:
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exec('self.%s = bus.slave' % p)
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def connectUncachedPorts(self, bus):
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for p in self._uncached_slave_ports:
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exec('self.%s = bus.master' % p)
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for p in self._uncached_master_ports:
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exec('self.%s = bus.slave' % p)
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def connectAllPorts(self, cached_bus, uncached_bus = None):
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self.connectCachedPorts(cached_bus)
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if not uncached_bus:
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uncached_bus = cached_bus
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self.connectUncachedPorts(uncached_bus)
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def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
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self.icache = ic
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self.dcache = dc
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self.icache_port = ic.cpu_side
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self.dcache_port = dc.cpu_side
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self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
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if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
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if iwc and dwc:
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self.itb_walker_cache = iwc
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self.dtb_walker_cache = dwc
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self.itb.walker.port = iwc.cpu_side
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self.dtb.walker.port = dwc.cpu_side
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self._cached_ports += ["itb_walker_cache.mem_side", \
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"dtb_walker_cache.mem_side"]
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else:
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self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
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# Checker doesn't need its own tlb caches because it does
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# functional accesses only
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if self.checker != NULL:
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self._cached_ports += ["checker.itb.walker.port", \
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"checker.dtb.walker.port"]
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def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
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self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
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self.toL2Bus = L2XBar()
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self.connectCachedPorts(self.toL2Bus)
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self.l2cache = l2c
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self.toL2Bus.master = self.l2cache.cpu_side
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self._cached_ports = ['l2cache.mem_side']
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def createThreads(self):
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self.isa = [ isa_class() for i in xrange(self.numThreads) ]
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if self.checker != NULL:
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self.checker.createThreads()
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def addCheckerCpu(self):
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pass
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