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gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

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Set up m5threads tests on classic (non-ruby) memory system. Just one test (40.m5threads-test-atomic) is set up for now. These tests require that the m5threads SPARC binaries are present in /dist or in test-progs.
2009-04-21 17:37:50 +02:00
---------- Begin Simulation Statistics ----------
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
sim_seconds 0.000110 # Number of seconds simulated
sim_ticks 110344500 # Number of ticks simulated
final_tick 110344500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
host_inst_rate 97195 # Simulator instruction rate (inst/s)
host_op_rate 97194 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 10306929 # Simulator tick rate (ticks/s)
host_mem_usage 249456 # Number of bytes of host memory used
host_seconds 10.71 # Real time elapsed on the host
sim_insts 1040548 # Number of instructions simulated
sim_ops 1040548 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytes_read::cpu3.inst 384 # Number of bytes read from this memory
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytes_read::total 42176 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 22784 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst 384 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 28480 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst 356 # Number of read requests responded to by this memory
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.num_reads::total 659 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst 206480613 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 97440289 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 46400138 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 11600034 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 1740005 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 7540022 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst 3480010 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data 7540022 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 382221135 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 206480613 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 46400138 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 1740005 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst 3480010 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 258100766 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 206480613 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 97440289 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 46400138 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 11600034 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 1740005 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 7540022 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst 3480010 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 7540022 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 382221135 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 660 # Total number of read requests seen
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeReqs 0 # Total number of write requests seen
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.cpureqs 735 # Reqs generatd by CPU via cache - shady
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytesRead 42176 # Total number of bytes read from memory
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.bytesWritten 0 # Total number of bytes written to memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytesConsumedRd 42176 # bytesRead derated as per pkt->getSize()
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.neitherReadNorWrite 75 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 115 # Track reads on a per bank basis
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 60 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 65 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 27 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 18 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 24 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 7 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 23 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 60 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 38 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 17 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 98 # Track reads on a per bank basis
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.totGap 110316500 # Total gap between requests
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.readPktSize::6 660 # Categorize read packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.rdQLenPdf::0 407 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 192 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 47 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytesPerActivate::samples 128 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 282 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 172.796288 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 318.984215 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64 51 39.84% 39.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128 11 8.59% 48.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192 15 11.72% 60.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256 9 7.03% 67.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320 10 7.81% 75.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384 5 3.91% 78.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448 3 2.34% 81.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512 4 3.12% 84.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576 3 2.34% 86.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640 4 3.12% 89.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704 2 1.56% 91.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768 2 1.56% 92.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832 2 1.56% 94.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024 4 3.12% 97.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216 1 0.78% 98.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536 1 0.78% 99.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984 1 0.78% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 128 # Bytes accessed per row activation
system.physmem.totQLat 3607500 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 17921250 # Sum of mem lat for all requests
system.physmem.totBusLat 3300000 # Total cycles spent in databus access
system.physmem.totBankLat 11013750 # Total cycles spent in bank access
system.physmem.avgQLat 5465.91 # Average queueing delay per request
system.physmem.avgBankLat 16687.50 # Average bank access latency per request
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per request
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.avgMemAccLat 27153.41 # Average memory access latency
system.physmem.avgRdBW 382.22 # Average achieved read bandwidth in MB/s
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.avgConsumedRdBW 382.22 # Average consumed read bandwidth in MB/s
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.busUtil 2.99 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.16 # Average read queue length over time
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgWrQLen 0.00 # Average write queue length over time
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.readRowHits 532 # Number of row buffer hits during reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.avgGap 167146.21 # Average gap between requests
system.membus.throughput 382221135 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 529 # Transaction distribution
system.membus.trans_dist::ReadResp 528 # Transaction distribution
system.membus.trans_dist::UpgradeReq 284 # Transaction distribution
system.membus.trans_dist::UpgradeResp 75 # Transaction distribution
system.membus.trans_dist::ReadExReq 164 # Transaction distribution
system.membus.trans_dist::ReadExResp 131 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side 1711 # Packet count per connected master and slave (bytes)
system.membus.pkt_count 1711 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side 42176 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size 42176 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 42176 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 906000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.8 # Layer utilization (%)
system.membus.respLayer0.occupancy 6286926 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 5.7 # Layer utilization (%)
system.toL2Bus.throughput 1697085038 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 2531 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2530 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 287 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 287 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 395 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 395 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1175 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 585 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 850 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 363 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 856 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 356 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 860 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 363 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count 5408 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 37568 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 11136 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 27200 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 27392 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 27520 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size 135488 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 135488 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 51776 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 1621980 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 2642498 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 1437498 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 1913498 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 1155972 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 1.0 # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy 1929492 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy 1158481 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 1.0 # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy 1936496 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 1.8 # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy 1165479 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 1.1 # Layer utilization (%)
system.cpu0.branchPred.lookups 82851 # Number of BP lookups
system.cpu0.branchPred.condPredicted 80650 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 80180 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 78131 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.branchPred.BTBHitPct 97.444500 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target.
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions.
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.workload.num_syscalls 89 # Number of system calls
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.numCycles 220690 # number of cpu cycles simulated
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.fetch.icacheStallCycles 17257 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 491686 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 82851 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 78643 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 161395 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 3805 # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles 13763 # Number of cycles fetch has spent blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.fetch.PendingTrapStallCycles 1562 # Number of stall cycles due to pending traps
system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 494 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples 196421 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 2.503225 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.215279 # Number of instructions fetched each cycle (Total)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.fetch.rateDist::0 35026 17.83% 17.83% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 79943 40.70% 58.53% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 578 0.29% 58.83% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 973 0.50% 59.32% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 477 0.24% 59.56% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 76047 38.72% 98.28% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 571 0.29% 98.57% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 2457 1.25% 100.00% # Number of instructions fetched each cycle (Total)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.fetch.rateDist::total 196421 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.375418 # Number of branch fetches per cycle
system.cpu0.fetch.rate 2.227949 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 17908 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 15370 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 160419 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 285 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 2439 # Number of cycles decode is squashing
system.cpu0.decode.DecodedInsts 488842 # Number of instructions handled by decode
system.cpu0.rename.SquashCycles 2439 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 18575 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 759 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 14008 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 160070 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 570 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 485981 # Number of instructions processed by rename
system.cpu0.rename.LSQFullEvents 199 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands 332328 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 969157 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 969157 # Number of integer rename lookups
system.cpu0.rename.CommittedMaps 319407 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 12921 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 867 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 888 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 3600 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 155469 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 78571 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 75822 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 75638 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 406410 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 911 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 403726 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 135 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 10718 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 9636 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 352 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 196421 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 2.055412 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.097532 # Number of insts issued each cycle
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iq.issued_per_cycle::0 34004 17.31% 17.31% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 4909 2.50% 19.81% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 77804 39.61% 59.42% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 77117 39.26% 98.68% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 1569 0.80% 99.48% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 649 0.33% 99.81% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 264 0.13% 99.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu0.iq.issued_per_cycle::8 18 0.01% 100.00% # Number of insts issued each cycle
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iq.issued_per_cycle::total 196421 # Number of insts issued each cycle
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iq.fu_full::IntAlu 57 25.68% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 53 23.87% 49.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 112 50.45% 100.00% # attempts to use FU when none available
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iq.FU_type_0::IntAlu 170720 42.29% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 155014 38.40% 80.68% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 77992 19.32% 100.00% # Type of FU issued
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iq.FU_type_0::total 403726 # Type of FU issued
system.cpu0.iq.rate 1.829381 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 222 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.000550 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 1004230 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 418093 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 401910 # Number of integer instruction queue wakeup accesses
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iq.int_alu_accesses 403948 # Number of integer alu accesses
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iew.lsq.thread0.forwLoads 75361 # Number of loads that had data forwarded from stores
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iew.lsq.thread0.squashedLoads 2176 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 1418 # Number of stores squashed
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iew.lsq.thread0.cacheBlocked 20 # Number of times an access to memory failed due to the cache being blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iew.iewSquashCycles 2439 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 333 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 32 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 483693 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 313 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 155469 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 78571 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 799 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 342 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 1448 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 402662 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 154684 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 1064 # Number of squashed instructions skipped in execute
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iew.exec_nop 76372 # number of nop insts executed
system.cpu0.iew.exec_refs 232577 # number of memory reference insts executed
system.cpu0.iew.exec_branches 79993 # Number of branches executed
system.cpu0.iew.exec_stores 77893 # Number of stores executed
system.cpu0.iew.exec_rate 1.824559 # Inst execution rate
system.cpu0.iew.wb_sent 402239 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 401910 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 238133 # num instructions producing a value
system.cpu0.iew.wb_consumers 240585 # num instructions consuming a value
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iew.wb_rate 1.821152 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.989808 # average fanout of values written-back
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.commit.commitSquashedInsts 12210 # The number of squashed insts skipped by commit
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 193982 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 2.430442 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 2.136125 # Number of insts commited each cycle
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.commit.committed_per_cycle::0 34427 17.75% 17.75% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 79760 41.12% 58.86% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 2402 1.24% 60.10% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 693 0.36% 60.46% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 529 0.27% 60.73% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 75180 38.76% 99.49% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 442 0.23% 99.72% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 241 0.12% 99.84% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 308 0.16% 100.00% # Number of insts commited each cycle
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.commit.committed_per_cycle::total 193982 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 471462 # Number of instructions committed
system.cpu0.commit.committedOps 471462 # Number of ops (including micro ops) committed
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.commit.refs 230446 # Number of memory references committed
system.cpu0.commit.loads 153293 # Number of loads committed
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.commit.membars 84 # Number of memory barriers committed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.commit.branches 79040 # Number of branches committed
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.commit.int_insts 317738 # Number of committed integer instructions.
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.commit.function_calls 223 # Number of function calls committed.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.commit.bw_lim_events 308 # number cycles where commit BW limit reached
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.rob.rob_reads 676185 # The number of ROB reads
system.cpu0.rob.rob_writes 969800 # The number of ROB writes
system.cpu0.timesIdled 326 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 24269 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts 395606 # Number of Instructions Simulated
system.cpu0.committedOps 395606 # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total 395606 # Number of Instructions Simulated
system.cpu0.cpi 0.557853 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 0.557853 # CPI: Total CPI of All Threads
system.cpu0.ipc 1.792587 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 1.792587 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 720352 # number of integer regfile reads
system.cpu0.int_regfile_writes 324661 # number of integer regfile writes
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.misc_regfile_reads 234400 # number of misc regfile reads
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.icache.replacements 297 # number of replacements
system.cpu0.icache.tagsinuse 241.066229 # Cycle average of tags in use
system.cpu0.icache.total_refs 5081 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 587 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 8.655877 # Average number of references to valid blocks.
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.icache.occ_blocks::cpu0.inst 241.066229 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.470832 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.470832 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 5081 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 5081 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 5081 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 5081 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 5081 # number of overall hits
system.cpu0.icache.overall_hits::total 5081 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 754 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 754 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 754 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 754 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 754 # number of overall misses
system.cpu0.icache.overall_misses::total 754 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 34643000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 34643000 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 34643000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 34643000 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 34643000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 34643000 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 5835 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 5835 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 5835 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 5835 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 5835 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 5835 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.129220 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.129220 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129220 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.129220 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129220 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.129220 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 45945.623342 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 45945.623342 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 45945.623342 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 45945.623342 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 45945.623342 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 45945.623342 # average overall miss latency
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 166 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 166 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 166 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 166 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27004002 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 27004002 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27004002 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 27004002 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27004002 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 27004002 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100771 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.100771 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 45925.173469 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 45925.173469 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 45925.173469 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 45925.173469 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 45925.173469 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 45925.173469 # average overall mshr miss latency
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu0.dcache.replacements 2 # number of replacements
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.tagsinuse 141.846177 # Cycle average of tags in use
system.cpu0.dcache.total_refs 155338 # Total number of references to valid blocks.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.avg_refs 913.752941 # Average number of references to valid blocks.
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.occ_blocks::cpu0.data 141.846177 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.277043 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.277043 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 78856 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 78856 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 76566 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 76566 # number of WriteReq hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.demand_hits::cpu0.data 155422 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 155422 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 155422 # number of overall hits
system.cpu0.dcache.overall_hits::total 155422 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 406 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 406 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 545 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 545 # number of WriteReq misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.demand_misses::cpu0.data 951 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 951 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 951 # number of overall misses
system.cpu0.dcache.overall_misses::total 951 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 12750500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 12750500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35495482 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 35495482 # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 416500 # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total 416500 # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 48245982 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 48245982 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 48245982 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 48245982 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 79262 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 79262 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 77111 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 77111 # number of WriteReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.demand_accesses::cpu0.data 156373 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 156373 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 156373 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 156373 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005122 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.005122 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007068 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.007068 # miss rate for WriteReq accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006082 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.006082 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006082 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.006082 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31405.172414 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 31405.172414 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65129.324771 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 65129.324771 # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19833.333333 # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total 19833.333333 # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50731.842271 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 50731.842271 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50731.842271 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 50731.842271 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 499 # number of cycles access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.761905 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu0.dcache.writebacks::total 1 # number of writebacks
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 220 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 220 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 590 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 590 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 590 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 590 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 186 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 186 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.demand_mshr_misses::cpu0.data 361 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 361 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 361 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6035502 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6035502 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7873000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7873000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 374500 # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total 374500 # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13908502 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 13908502 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13908502 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 13908502 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002347 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002347 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002269 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002269 # mshr miss rate for WriteReq accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002309 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.002309 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002309 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.002309 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32448.935484 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32448.935484 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44988.571429 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44988.571429 # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17833.333333 # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17833.333333 # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38527.706371 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38527.706371 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38527.706371 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38527.706371 # average overall mshr miss latency
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.branchPred.lookups 58259 # Number of BP lookups
system.cpu1.branchPred.condPredicted 55591 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 1274 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 52252 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 51480 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.branchPred.BTBHitPct 98.522545 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 650 # Number of times the RAS was used to get a target.
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.numCycles 176870 # number of cpu cycles simulated
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.fetch.icacheStallCycles 24483 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 332703 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 58259 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 52130 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 112942 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 3669 # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles 23224 # Number of cycles fetch has spent blocked
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.fetch.NoActiveThreadStallCycles 7326 # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles 755 # Number of stall cycles due to pending traps
system.cpu1.fetch.CacheLines 15523 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples 171052 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.945040 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.217476 # Number of instructions fetched each cycle (Total)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.fetch.rateDist::0 58110 33.97% 33.97% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 56330 32.93% 66.90% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 4061 2.37% 69.28% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 3192 1.87% 71.14% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 642 0.38% 71.52% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 43436 25.39% 96.91% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 1285 0.75% 97.66% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 751 0.44% 98.10% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 3245 1.90% 100.00% # Number of instructions fetched each cycle (Total)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.fetch.rateDist::total 171052 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.329389 # Number of branch fetches per cycle
system.cpu1.fetch.rate 1.881060 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 27575 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 21737 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 108940 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 3156 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 2318 # Number of cycles decode is squashing
system.cpu1.decode.DecodedInsts 329200 # Number of instructions handled by decode
system.cpu1.rename.SquashCycles 2318 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 28271 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 9057 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 11940 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 106039 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 6101 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 326983 # Number of instructions processed by rename
system.cpu1.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands 231035 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 638817 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 638817 # Number of integer rename lookups
system.cpu1.rename.CommittedMaps 218174 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 12861 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 1086 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 1205 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 8759 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 95375 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 46677 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 44840 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 41648 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 274055 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 4247 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 274319 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 86 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 10569 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 10360 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 496 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 171052 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 1.603717 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.300528 # Number of insts issued each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iq.issued_per_cycle::0 55274 32.31% 32.31% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 16462 9.62% 41.94% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 46955 27.45% 69.39% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 47561 27.80% 97.19% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 3274 1.91% 99.11% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 1158 0.68% 99.78% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 257 0.15% 99.94% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iq.issued_per_cycle::total 171052 # Number of insts issued each cycle
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iq.fu_full::IntAlu 17 6.05% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 54 19.22% 25.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 210 74.73% 100.00% # attempts to use FU when none available
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iq.FU_type_0::IntAlu 130533 47.58% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.58% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 97787 35.65% 83.23% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 45999 16.77% 100.00% # Type of FU issued
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iq.FU_type_0::total 274319 # Type of FU issued
system.cpu1.iq.rate 1.550964 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 281 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.001024 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 720057 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 288914 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 272470 # Number of integer instruction queue wakeup accesses
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iq.int_alu_accesses 274600 # Number of integer alu accesses
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iew.lsq.thread0.forwLoads 41423 # Number of loads that had data forwarded from stores
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iew.lsq.thread0.squashedLoads 2326 # Number of loads squashed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 1418 # Number of stores squashed
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iew.iewSquashCycles 2318 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 743 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 324068 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 389 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 95375 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 46677 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 1041 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 463 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 924 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 1387 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 273134 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 94466 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 1185 # Number of squashed instructions skipped in execute
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iew.exec_nop 45766 # number of nop insts executed
system.cpu1.iew.exec_refs 140389 # number of memory reference insts executed
system.cpu1.iew.exec_branches 55097 # Number of branches executed
system.cpu1.iew.exec_stores 45923 # Number of stores executed
system.cpu1.iew.exec_rate 1.544264 # Inst execution rate
system.cpu1.iew.wb_sent 272765 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 272470 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 157153 # num instructions producing a value
system.cpu1.iew.wb_consumers 161823 # num instructions consuming a value
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iew.wb_rate 1.540510 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.971141 # average fanout of values written-back
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.commit.commitSquashedInsts 12117 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 3751 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 1274 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 161408 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 1.932674 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 2.096378 # Number of insts commited each cycle
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.commit.committed_per_cycle::0 51564 31.95% 31.95% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 53244 32.99% 64.93% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 6086 3.77% 68.70% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 4696 2.91% 71.61% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 1571 0.97% 72.59% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 41954 25.99% 98.58% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 476 0.29% 98.87% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 816 0.51% 100.00% # Number of insts commited each cycle
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.commit.committed_per_cycle::total 161408 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 311949 # Number of instructions committed
system.cpu1.commit.committedOps 311949 # Number of ops (including micro ops) committed
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.commit.refs 138308 # Number of memory references committed
system.cpu1.commit.loads 93049 # Number of loads committed
system.cpu1.commit.membars 3038 # Number of memory barriers committed
system.cpu1.commit.branches 54264 # Number of branches committed
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.commit.int_insts 214693 # Number of committed integer instructions.
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.commit.function_calls 322 # Number of function calls committed.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.commit.bw_lim_events 816 # number cycles where commit BW limit reached
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.rob.rob_reads 484071 # The number of ROB reads
system.cpu1.rob.rob_writes 650455 # The number of ROB writes
system.cpu1.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 5818 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 43818 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 263856 # Number of Instructions Simulated
system.cpu1.committedOps 263856 # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total 263856 # Number of Instructions Simulated
system.cpu1.cpi 0.670328 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 0.670328 # CPI: Total CPI of All Threads
system.cpu1.ipc 1.491808 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 1.491808 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 479823 # number of integer regfile reads
system.cpu1.int_regfile_writes 223101 # number of integer regfile writes
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.misc_regfile_reads 141972 # number of misc regfile reads
regressions: stats update due to decoder changes
2013-01-05 02:00:48 +01:00
system.cpu1.misc_regfile_writes 648 # number of misc regfile writes
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu1.icache.replacements 317 # number of replacements
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.icache.tagsinuse 82.334562 # Cycle average of tags in use
system.cpu1.icache.total_refs 15036 # Total number of references to valid blocks.
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu1.icache.sampled_refs 425 # Sample count of references to valid blocks.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.icache.avg_refs 35.378824 # Average number of references to valid blocks.
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.icache.occ_blocks::cpu1.inst 82.334562 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.160810 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.160810 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 15036 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 15036 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 15036 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 15036 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 15036 # number of overall hits
system.cpu1.icache.overall_hits::total 15036 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 487 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 487 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 487 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 487 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 487 # number of overall misses
system.cpu1.icache.overall_misses::total 487 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 12109000 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 12109000 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 12109000 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 12109000 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 12109000 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 12109000 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 15523 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 15523 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 15523 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 15523 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 15523 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 15523 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.031373 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.031373 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.031373 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.031373 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.031373 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.031373 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24864.476386 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 24864.476386 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24864.476386 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 24864.476386 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24864.476386 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 24864.476386 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 84 # number of cycles access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.icache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 62 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 62 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 62 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 62 # number of overall MSHR hits
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 425 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 425 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 425 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 425 # number of overall MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 9721502 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 9721502 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 9721502 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 9721502 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 9721502 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 9721502 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027379 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027379 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027379 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.027379 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027379 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.027379 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22874.122353 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22874.122353 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22874.122353 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 22874.122353 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22874.122353 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 22874.122353 # average overall mshr miss latency
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu1.dcache.replacements 0 # number of replacements
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dcache.tagsinuse 26.168894 # Cycle average of tags in use
system.cpu1.dcache.total_refs 51272 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 1831.142857 # Average number of references to valid blocks.
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dcache.occ_blocks::cpu1.data 26.168894 # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data 0.051111 # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total 0.051111 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 52686 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 52686 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 45050 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 45050 # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data 97736 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 97736 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 97736 # number of overall hits
system.cpu1.dcache.overall_hits::total 97736 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 340 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 340 # number of ReadReq misses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.dcache.WriteReq_misses::cpu1.data 142 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 142 # number of WriteReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data 482 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 482 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 482 # number of overall misses
system.cpu1.dcache.overall_misses::total 482 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5254500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 5254500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3040000 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 3040000 # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 532000 # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total 532000 # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 8294500 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 8294500 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 8294500 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 8294500 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 53026 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 53026 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 45192 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 45192 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data 67 # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 98218 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 98218 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 98218 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 98218 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.006412 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.006412 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003142 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.003142 # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.835821 # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total 0.835821 # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004907 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.004907 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004907 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.004907 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15454.411765 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15454.411765 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21408.450704 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 21408.450704 # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9500 # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::total 9500 # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17208.506224 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 17208.506224 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17208.506224 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 17208.506224 # average overall miss latency
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 185 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 185 # number of ReadReq MSHR hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dcache.demand_mshr_hits::cpu1.data 219 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 219 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 219 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 219 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 155 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1346027 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1346027 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1452501 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1452501 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 420000 # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total 420000 # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2798528 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 2798528 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2798528 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 2798528 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002923 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002923 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002390 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002390 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.835821 # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.835821 # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002678 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.002678 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002678 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.002678 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 8684.045161 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 8684.045161 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13449.083333 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13449.083333 # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7500 # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7500 # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 10640.790875 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 10640.790875 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 10640.790875 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 10640.790875 # average overall mshr miss latency
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.branchPred.lookups 40256 # Number of BP lookups
system.cpu2.branchPred.condPredicted 37554 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 1244 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 34216 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 33404 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.branchPred.BTBHitPct 97.626841 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 656 # Number of times the RAS was used to get a target.
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.numCycles 176505 # number of cpu cycles simulated
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.fetch.icacheStallCycles 35945 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 212693 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 40256 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 34060 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 82824 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 3666 # Number of cycles fetch has spent squashing
system.cpu2.fetch.BlockedCycles 45362 # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.NoActiveThreadStallCycles 7326 # Number of stall cycles due to no active thread to fetch from
system.cpu2.fetch.PendingTrapStallCycles 778 # Number of stall cycles due to pending traps
system.cpu2.fetch.CacheLines 27473 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 251 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples 174585 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.218278 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 1.916616 # Number of instructions fetched each cycle (Total)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.fetch.rateDist::0 91761 52.56% 52.56% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 44191 25.31% 77.87% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 10007 5.73% 83.60% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 3161 1.81% 85.41% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 734 0.42% 85.83% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 19642 11.25% 97.09% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 1038 0.59% 97.68% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 777 0.45% 98.12% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 3274 1.88% 100.00% # Number of instructions fetched each cycle (Total)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.fetch.rateDist::total 174585 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.228073 # Number of branch fetches per cycle
system.cpu2.fetch.rate 1.205025 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 44684 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 38236 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 73287 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 8707 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 2345 # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts 209159 # Number of instructions handled by decode
system.cpu2.rename.SquashCycles 2345 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 45347 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 25711 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 11752 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 64880 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 17224 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 207132 # Number of instructions processed by rename
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.rename.LSQFullEvents 18 # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RenamedOperands 141115 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 375802 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 375802 # Number of integer rename lookups
system.cpu2.rename.CommittedMaps 128666 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 12449 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 1089 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 1217 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 19740 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 53610 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 22854 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 26965 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 17848 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 166370 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 10183 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 172186 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 129 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 10670 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 10572 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 668 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 174585 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 0.986259 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 1.235789 # Number of insts issued each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iq.issued_per_cycle::0 89355 51.18% 51.18% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 33684 19.29% 70.48% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 23026 13.19% 83.66% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 23727 13.59% 97.25% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 3246 1.86% 99.11% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 1164 0.67% 99.78% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 273 0.16% 99.94% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iq.issued_per_cycle::total 174585 # Number of insts issued each cycle
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iq.fu_full::IntAlu 12 4.35% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 54 19.57% 23.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 210 76.09% 100.00% # attempts to use FU when none available
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iq.FU_type_0::IntAlu 88373 51.32% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.32% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 61586 35.77% 87.09% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 22227 12.91% 100.00% # Type of FU issued
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iq.FU_type_0::total 172186 # Type of FU issued
system.cpu2.iq.rate 0.975530 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 276 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.001603 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 519362 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 187269 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 170462 # Number of integer instruction queue wakeup accesses
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iq.int_alu_accesses 172462 # Number of integer alu accesses
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iew.lsq.thread0.forwLoads 17592 # Number of loads that had data forwarded from stores
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iew.lsq.thread0.squashedLoads 2439 # Number of loads squashed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu2.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iew.lsq.thread0.squashedStores 1401 # Number of stores squashed
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iew.iewSquashCycles 2345 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 684 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 40 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 204373 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 344 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 53610 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 22854 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu2.iew.memOrderViolationEvents 46 # Number of memory order violations
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iew.predictedTakenIncorrect 451 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 900 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 1351 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 171090 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 52536 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 1096 # Number of squashed instructions skipped in execute
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.iew.exec_swp 0 # number of swp insts executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iew.exec_nop 27820 # number of nop insts executed
system.cpu2.iew.exec_refs 74679 # number of memory reference insts executed
system.cpu2.iew.exec_branches 36982 # Number of branches executed
system.cpu2.iew.exec_stores 22143 # Number of stores executed
system.cpu2.iew.exec_rate 0.969321 # Inst execution rate
system.cpu2.iew.wb_sent 170734 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 170462 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 91387 # num instructions producing a value
system.cpu2.iew.wb_consumers 96059 # num instructions consuming a value
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iew.wb_rate 0.965763 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.951363 # average fanout of values written-back
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.commit.commitSquashedInsts 12267 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 9515 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 1244 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 164914 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 1.164777 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 1.788510 # Number of insts commited each cycle
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.commit.committed_per_cycle::0 91274 55.35% 55.35% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 35097 21.28% 76.63% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 6075 3.68% 80.31% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 10441 6.33% 86.64% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 1560 0.95% 87.59% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 18154 11.01% 98.60% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 495 0.30% 98.90% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 1006 0.61% 99.51% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 812 0.49% 100.00% # Number of insts commited each cycle
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.commit.committed_per_cycle::total 164914 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 192088 # Number of instructions committed
system.cpu2.commit.committedOps 192088 # Number of ops (including micro ops) committed
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.commit.refs 72624 # Number of memory references committed
system.cpu2.commit.loads 51171 # Number of loads committed
system.cpu2.commit.membars 8798 # Number of memory barriers committed
system.cpu2.commit.branches 36206 # Number of branches committed
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.commit.int_insts 130952 # Number of committed integer instructions.
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.commit.function_calls 322 # Number of function calls committed.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.commit.bw_lim_events 812 # number cycles where commit BW limit reached
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.rob.rob_reads 367870 # The number of ROB reads
system.cpu2.rob.rob_writes 411061 # The number of ROB writes
system.cpu2.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 1920 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 44183 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 156297 # Number of Instructions Simulated
system.cpu2.committedOps 156297 # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total 156297 # Number of Instructions Simulated
system.cpu2.cpi 1.129292 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 1.129292 # CPI: Total CPI of All Threads
system.cpu2.ipc 0.885510 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 0.885510 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 282509 # number of integer regfile reads
system.cpu2.int_regfile_writes 133289 # number of integer regfile writes
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.misc_regfile_reads 76201 # number of misc regfile reads
regressions: stats update due to decoder changes
2013-01-05 02:00:48 +01:00
system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.icache.replacements 318 # number of replacements
system.cpu2.icache.tagsinuse 76.657940 # Cycle average of tags in use
system.cpu2.icache.total_refs 26999 # Total number of references to valid blocks.
system.cpu2.icache.sampled_refs 428 # Sample count of references to valid blocks.
system.cpu2.icache.avg_refs 63.081776 # Average number of references to valid blocks.
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.icache.occ_blocks::cpu2.inst 76.657940 # Average occupied blocks per requestor
system.cpu2.icache.occ_percent::cpu2.inst 0.149723 # Average percentage of cache occupancy
system.cpu2.icache.occ_percent::total 0.149723 # Average percentage of cache occupancy
system.cpu2.icache.ReadReq_hits::cpu2.inst 26999 # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total 26999 # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst 26999 # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total 26999 # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst 26999 # number of overall hits
system.cpu2.icache.overall_hits::total 26999 # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst 474 # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total 474 # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst 474 # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total 474 # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst 474 # number of overall misses
system.cpu2.icache.overall_misses::total 474 # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6632500 # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total 6632500 # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst 6632500 # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total 6632500 # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst 6632500 # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total 6632500 # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst 27473 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total 27473 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst 27473 # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total 27473 # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst 27473 # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total 27473 # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.017253 # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total 0.017253 # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.017253 # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total 0.017253 # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.017253 # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total 0.017253 # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13992.616034 # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_miss_latency::total 13992.616034 # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13992.616034 # average overall miss latency
system.cpu2.icache.demand_avg_miss_latency::total 13992.616034 # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13992.616034 # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::total 13992.616034 # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.icache.blocked::no_mshrs 2 # number of cycles access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.icache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 46 # number of ReadReq MSHR hits
system.cpu2.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits
system.cpu2.icache.demand_mshr_hits::cpu2.inst 46 # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits
system.cpu2.icache.overall_mshr_hits::cpu2.inst 46 # number of overall MSHR hits
system.cpu2.icache.overall_mshr_hits::total 46 # number of overall MSHR hits
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 428 # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst 428 # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst 428 # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total 428 # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5331008 # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total 5331008 # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5331008 # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total 5331008 # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5331008 # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total 5331008 # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.015579 # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.015579 # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.015579 # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total 0.015579 # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.015579 # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total 0.015579 # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12455.626168 # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12455.626168 # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12455.626168 # average overall mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::total 12455.626168 # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12455.626168 # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 12455.626168 # average overall mshr miss latency
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu2.dcache.replacements 0 # number of replacements
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.dcache.tagsinuse 23.628047 # Cycle average of tags in use
system.cpu2.dcache.total_refs 27574 # Total number of references to valid blocks.
system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks.
system.cpu2.dcache.avg_refs 950.827586 # Average number of references to valid blocks.
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.dcache.occ_blocks::cpu2.data 23.628047 # Average occupied blocks per requestor
system.cpu2.dcache.occ_percent::cpu2.data 0.046149 # Average percentage of cache occupancy
system.cpu2.dcache.occ_percent::total 0.046149 # Average percentage of cache occupancy
system.cpu2.dcache.ReadReq_hits::cpu2.data 34611 # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total 34611 # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data 21248 # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total 21248 # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data 17 # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total 17 # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data 55859 # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total 55859 # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data 55859 # number of overall hits
system.cpu2.dcache.overall_hits::total 55859 # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data 317 # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total 317 # number of ReadReq misses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu2.dcache.WriteReq_misses::cpu2.data 134 # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total 134 # number of WriteReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data 451 # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total 451 # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data 451 # number of overall misses
system.cpu2.dcache.overall_misses::total 451 # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3712500 # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total 3712500 # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2774500 # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total 2774500 # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 533000 # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total 533000 # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data 6487000 # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total 6487000 # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data 6487000 # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total 6487000 # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data 34928 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total 34928 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data 21382 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total 21382 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data 56310 # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total 56310 # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data 56310 # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total 56310 # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009076 # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total 0.009076 # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006267 # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total 0.006267 # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.760563 # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total 0.760563 # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008009 # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total 0.008009 # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008009 # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total 0.008009 # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 11711.356467 # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_miss_latency::total 11711.356467 # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20705.223881 # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::total 20705.223881 # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9870.370370 # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::total 9870.370370 # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14383.592018 # average overall miss latency
system.cpu2.dcache.demand_avg_miss_latency::total 14383.592018 # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14383.592018 # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::total 14383.592018 # average overall miss latency
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 156 # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_hits::total 156 # number of ReadReq MSHR hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 33 # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.dcache.demand_mshr_hits::cpu2.data 189 # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_hits::total 189 # number of demand (read+write) MSHR hits
system.cpu2.dcache.overall_mshr_hits::cpu2.data 189 # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_hits::total 189 # number of overall MSHR hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 54 # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1142519 # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1142519 # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1333500 # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1333500 # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 425000 # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total 425000 # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2476019 # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total 2476019 # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2476019 # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total 2476019 # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004609 # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004609 # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.004724 # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.004724 # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.760563 # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.760563 # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004653 # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_miss_rate::total 0.004653 # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004653 # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total 0.004653 # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 7096.391304 # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 7096.391304 # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13202.970297 # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13202.970297 # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7870.370370 # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7870.370370 # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9450.454198 # average overall mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9450.454198 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9450.454198 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9450.454198 # average overall mshr miss latency
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.branchPred.lookups 52069 # Number of BP lookups
system.cpu3.branchPred.condPredicted 49356 # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect 1283 # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups 46005 # Number of BTB lookups
system.cpu3.branchPred.BTBHits 45233 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.branchPred.BTBHitPct 98.321922 # BTB Hit Percentage
system.cpu3.branchPred.usedRAS 642 # Number of times the RAS was used to get a target.
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.numCycles 176161 # number of cpu cycles simulated
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.fetch.icacheStallCycles 28821 # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts 290359 # Number of instructions fetch has processed
system.cpu3.fetch.Branches 52069 # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches 45875 # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles 102938 # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles 3745 # Number of cycles fetch has spent squashing
system.cpu3.fetch.BlockedCycles 32453 # Number of cycles fetch has spent blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.fetch.NoActiveThreadStallCycles 7327 # Number of stall cycles due to no active thread to fetch from
system.cpu3.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps
system.cpu3.fetch.CacheLines 20536 # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes 262 # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.rateDist::samples 174715 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean 1.661901 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev 2.131946 # Number of instructions fetched each cycle (Total)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.fetch.rateDist::0 71777 41.08% 41.08% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1 52540 30.07% 71.15% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2 6531 3.74% 74.89% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3 3210 1.84% 76.73% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4 677 0.39% 77.12% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5 34730 19.88% 97.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6 1243 0.71% 97.71% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7 745 0.43% 98.13% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8 3262 1.87% 100.00% # Number of instructions fetched each cycle (Total)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.fetch.rateDist::total 174715 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate 0.295576 # Number of branch fetches per cycle
system.cpu3.fetch.rate 1.648259 # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles 34404 # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles 28518 # Number of cycles decode is blocked
system.cpu3.decode.RunCycles 96588 # Number of cycles decode is running
system.cpu3.decode.UnblockCycles 5492 # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles 2386 # Number of cycles decode is squashing
system.cpu3.decode.DecodedInsts 286754 # Number of instructions handled by decode
system.cpu3.rename.SquashCycles 2386 # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles 35116 # Number of cycles rename is idle
system.cpu3.rename.BlockCycles 15951 # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles 11812 # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles 91334 # Number of cycles rename is running
system.cpu3.rename.UnblockCycles 10789 # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts 284513 # Number of instructions processed by rename
system.cpu3.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full
system.cpu3.rename.LSQFullEvents 22 # Number of times rename has blocked due to LSQ full
system.cpu3.rename.RenamedOperands 198512 # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups 543834 # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups 543834 # Number of integer rename lookups
system.cpu3.rename.CommittedMaps 185460 # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps 13052 # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts 1098 # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts 1218 # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts 13448 # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads 80352 # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores 37945 # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads 38583 # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores 32886 # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded 235223 # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded 6760 # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued 237671 # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined 10910 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined 10900 # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved 576 # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples 174715 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean 1.360335 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev 1.308190 # Number of insts issued each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.iq.issued_per_cycle::0 69245 39.63% 39.63% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1 23718 13.58% 53.21% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2 38151 21.84% 75.04% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3 38808 22.21% 97.26% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4 3275 1.87% 99.13% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5 1152 0.66% 99.79% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6 254 0.15% 99.94% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.iq.issued_per_cycle::total 174715 # Number of insts issued each cycle
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.iq.fu_full::IntAlu 17 5.94% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 5.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead 59 20.63% 26.57% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite 210 73.43% 100.00% # attempts to use FU when none available
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.iq.FU_type_0::IntAlu 115348 48.53% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.53% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead 85085 35.80% 84.33% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite 37238 15.67% 100.00% # Type of FU issued
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.iq.FU_type_0::total 237671 # Type of FU issued
system.cpu3.iq.rate 1.349169 # Inst issue rate
system.cpu3.iq.fu_busy_cnt 286 # FU busy when requested
system.cpu3.iq.fu_busy_rate 0.001203 # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads 650461 # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes 252939 # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses 235820 # Number of integer instruction queue wakeup accesses
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.iq.int_alu_accesses 237957 # Number of integer alu accesses
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.iew.lsq.thread0.forwLoads 32638 # Number of loads that had data forwarded from stores
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.iew.lsq.thread0.squashedLoads 2448 # Number of loads squashed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores 1468 # Number of stores squashed
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.iew.iewSquashCycles 2386 # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles 609 # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts 281506 # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts 366 # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts 80352 # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts 37945 # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.iew.memOrderViolationEvents 46 # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect 925 # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts 1395 # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts 236476 # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts 79331 # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts 1195 # Number of squashed instructions skipped in execute
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.iew.exec_swp 0 # number of swp insts executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.iew.exec_nop 39523 # number of nop insts executed
system.cpu3.iew.exec_refs 116486 # number of memory reference insts executed
system.cpu3.iew.exec_branches 48746 # Number of branches executed
system.cpu3.iew.exec_stores 37155 # Number of stores executed
system.cpu3.iew.exec_rate 1.342386 # Inst execution rate
system.cpu3.iew.wb_sent 236114 # cumulative count of insts sent to commit
system.cpu3.iew.wb_count 235820 # cumulative count of insts written-back
system.cpu3.iew.wb_producers 133214 # num instructions producing a value
system.cpu3.iew.wb_consumers 137877 # num instructions consuming a value
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.iew.wb_rate 1.338662 # insts written-back per cycle
system.cpu3.iew.wb_fanout 0.966180 # average fanout of values written-back
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.commit.commitSquashedInsts 12531 # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls 6184 # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts 1283 # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples 165002 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean 1.630011 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev 2.014402 # Number of insts commited each cycle
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.commit.committed_per_cycle::0 67849 41.12% 41.12% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1 46915 28.43% 69.55% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2 6084 3.69% 73.24% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3 7112 4.31% 77.55% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4 1576 0.96% 78.51% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5 33196 20.12% 98.62% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6 454 0.28% 98.90% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7 1000 0.61% 99.51% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8 816 0.49% 100.00% # Number of insts commited each cycle
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.commit.committed_per_cycle::total 165002 # Number of insts commited each cycle
system.cpu3.commit.committedInsts 268955 # Number of instructions committed
system.cpu3.commit.committedOps 268955 # Number of ops (including micro ops) committed
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.commit.refs 114381 # Number of memory references committed
system.cpu3.commit.loads 77904 # Number of loads committed
system.cpu3.commit.membars 5468 # Number of memory barriers committed
system.cpu3.commit.branches 47910 # Number of branches committed
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.commit.int_insts 184410 # Number of committed integer instructions.
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.commit.function_calls 322 # Number of function calls committed.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.commit.bw_lim_events 816 # number cycles where commit BW limit reached
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.rob.rob_reads 445085 # The number of ROB reads
system.cpu3.rob.rob_writes 565364 # The number of ROB writes
system.cpu3.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles 1446 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles 44527 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts 224789 # Number of Instructions Simulated
system.cpu3.committedOps 224789 # Number of Ops (including micro ops) Simulated
system.cpu3.committedInsts_total 224789 # Number of Instructions Simulated
system.cpu3.cpi 0.783673 # CPI: Cycles Per Instruction
system.cpu3.cpi_total 0.783673 # CPI: Total CPI of All Threads
system.cpu3.ipc 1.276043 # IPC: Instructions Per Cycle
system.cpu3.ipc_total 1.276043 # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads 408025 # number of integer regfile reads
system.cpu3.int_regfile_writes 190344 # number of integer regfile writes
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.misc_regfile_reads 118055 # number of misc regfile reads
regressions: stats update due to decoder changes
2013-01-05 02:00:48 +01:00
system.cpu3.misc_regfile_writes 648 # number of misc regfile writes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.icache.replacements 319 # number of replacements
system.cpu3.icache.tagsinuse 80.505037 # Cycle average of tags in use
system.cpu3.icache.total_refs 20059 # Total number of references to valid blocks.
system.cpu3.icache.sampled_refs 430 # Sample count of references to valid blocks.
system.cpu3.icache.avg_refs 46.648837 # Average number of references to valid blocks.
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.icache.occ_blocks::cpu3.inst 80.505037 # Average occupied blocks per requestor
system.cpu3.icache.occ_percent::cpu3.inst 0.157236 # Average percentage of cache occupancy
system.cpu3.icache.occ_percent::total 0.157236 # Average percentage of cache occupancy
system.cpu3.icache.ReadReq_hits::cpu3.inst 20059 # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total 20059 # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst 20059 # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total 20059 # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst 20059 # number of overall hits
system.cpu3.icache.overall_hits::total 20059 # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst 477 # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total 477 # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst 477 # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total 477 # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst 477 # number of overall misses
system.cpu3.icache.overall_misses::total 477 # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6428500 # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total 6428500 # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst 6428500 # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total 6428500 # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst 6428500 # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total 6428500 # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst 20536 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total 20536 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst 20536 # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total 20536 # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst 20536 # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total 20536 # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023228 # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total 0.023228 # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023228 # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total 0.023228 # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023228 # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total 0.023228 # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13476.939203 # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_miss_latency::total 13476.939203 # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13476.939203 # average overall miss latency
system.cpu3.icache.demand_avg_miss_latency::total 13476.939203 # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13476.939203 # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::total 13476.939203 # average overall miss latency
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 47 # number of ReadReq MSHR hits
system.cpu3.icache.ReadReq_mshr_hits::total 47 # number of ReadReq MSHR hits
system.cpu3.icache.demand_mshr_hits::cpu3.inst 47 # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_hits::total 47 # number of demand (read+write) MSHR hits
system.cpu3.icache.overall_mshr_hits::cpu3.inst 47 # number of overall MSHR hits
system.cpu3.icache.overall_mshr_hits::total 47 # number of overall MSHR hits
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 430 # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst 430 # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst 430 # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total 430 # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5181004 # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total 5181004 # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5181004 # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total 5181004 # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5181004 # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total 5181004 # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020939 # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020939 # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020939 # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_miss_rate::total 0.020939 # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020939 # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_miss_rate::total 0.020939 # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12048.846512 # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12048.846512 # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12048.846512 # average overall mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::total 12048.846512 # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12048.846512 # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 12048.846512 # average overall mshr miss latency
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu3.dcache.replacements 0 # number of replacements
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.dcache.tagsinuse 24.780818 # Cycle average of tags in use
system.cpu3.dcache.total_refs 42491 # Total number of references to valid blocks.
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.dcache.avg_refs 1517.535714 # Average number of references to valid blocks.
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.dcache.occ_blocks::cpu3.data 24.780818 # Average occupied blocks per requestor
system.cpu3.dcache.occ_percent::cpu3.data 0.048400 # Average percentage of cache occupancy
system.cpu3.dcache.occ_percent::total 0.048400 # Average percentage of cache occupancy
system.cpu3.dcache.ReadReq_hits::cpu3.data 46335 # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total 46335 # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data 36269 # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total 36269 # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data 82604 # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total 82604 # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data 82604 # number of overall hits
system.cpu3.dcache.overall_hits::total 82604 # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data 340 # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total 340 # number of ReadReq misses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu3.dcache.WriteReq_misses::cpu3.data 138 # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total 138 # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.dcache.demand_misses::cpu3.data 478 # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total 478 # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data 478 # number of overall misses
system.cpu3.dcache.overall_misses::total 478 # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4247000 # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total 4247000 # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2709000 # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total 2709000 # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 548500 # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total 548500 # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data 6956000 # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total 6956000 # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data 6956000 # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total 6956000 # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data 46675 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total 46675 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data 36407 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total 36407 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data 83082 # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total 83082 # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data 83082 # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total 83082 # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.007284 # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total 0.007284 # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003790 # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total 0.003790 # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.828571 # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total 0.828571 # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005753 # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total 0.005753 # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005753 # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total 0.005753 # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12491.176471 # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_miss_latency::total 12491.176471 # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19630.434783 # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::total 19630.434783 # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9456.896552 # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total 9456.896552 # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14552.301255 # average overall miss latency
system.cpu3.dcache.demand_avg_miss_latency::total 14552.301255 # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14552.301255 # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::total 14552.301255 # average overall miss latency
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 182 # number of ReadReq MSHR hits
system.cpu3.dcache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits
system.cpu3.dcache.demand_mshr_hits::cpu3.data 215 # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits
system.cpu3.dcache.overall_mshr_hits::cpu3.data 215 # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_hits::total 215 # number of overall MSHR hits
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 158 # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.dcache.demand_mshr_misses::cpu3.data 263 # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data 263 # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1065020 # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1065020 # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1284501 # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1284501 # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 432500 # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total 432500 # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2349521 # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total 2349521 # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2349521 # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total 2349521 # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003385 # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003385 # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002884 # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002884 # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.828571 # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.828571 # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003166 # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_miss_rate::total 0.003166 # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003166 # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total 0.003166 # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6740.632911 # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6740.632911 # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12233.342857 # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12233.342857 # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7456.896552 # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7456.896552 # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 8933.539924 # average overall mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 8933.539924 # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 8933.539924 # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 8933.539924 # average overall mshr miss latency
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.replacements 0 # number of replacements
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.tagsinuse 416.873465 # Cycle average of tags in use
system.l2c.total_refs 1443 # Total number of references to valid blocks.
system.l2c.sampled_refs 526 # Sample count of references to valid blocks.
system.l2c.avg_refs 2.743346 # Average number of references to valid blocks.
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.occ_blocks::writebacks 0.799918 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 284.792904 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 58.372123 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 60.210015 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 5.411849 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.inst 2.383180 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.data 0.694731 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.inst 3.476542 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.data 0.732205 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.004346 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.000919 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.000083 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.inst 0.000036 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.inst 0.000053 # Average percentage of cache occupancy
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.occ_percent::total 0.006361 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.ReadReq_hits::cpu1.inst 343 # number of ReadReq hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_hits::cpu2.inst 417 # number of ReadReq hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_hits::cpu3.inst 422 # number of ReadReq hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_hits::total 1443 # number of ReadReq hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
system.l2c.Writeback_hits::total 1 # number of Writeback hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_hits::cpu0.inst 229 # number of demand (read+write) hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.demand_hits::cpu1.inst 343 # number of demand (read+write) hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_hits::cpu2.inst 417 # number of demand (read+write) hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_hits::cpu3.inst 422 # number of demand (read+write) hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_hits::total 1443 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 229 # number of overall hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.overall_hits::cpu1.inst 343 # number of overall hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_hits::cpu1.data 5 # number of overall hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_hits::cpu2.inst 417 # number of overall hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_hits::cpu2.data 11 # number of overall hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_hits::cpu3.inst 422 # number of overall hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_hits::cpu3.data 11 # number of overall hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_hits::total 1443 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 359 # number of ReadReq misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.ReadReq_misses::cpu1.inst 82 # number of ReadReq misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_misses::cpu2.inst 11 # number of ReadReq misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_misses::cpu3.inst 8 # number of ReadReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_misses::total 543 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 75 # number of UpgradeReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_misses::cpu0.inst 359 # number of demand (read+write) misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.demand_misses::cpu1.inst 82 # number of demand (read+write) misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_misses::cpu2.inst 11 # number of demand (read+write) misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_misses::cpu3.inst 8 # number of demand (read+write) misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_misses::total 674 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 359 # number of overall misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.overall_misses::cpu0.data 168 # number of overall misses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.overall_misses::cpu1.inst 82 # number of overall misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_misses::cpu1.data 20 # number of overall misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_misses::cpu2.inst 11 # number of overall misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_misses::cpu2.data 13 # number of overall misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_misses::cpu3.inst 8 # number of overall misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_misses::cpu3.data 13 # number of overall misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_misses::total 674 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst 24109000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 5458500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 5845000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 521000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst 717000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data 88500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.inst 521500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.data 88500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 37349000 # number of ReadReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 7419500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 1013000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 901500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data 851000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 10185000 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst 24109000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 12878000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 5845000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 1534000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst 717000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 990000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst 521500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data 939500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 47534000 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst 24109000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 12878000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 5845000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 1534000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 717000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 990000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst 521500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data 939500 # number of overall miss cycles
system.l2c.overall_miss_latency::total 47534000 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses)
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses)
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.l2c.ReadReq_accesses::cpu1.inst 425 # number of ReadReq accesses(hits+misses)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_accesses::cpu2.inst 428 # number of ReadReq accesses(hits+misses)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_accesses::cpu3.inst 430 # number of ReadReq accesses(hits+misses)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_accesses::total 1986 # number of ReadReq accesses(hits+misses)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 78 # number of UpgradeReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_accesses::cpu0.inst 588 # number of demand (read+write) accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.l2c.demand_accesses::cpu1.inst 425 # number of demand (read+write) accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_accesses::cpu2.inst 428 # number of demand (read+write) accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_accesses::cpu3.inst 430 # number of demand (read+write) accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_accesses::total 2117 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 588 # number of overall (read+write) accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.l2c.overall_accesses::cpu1.inst 425 # number of overall (read+write) accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_accesses::cpu2.inst 428 # number of overall (read+write) accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_accesses::cpu3.inst 430 # number of overall (read+write) accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_accesses::total 2117 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.610544 # miss rate for ReadReq accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.ReadReq_miss_rate::cpu1.inst 0.192941 # miss rate for ReadReq accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_miss_rate::cpu2.inst 0.025701 # miss rate for ReadReq accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_miss_rate::cpu3.inst 0.018605 # miss rate for ReadReq accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_miss_rate::total 0.273414 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.UpgradeReq_miss_rate::total 0.961538 # miss rate for UpgradeReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_miss_rate::cpu0.inst 0.610544 # miss rate for demand accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.demand_miss_rate::cpu1.inst 0.192941 # miss rate for demand accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_miss_rate::cpu2.inst 0.025701 # miss rate for demand accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_miss_rate::cpu3.inst 0.018605 # miss rate for demand accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_miss_rate::total 0.318375 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.610544 # miss rate for overall accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.overall_miss_rate::cpu1.inst 0.192941 # miss rate for overall accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_miss_rate::cpu2.inst 0.025701 # miss rate for overall accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_miss_rate::cpu3.inst 0.018605 # miss rate for overall accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_miss_rate::total 0.318375 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 67155.988858 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 73763.513514 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71280.487805 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 74428.571429 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 65181.818182 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 88500 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.inst 65187.500000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.data 88500 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 68782.688766 # average ReadReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 78930.851064 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77923.076923 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 75125 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 70916.666667 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 77748.091603 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 67155.988858 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 76654.761905 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 71280.487805 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 76700 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 65181.818182 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 76153.846154 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 65187.500000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 72269.230769 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 70525.222552 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 67155.988858 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 76654.761905 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 71280.487805 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 76700 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 65181.818182 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 76153.846154 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 65187.500000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 72269.230769 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 70525.222552 # average overall miss latency
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.l2c.fast_writes 0 # number of fast writes performed
Set up m5threads tests on classic (non-ruby) memory system. Just one test (40.m5threads-test-atomic) is set up for now. These tests require that the m5threads SPARC binaries are present in /dist or in test-progs.
2009-04-21 17:37:50 +02:00
system.l2c.cache_copies 0 # number of cache copies performed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_hits::cpu1.inst 2 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.inst 8 # number of ReadReq MSHR hits
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.ReadReq_mshr_hits::cpu3.inst 2 # number of ReadReq MSHR hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst 8 # number of demand (read+write) MSHR hits
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.demand_mshr_hits::cpu3.inst 2 # number of demand (read+write) MSHR hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst 8 # number of overall MSHR hits
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.overall_mshr_hits::cpu3.inst 2 # number of overall MSHR hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.overall_mshr_hits::total 14 # number of overall MSHR hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_misses::cpu0.inst 357 # number of ReadReq MSHR misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_misses::cpu1.inst 80 # number of ReadReq MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_misses::cpu2.inst 3 # number of ReadReq MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_misses::cpu3.inst 6 # number of ReadReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_misses::total 529 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 22 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 19 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data 16 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data 18 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 75 # number of UpgradeReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_misses::cpu0.inst 357 # number of demand (read+write) MSHR misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_misses::cpu1.inst 80 # number of demand (read+write) MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_misses::cpu2.inst 3 # number of demand (read+write) MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_misses::cpu3.inst 6 # number of demand (read+write) MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_misses::total 660 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 357 # number of overall MSHR misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_mshr_misses::cpu1.inst 80 # number of overall MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_mshr_misses::cpu2.inst 3 # number of overall MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_mshr_misses::cpu3.inst 6 # number of overall MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_mshr_misses::total 660 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 19614500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 4554750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 4712500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 435750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 181750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 76250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 368750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.data 76250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 30020500 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 220022 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 190019 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 169015 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 180018 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 759074 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6263250 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 854250 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 755250 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 703250 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 8576000 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 19614500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 10818000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 4712500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 1290000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 181750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 831500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst 368750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data 779500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 38596500 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 19614500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 10818000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 4712500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 1290000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 181750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 831500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst 368750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data 779500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 38596500 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for ReadReq accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for ReadReq accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.007009 # mshr miss rate for ReadReq accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for ReadReq accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_miss_rate::total 0.266365 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.UpgradeReq_mshr_miss_rate::total 0.961538 # mshr miss rate for UpgradeReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for demand accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for demand accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.007009 # mshr miss rate for demand accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for demand accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_miss_rate::total 0.311762 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for overall accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.007009 # mshr miss rate for overall accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for overall accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_mshr_miss_rate::total 0.311762 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 54942.577031 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61550.675676 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58906.250000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62250 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 60583.333333 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 76250 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 61458.333333 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 76250 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 56749.527410 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10563.437500 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10120.986667 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66630.319149 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65711.538462 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62937.500000 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 58604.166667 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 65465.648855 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 54942.577031 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64392.857143 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58906.250000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 60583.333333 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63961.538462 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61458.333333 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 59961.538462 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 58479.545455 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 54942.577031 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64392.857143 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58906.250000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 60583.333333 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63961.538462 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61458.333333 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 59961.538462 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 58479.545455 # average overall mshr miss latency
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
Set up m5threads tests on classic (non-ruby) memory system. Just one test (40.m5threads-test-atomic) is set up for now. These tests require that the m5threads SPARC binaries are present in /dist or in test-progs.
2009-04-21 17:37:50 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink