gem5/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

---------- Begin Simulation Statistics ----------
host_inst_rate                                 134273                       # Simulator instruction rate (inst/s)
host_mem_usage                                 216692                       # Number of bytes of host memory used
host_seconds                                     8.59                       # Real time elapsed on the host
host_tick_rate                               13675054                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                     1153138                       # Number of instructions simulated
sim_seconds                                  0.000117                       # Number of seconds simulated
sim_ticks                                   117445500                       # Number of ticks simulated
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.BTBHits                   89261                       # Number of BTB hits
system.cpu0.BPredUnit.BTBLookups                91887                       # Number of BTB lookups
system.cpu0.BPredUnit.RASInCorrect                  0                       # Number of incorrect RAS predictions.
system.cpu0.BPredUnit.condIncorrect              1075                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.condPredicted             92336                       # Number of conditional branches predicted
system.cpu0.BPredUnit.lookups                   92336                       # Number of BP lookups
system.cpu0.BPredUnit.usedRAS                       0                       # Number of times the RAS was used to get a target.
system.cpu0.commit.COM:branches                 89544                       # Number of branches committed
system.cpu0.commit.COM:bw_lim_events              223                       # number cycles where commit BW limit reached
system.cpu0.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
system.cpu0.commit.COM:committed_per_cycle::samples       214748                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::mean     2.488931                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::stdev     2.121519                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::0        33657     15.67%     15.67% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::1        90653     42.21%     57.89% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::2         2478      1.15%     59.04% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::3          734      0.34%     59.38% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::4          738      0.34%     59.73% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::5        85720     39.92%     99.64% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::6          469      0.22%     99.86% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::7           76      0.04%     99.90% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::8          223      0.10%    100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::total       214748                       # Number of insts commited each cycle
system.cpu0.commit.COM:count                   534493                       # Number of instructions committed
system.cpu0.commit.COM:fp_insts                     0                       # Number of committed floating point instructions.
system.cpu0.commit.COM:function_calls               0                       # Number of function calls committed.
system.cpu0.commit.COM:int_insts               359762                       # Number of committed integer instructions.
system.cpu0.commit.COM:loads                   174300                       # Number of loads committed
system.cpu0.commit.COM:membars                     84                       # Number of memory barriers committed
system.cpu0.commit.COM:refs                    261956                       # Number of memory references committed
system.cpu0.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
system.cpu0.commit.branchMispredicts             1075                       # The number of times a branch was mispredicted
system.cpu0.commit.commitCommittedInsts        534493                       # The number of committed instructions
system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.commitSquashedInsts           9438                       # The number of squashed insts skipped by commit
system.cpu0.committedInsts                     448134                       # Number of Instructions Simulated
system.cpu0.committedInsts_total               448134                       # Number of Instructions Simulated
system.cpu0.cpi                              0.524156                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        0.524156                       # CPI: Total CPI of All Threads
system.cpu0.dcache.ReadReq_accesses             89494                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_avg_miss_latency 27082.653061                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27751.366120                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_hits                 89004                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_miss_latency      13270500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_rate         0.005475                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_misses                 490                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_mshr_hits              307                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_miss_latency      5078500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate     0.002045                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_misses            183                       # number of ReadReq MSHR misses
system.cpu0.dcache.SwapReq_accesses                42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_avg_miss_latency 16923.076923                       # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 13923.076923                       # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_hits                    16                       # number of SwapReq hits
system.cpu0.dcache.SwapReq_miss_latency        440000                       # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_rate         0.619048                       # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_misses                  26                       # number of SwapReq misses
system.cpu0.dcache.SwapReq_mshr_miss_latency       362000                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_rate     0.619048                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_misses             26                       # number of SwapReq MSHR misses
system.cpu0.dcache.WriteReq_accesses            87614                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_avg_miss_latency 46112.007407                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 37114.942529                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_hits                87074                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_miss_latency     24900484                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_rate        0.006163                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_misses                540                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_mshr_hits             366                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_miss_latency      6458000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_rate     0.001986                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_misses           174                       # number of WriteReq MSHR misses
system.cpu0.dcache.avg_blocked_cycles::no_mshrs  8595.238095                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs                608.017241                       # Average number of references to valid blocks.
system.cpu0.dcache.blocked::no_mshrs               21                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_mshrs       180500                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.demand_accesses             177108                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_avg_miss_latency 37059.207767                       # average overall miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency 32315.126050                       # average overall mshr miss latency
system.cpu0.dcache.demand_hits                 176078                       # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency       38170984                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_rate          0.005816                       # miss rate for demand accesses
system.cpu0.dcache.demand_misses                 1030                       # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits               673                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency     11536500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_rate     0.002016                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_misses             357                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.occ_%::0                  0.275966                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_%::1                 -0.002190                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_blocks::0           141.294426                       # Average occupied blocks per context
system.cpu0.dcache.occ_blocks::1            -1.121239                       # Average occupied blocks per context
system.cpu0.dcache.overall_accesses            177108                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency 37059.207767                       # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency 32315.126050                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_hits                176078                       # number of overall hits
system.cpu0.dcache.overall_miss_latency      38170984                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_rate         0.005816                       # miss rate for overall accesses
system.cpu0.dcache.overall_misses                1030                       # number of overall misses
system.cpu0.dcache.overall_mshr_hits              673                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency     11536500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_rate     0.002016                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_misses            357                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.replacements                     9                       # number of replacements
system.cpu0.dcache.sampled_refs                   174                       # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.dcache.tagsinuse               140.173187                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                  105795                       # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks                       6                       # number of writebacks
system.cpu0.decode.DECODE:BlockedCycles         13474                       # Number of cycles decode is blocked
system.cpu0.decode.DECODE:DecodedInsts         548904                       # Number of instructions handled by decode
system.cpu0.decode.DECODE:IdleCycles            20013                       # Number of cycles decode is idle
system.cpu0.decode.DECODE:RunCycles            181043                       # Number of cycles decode is running
system.cpu0.decode.DECODE:SquashCycles           2044                       # Number of cycles decode is squashing
system.cpu0.decode.DECODE:UnblockCycles           201                       # Number of cycles decode is unblocking
system.cpu0.fetch.Branches                      92336                       # Number of branches that fetch encountered
system.cpu0.fetch.CacheLines                     5242                       # Number of cache lines fetched
system.cpu0.fetch.Cycles                       181487                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.IcacheSquashes                  476                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.Insts                        549904                       # Number of instructions fetch has processed
system.cpu0.fetch.MiscStallCycles                  41                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.SquashCycles                   1222                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.branchRate                 0.393100                       # Number of branch fetches per cycle
system.cpu0.fetch.icacheStallCycles              5242                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.predictedBranches             89261                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.rate                       2.341093                       # Number of inst fetches per cycle
system.cpu0.fetch.rateDist::samples            216775                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             2.536750                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.186468                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                   35288     16.28%     16.28% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                   90175     41.60%     57.88% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                     487      0.22%     58.10% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                     807      0.37%     58.47% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                     586      0.27%     58.74% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                   86536     39.92%     98.66% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                     826      0.38%     99.05% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                     206      0.10%     99.14% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                    1864      0.86%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total              216775                       # Number of instructions fetched each cycle (Total)
system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
system.cpu0.icache.ReadReq_accesses              5242                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_avg_miss_latency 39013.262599                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36995.894910                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_hits                  4488                       # number of ReadReq hits
system.cpu0.icache.ReadReq_miss_latency      29416000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_rate         0.143838                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_misses                 754                       # number of ReadReq misses
system.cpu0.icache.ReadReq_mshr_hits              145                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_miss_latency     22530500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate     0.116177                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_misses            609                       # number of ReadReq MSHR misses
system.cpu0.icache.avg_blocked_cycles::no_mshrs        11000                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.icache.avg_refs                  7.381579                       # Average number of references to valid blocks.
system.cpu0.icache.blocked::no_mshrs                2                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_mshrs        22000                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.demand_accesses               5242                       # number of demand (read+write) accesses
system.cpu0.icache.demand_avg_miss_latency 39013.262599                       # average overall miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency 36995.894910                       # average overall mshr miss latency
system.cpu0.icache.demand_hits                   4488                       # number of demand (read+write) hits
system.cpu0.icache.demand_miss_latency       29416000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_rate          0.143838                       # miss rate for demand accesses
system.cpu0.icache.demand_misses                  754                       # number of demand (read+write) misses
system.cpu0.icache.demand_mshr_hits               145                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_miss_latency     22530500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_rate     0.116177                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_misses             609                       # number of demand (read+write) MSHR misses
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.occ_%::0                  0.502878                       # Average percentage of cache occupancy
system.cpu0.icache.occ_blocks::0           257.473705                       # Average occupied blocks per context
system.cpu0.icache.overall_accesses              5242                       # number of overall (read+write) accesses
system.cpu0.icache.overall_avg_miss_latency 39013.262599                       # average overall miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency 36995.894910                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_hits                  4488                       # number of overall hits
system.cpu0.icache.overall_miss_latency      29416000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_rate         0.143838                       # miss rate for overall accesses
system.cpu0.icache.overall_misses                 754                       # number of overall misses
system.cpu0.icache.overall_mshr_hits              145                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_miss_latency     22530500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_rate     0.116177                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_misses            609                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.icache.replacements                   307                       # number of replacements
system.cpu0.icache.sampled_refs                   608                       # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.icache.tagsinuse               257.473705                       # Cycle average of tags in use
system.cpu0.icache.total_refs                    4488                       # Total number of references to valid blocks.
system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks                       0                       # number of writebacks
system.cpu0.idleCycles                          18117                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.iew.EXEC:branches                   90345                       # Number of branches executed
system.cpu0.iew.EXEC:nop                        86733                       # number of nop insts executed
system.cpu0.iew.EXEC:rate                    1.932437                       # Inst execution rate
system.cpu0.iew.EXEC:refs                      263598                       # number of memory reference insts executed
system.cpu0.iew.EXEC:stores                     88173                       # Number of stores executed
system.cpu0.iew.EXEC:swp                            0                       # number of swp insts executed
system.cpu0.iew.WB:consumers                   270902                       # num instructions consuming a value
system.cpu0.iew.WB:count                       453315                       # cumulative count of insts written-back
system.cpu0.iew.WB:fanout                    0.992949                       # average fanout of values written-back
system.cpu0.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.iew.WB:producers                   268992                       # num instructions producing a value
system.cpu0.iew.WB:rate                      1.929887                       # insts written-back per cycle
system.cpu0.iew.WB:sent                        453561                       # cumulative count of insts sent to commit
system.cpu0.iew.branchMispredicts                1242                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewBlockCycles                    823                       # Number of cycles IEW is blocking
system.cpu0.iew.iewDispLoadInsts               175971                       # Number of dispatched load instructions
system.cpu0.iew.iewDispNonSpecInsts               722                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewDispSquashedInsts              481                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispStoreInsts               88710                       # Number of dispatched store instructions
system.cpu0.iew.iewDispatchedInsts             543927                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewExecLoadInsts               175425                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts              910                       # Number of squashed instructions skipped in execute
system.cpu0.iew.iewExecutedInsts               453914                       # Number of executed instructions
system.cpu0.iew.iewIQFullEvents                    24                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.iewSquashCycles                  2044                       # Number of cycles IEW is squashing
system.cpu0.iew.iewUnblockCycles                   27                       # Number of cycles IEW is unblocking
system.cpu0.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread.0.cacheBlocked           18                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.lsq.thread.0.forwLoads          85880                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread.0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread.0.memOrderViolation           44                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread.0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread.0.squashedLoads         1671                       # Number of loads squashed
system.cpu0.iew.lsq.thread.0.squashedStores         1054                       # Number of stores squashed
system.cpu0.iew.memOrderViolationEvents            44                       # Number of memory order violations
system.cpu0.iew.predictedNotTakenIncorrect          817                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.predictedTakenIncorrect           425                       # Number of branches that were predicted taken incorrectly
system.cpu0.int_regfile_reads                  812740                       # number of integer regfile reads
system.cpu0.int_regfile_writes                 365710                       # number of integer regfile writes
system.cpu0.ipc                              1.907830                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        1.907830                       # IPC: Total IPC of All Threads
system.cpu0.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntAlu         190821     41.95%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntMult             0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatAdd            0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatDiv            0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdAdd             0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdAlu             0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdCmp             0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdCvt             0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdMisc            0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdMult            0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdSqrt            0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     41.95% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::MemRead        175718     38.63%     80.59% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::MemWrite        88285     19.41%    100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::total          454824                       # Type of FU issued
system.cpu0.iq.ISSUE:fu_busy_cnt                  223                       # FU busy when requested
system.cpu0.iq.ISSUE:fu_busy_rate            0.000490                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntAlu               33     14.80%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntMult               0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntDiv                0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatAdd              0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatCmp              0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatCvt              0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatMult             0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatDiv              0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatSqrt             0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdAdd               0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdAddAcc            0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdAlu               0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdCmp               0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdCvt               0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdMisc              0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdMult              0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdShift             0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdSqrt              0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%     14.80% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::MemRead              81     36.32%     51.12% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::MemWrite            109     48.88%    100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:issued_per_cycle::samples       216775                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::mean     2.098139                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::stdev     1.056899                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::0        33322     15.37%     15.37% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::1         5647      2.61%     17.98% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::2        88171     40.67%     58.65% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::3        87126     40.19%     98.84% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::4         1486      0.69%     99.53% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::5          733      0.34%     99.87% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::6          191      0.09%     99.95% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::7           90      0.04%    100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::8            9      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::total       216775                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:rate                    1.936311                       # Inst issue rate
system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu0.iq.int_alu_accesses                455047                       # Number of integer alu accesses
system.cpu0.iq.int_inst_queue_reads           1126736                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_wakeup_accesses       453315                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.int_inst_queue_writes           465372                       # Number of integer instruction queue writes
system.cpu0.iq.iqInstsAdded                    456374                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqInstsIssued                   454824                       # Number of instructions issued
system.cpu0.iq.iqNonSpecInstsAdded                820                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqSquashedInstsExamined           8136                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedInstsIssued               90                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedNonSpecRemoved           261                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.iqSquashedOperandsExamined         6774                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.memDep0.conflictingLoads            86214                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores           86089                       # Number of conflicting stores.
system.cpu0.memDep0.insertedLoads              175971                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores              88710                       # Number of stores inserted to the mem dependence unit.
system.cpu0.misc_regfile_reads                 265353                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
system.cpu0.numCycles                          234892                       # number of cpu cycles simulated
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.rename.RENAME:BlockCycles            1209                       # Number of cycles rename is blocking
system.cpu0.rename.RENAME:CommittedMaps        361432                       # Number of HB maps that are committed
system.cpu0.rename.RENAME:IQFullEvents              6                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.RENAME:IdleCycles            20699                       # Number of cycles rename is idle
system.cpu0.rename.RENAME:LSQFullEvents           289                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RENAME:RenameLookups       1088795                       # Number of register rename lookups that rename has made
system.cpu0.rename.RENAME:RenamedInsts         545750                       # Number of instructions processed by rename
system.cpu0.rename.RENAME:RenamedOperands       371672                       # Number of destination operands rename has renamed
system.cpu0.rename.RENAME:RunCycles            180600                       # Number of cycles rename is running
system.cpu0.rename.RENAME:SquashCycles           2044                       # Number of cycles rename is squashing
system.cpu0.rename.RENAME:UnblockCycles           697                       # Number of cycles rename is unblocking
system.cpu0.rename.RENAME:UndoneMaps            10240                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.RENAME:int_rename_lookups      1088795                       # Number of integer rename lookups
system.cpu0.rename.RENAME:serializeStallCycles        11526                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RENAME:serializingInsts          803                       # count of serializing insts renamed
system.cpu0.rename.RENAME:skidInsts              4179                       # count of insts added to the skid buffer
system.cpu0.rename.RENAME:tempSerializingInsts          807                       # count of temporary serializing insts renamed
system.cpu0.rob.rob_reads                      757295                       # The number of ROB reads
system.cpu0.rob.rob_writes                    1089916                       # The number of ROB writes
system.cpu0.timesIdled                            338                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.workload.PROG:num_syscalls             89                       # Number of system calls
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.BTBHits                   53298                       # Number of BTB hits
system.cpu1.BPredUnit.BTBLookups                55521                       # Number of BTB lookups
system.cpu1.BPredUnit.RASInCorrect                  0                       # Number of incorrect RAS predictions.
system.cpu1.BPredUnit.condIncorrect              1087                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.condPredicted             55616                       # Number of conditional branches predicted
system.cpu1.BPredUnit.lookups                   55616                       # Number of BP lookups
system.cpu1.BPredUnit.usedRAS                       0                       # Number of times the RAS was used to get a target.
system.cpu1.commit.COM:branches                 52878                       # Number of branches committed
system.cpu1.commit.COM:bw_lim_events              488                       # number cycles where commit BW limit reached
system.cpu1.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
system.cpu1.commit.COM:committed_per_cycle::samples       188159                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::mean     1.583331                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::stdev     1.956493                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::0        78134     41.53%     41.53% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::1        53655     28.52%     70.04% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::2         7488      3.98%     74.02% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::3         7425      3.95%     77.97% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::4         2454      1.30%     79.27% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::5        37926     20.16%     99.43% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::6          461      0.25%     99.67% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::7          128      0.07%     99.74% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::8          488      0.26%    100.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::total       188159                       # Number of insts commited each cycle
system.cpu1.commit.COM:count                   297918                       # Number of instructions committed
system.cpu1.commit.COM:fp_insts                     0                       # Number of committed floating point instructions.
system.cpu1.commit.COM:function_calls               0                       # Number of function calls committed.
system.cpu1.commit.COM:int_insts               203433                       # Number of committed integer instructions.
system.cpu1.commit.COM:loads                    87419                       # Number of loads committed
system.cpu1.commit.COM:membars                   5903                       # Number of memory barriers committed
system.cpu1.commit.COM:refs                    128431                       # Number of memory references committed
system.cpu1.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
system.cpu1.commit.branchMispredicts             1087                       # The number of times a branch was mispredicted
system.cpu1.commit.commitCommittedInsts        297918                       # The number of committed instructions
system.cpu1.commit.commitNonSpecStalls           6615                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.commitSquashedInsts           8048                       # The number of squashed insts skipped by commit
system.cpu1.committedInsts                     248345                       # Number of Instructions Simulated
system.cpu1.committedInsts_total               248345                       # Number of Instructions Simulated
system.cpu1.cpi                              0.804816                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        0.804816                       # CPI: Total CPI of All Threads
system.cpu1.dcache.ReadReq_accesses             51009                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_avg_miss_latency 20896.247241                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13877.358491                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_hits                 50556                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_miss_latency       9466000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_rate         0.008881                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_misses                 453                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_mshr_hits              294                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_miss_latency      2206500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate     0.003117                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_misses            159                       # number of ReadReq MSHR misses
system.cpu1.dcache.SwapReq_accesses                66                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_avg_miss_latency 25933.962264                       # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 22933.962264                       # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_hits                    13                       # number of SwapReq hits
system.cpu1.dcache.SwapReq_miss_latency       1374500                       # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_rate         0.803030                       # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_misses                  53                       # number of SwapReq misses
system.cpu1.dcache.SwapReq_mshr_miss_latency      1215500                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_rate     0.803030                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_misses             53                       # number of SwapReq MSHR misses
system.cpu1.dcache.WriteReq_accesses            40946                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_avg_miss_latency 23975.806452                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15514.150943                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_hits                40822                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_miss_latency      2973000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_rate        0.003028                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_misses                124                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_mshr_hits              18                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_miss_latency      1644500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_rate     0.002589                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_misses           106                       # number of WriteReq MSHR misses
system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_refs               1612.206897                       # Average number of references to valid blocks.
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.demand_accesses              91955                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_avg_miss_latency 21558.058925                       # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency 14532.075472                       # average overall mshr miss latency
system.cpu1.dcache.demand_hits                  91378                       # number of demand (read+write) hits
system.cpu1.dcache.demand_miss_latency       12439000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_rate          0.006275                       # miss rate for demand accesses
system.cpu1.dcache.demand_misses                  577                       # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits               312                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency      3851000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate     0.002882                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_misses             265                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.occ_%::0                  0.048953                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_%::1                 -0.017597                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_blocks::0            25.063911                       # Average occupied blocks per context
system.cpu1.dcache.occ_blocks::1            -9.009839                       # Average occupied blocks per context
system.cpu1.dcache.overall_accesses             91955                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_avg_miss_latency 21558.058925                       # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency 14532.075472                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_hits                 91378                       # number of overall hits
system.cpu1.dcache.overall_miss_latency      12439000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_rate         0.006275                       # miss rate for overall accesses
system.cpu1.dcache.overall_misses                 577                       # number of overall misses
system.cpu1.dcache.overall_mshr_hits              312                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_miss_latency      3851000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate     0.002882                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_misses            265                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.replacements                     2                       # number of replacements
system.cpu1.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.dcache.tagsinuse                16.054072                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                   46754                       # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.writebacks                       1                       # number of writebacks
system.cpu1.decode.DECODE:BlockedCycles         20803                       # Number of cycles decode is blocked
system.cpu1.decode.DECODE:DecodedInsts         309923                       # Number of instructions handled by decode
system.cpu1.decode.DECODE:IdleCycles            54694                       # Number of cycles decode is idle
system.cpu1.decode.DECODE:RunCycles            107191                       # Number of cycles decode is running
system.cpu1.decode.DECODE:SquashCycles           1741                       # Number of cycles decode is squashing
system.cpu1.decode.DECODE:UnblockCycles          5470                       # Number of cycles decode is unblocking
system.cpu1.fetch.Branches                      55616                       # Number of branches that fetch encountered
system.cpu1.fetch.CacheLines                    20621                       # Number of cache lines fetched
system.cpu1.fetch.Cycles                       113033                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.IcacheSquashes                  217                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.Insts                        311054                       # Number of instructions fetch has processed
system.cpu1.fetch.MiscStallCycles                  22                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.SquashCycles                   1161                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.branchRate                 0.278258                       # Number of branch fetches per cycle
system.cpu1.fetch.icacheStallCycles             20621                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.predictedBranches             53298                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.rate                       1.556266                       # Number of inst fetches per cycle
system.cpu1.fetch.rateDist::samples            196498                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.582988                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.040174                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                   83465     42.48%     42.48% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                   58273     29.66%     72.13% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                    7057      3.59%     75.72% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                    2697      1.37%     77.10% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                    1913      0.97%     78.07% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   38892     19.79%     97.86% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                    2445      1.24%     99.11% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                     254      0.13%     99.24% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                    1502      0.76%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total              196498                       # Number of instructions fetched each cycle (Total)
system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu1.icache.ReadReq_accesses             20621                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_avg_miss_latency 15456.066946                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12612.500000                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_hits                 20143                       # number of ReadReq hits
system.cpu1.icache.ReadReq_miss_latency       7388000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_rate         0.023180                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_misses                 478                       # number of ReadReq misses
system.cpu1.icache.ReadReq_mshr_hits               38                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_miss_latency      5549500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate     0.021337                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_misses            440                       # number of ReadReq MSHR misses
system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.icache.avg_refs                 45.779545                       # Average number of references to valid blocks.
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.demand_accesses              20621                       # number of demand (read+write) accesses
system.cpu1.icache.demand_avg_miss_latency 15456.066946                       # average overall miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency 12612.500000                       # average overall mshr miss latency
system.cpu1.icache.demand_hits                  20143                       # number of demand (read+write) hits
system.cpu1.icache.demand_miss_latency        7388000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_rate          0.023180                       # miss rate for demand accesses
system.cpu1.icache.demand_misses                  478                       # number of demand (read+write) misses
system.cpu1.icache.demand_mshr_hits                38                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_miss_latency      5549500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_rate     0.021337                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_misses             440                       # number of demand (read+write) MSHR misses
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.occ_%::0                  0.172715                       # Average percentage of cache occupancy
system.cpu1.icache.occ_blocks::0            88.430285                       # Average occupied blocks per context
system.cpu1.icache.overall_accesses             20621                       # number of overall (read+write) accesses
system.cpu1.icache.overall_avg_miss_latency 15456.066946                       # average overall miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency 12612.500000                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_hits                 20143                       # number of overall hits
system.cpu1.icache.overall_miss_latency       7388000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_rate         0.023180                       # miss rate for overall accesses
system.cpu1.icache.overall_misses                 478                       # number of overall misses
system.cpu1.icache.overall_mshr_hits               38                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_miss_latency      5549500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_rate     0.021337                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_misses            440                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.icache.replacements                   328                       # number of replacements
system.cpu1.icache.sampled_refs                   440                       # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.icache.tagsinuse                88.430285                       # Cycle average of tags in use
system.cpu1.icache.total_refs                   20143                       # Total number of references to valid blocks.
system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks                       0                       # number of writebacks
system.cpu1.idleCycles                           3374                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.iew.EXEC:branches                   53426                       # Number of branches executed
system.cpu1.iew.EXEC:nop                        44397                       # number of nop insts executed
system.cpu1.iew.EXEC:rate                    1.290846                       # Inst execution rate
system.cpu1.iew.EXEC:refs                      129529                       # number of memory reference insts executed
system.cpu1.iew.EXEC:stores                     41363                       # Number of stores executed
system.cpu1.iew.EXEC:swp                            0                       # number of swp insts executed
system.cpu1.iew.WB:consumers                   149591                       # num instructions consuming a value
system.cpu1.iew.WB:count                       257643                       # cumulative count of insts written-back
system.cpu1.iew.WB:fanout                    0.975567                       # average fanout of values written-back
system.cpu1.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.iew.WB:producers                   145936                       # num instructions producing a value
system.cpu1.iew.WB:rate                      1.289040                       # insts written-back per cycle
system.cpu1.iew.WB:sent                        257774                       # cumulative count of insts sent to commit
system.cpu1.iew.branchMispredicts                1186                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewBlockCycles                   1504                       # Number of cycles IEW is blocking
system.cpu1.iew.iewDispLoadInsts                88859                       # Number of dispatched load instructions
system.cpu1.iew.iewDispNonSpecInsts               932                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewDispSquashedInsts              535                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispStoreInsts               41782                       # Number of dispatched store instructions
system.cpu1.iew.iewDispatchedInsts             305999                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewExecLoadInsts                88166                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts              964                       # Number of squashed instructions skipped in execute
system.cpu1.iew.iewExecutedInsts               258004                       # Number of executed instructions
system.cpu1.iew.iewIQFullEvents                    47                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.iewSquashCycles                  1741                       # Number of cycles IEW is squashing
system.cpu1.iew.iewUnblockCycles                   54                       # Number of cycles IEW is unblocking
system.cpu1.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread.0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.lsq.thread.0.forwLoads          37142                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread.0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread.0.memOrderViolation           29                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread.0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread.0.squashedLoads         1440                       # Number of loads squashed
system.cpu1.iew.lsq.thread.0.squashedStores          770                       # Number of stores squashed
system.cpu1.iew.memOrderViolationEvents            29                       # Number of memory order violations
system.cpu1.iew.predictedNotTakenIncorrect          196                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.predictedTakenIncorrect           990                       # Number of branches that were predicted taken incorrectly
system.cpu1.int_regfile_reads                  446126                       # number of integer regfile reads
system.cpu1.int_regfile_writes                 206677                       # number of integer regfile writes
system.cpu1.ipc                              1.242520                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        1.242520                       # IPC: Total IPC of All Threads
system.cpu1.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntAlu         123325     47.62%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntMult             0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatAdd            0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatDiv            0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdAdd             0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdAlu             0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdCmp             0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdCvt             0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdMisc            0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdMult            0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt            0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::MemRead         94249     36.39%     84.02% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::MemWrite        41394     15.98%    100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::total          258968                       # Type of FU issued
system.cpu1.iq.ISSUE:fu_busy_cnt                  195                       # FU busy when requested
system.cpu1.iq.ISSUE:fu_busy_rate            0.000753                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntAlu               11      5.64%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntMult               0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntDiv                0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatAdd              0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatCmp              0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatCvt              0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatMult             0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatDiv              0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatSqrt             0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdAdd               0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdAddAcc            0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdAlu               0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdCmp               0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdCvt               0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdMisc              0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdMult              0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdShift             0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdSqrt              0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      5.64% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::MemRead              53     27.18%     32.82% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::MemWrite            131     67.18%    100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:issued_per_cycle::samples       196498                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::mean     1.317917                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::stdev     1.287238                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::0        79641     40.53%     40.53% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::1        27330     13.91%     54.44% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::2        43586     22.18%     76.62% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::3        41460     21.10%     97.72% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::4         2668      1.36%     99.08% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::5         1566      0.80%     99.87% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::6          155      0.08%     99.95% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::7           82      0.04%     99.99% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::8           10      0.01%    100.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::total       196498                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:rate                    1.295669                       # Inst issue rate
system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu1.iq.int_alu_accesses                259163                       # Number of integer alu accesses
system.cpu1.iq.int_inst_queue_reads            714631                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_wakeup_accesses       257643                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.int_inst_queue_writes           268053                       # Number of integer instruction queue writes
system.cpu1.iq.iqInstsAdded                    254426                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqInstsIssued                   258968                       # Number of instructions issued
system.cpu1.iq.iqNonSpecInstsAdded               7176                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqSquashedInstsExamined           6422                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedInstsIssued                2                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedNonSpecRemoved           561                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.iqSquashedOperandsExamined         5912                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.memDep0.conflictingLoads            43433                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores           37289                       # Number of conflicting stores.
system.cpu1.memDep0.insertedLoads               88859                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores              41782                       # Number of stores inserted to the mem dependence unit.
system.cpu1.misc_regfile_reads                 131065                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                   646                       # number of misc regfile writes
system.cpu1.numCycles                          199872                       # number of cpu cycles simulated
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.rename.RENAME:BlockCycles            7004                       # Number of cycles rename is blocking
system.cpu1.rename.RENAME:CommittedMaps        204047                       # Number of HB maps that are committed
system.cpu1.rename.RENAME:IQFullEvents             57                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.RENAME:IdleCycles            55307                       # Number of cycles rename is idle
system.cpu1.rename.RENAME:LSQFullEvents            48                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RENAME:RenameLookups        588542                       # Number of register rename lookups that rename has made
system.cpu1.rename.RENAME:RenamedInsts         308173                       # Number of instructions processed by rename
system.cpu1.rename.RENAME:RenamedOperands       212215                       # Number of destination operands rename has renamed
system.cpu1.rename.RENAME:RunCycles            112201                       # Number of cycles rename is running
system.cpu1.rename.RENAME:SquashCycles           1741                       # Number of cycles rename is squashing
system.cpu1.rename.RENAME:UnblockCycles           589                       # Number of cycles rename is unblocking
system.cpu1.rename.RENAME:UndoneMaps             8168                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.RENAME:int_rename_lookups       588542                       # Number of integer rename lookups
system.cpu1.rename.RENAME:serializeStallCycles        13057                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RENAME:serializingInsts          954                       # count of serializing insts renamed
system.cpu1.rename.RENAME:skidInsts              2780                       # count of insts added to the skid buffer
system.cpu1.rename.RENAME:tempSerializingInsts         1009                       # count of temporary serializing insts renamed
system.cpu1.rob.rob_reads                      493050                       # The number of ROB reads
system.cpu1.rob.rob_writes                     613675                       # The number of ROB writes
system.cpu1.timesIdled                            291                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.BPredUnit.BTBHits                   55906                       # Number of BTB hits
system.cpu2.BPredUnit.BTBLookups                58100                       # Number of BTB lookups
system.cpu2.BPredUnit.RASInCorrect                  0                       # Number of incorrect RAS predictions.
system.cpu2.BPredUnit.condIncorrect              1096                       # Number of conditional branches incorrect
system.cpu2.BPredUnit.condPredicted             58228                       # Number of conditional branches predicted
system.cpu2.BPredUnit.lookups                   58228                       # Number of BP lookups
system.cpu2.BPredUnit.usedRAS                       0                       # Number of times the RAS was used to get a target.
system.cpu2.commit.COM:branches                 55433                       # Number of branches committed
system.cpu2.commit.COM:bw_lim_events              499                       # number cycles where commit BW limit reached
system.cpu2.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
system.cpu2.commit.COM:committed_per_cycle::samples       185729                       # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::mean     1.698900                       # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::stdev     1.997080                       # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::0        70586     38.00%     38.00% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::1        56238     30.28%     68.28% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::2         7477      4.03%     72.31% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::3         6262      3.37%     75.68% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::4         2451      1.32%     77.00% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::5        41665     22.43%     99.43% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::6          421      0.23%     99.66% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::7          130      0.07%     99.73% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::8          499      0.27%    100.00% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::total       185729                       # Number of insts commited each cycle
system.cpu2.commit.COM:count                   315535                       # Number of instructions committed
system.cpu2.commit.COM:fp_insts                     0                       # Number of committed floating point instructions.
system.cpu2.commit.COM:function_calls               0                       # Number of function calls committed.
system.cpu2.commit.COM:int_insts               215944                       # Number of committed integer instructions.
system.cpu2.commit.COM:loads                    93671                       # Number of loads committed
system.cpu2.commit.COM:membars                   4747                       # Number of memory barriers committed
system.cpu2.commit.COM:refs                    138392                       # Number of memory references committed
system.cpu2.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
system.cpu2.commit.branchMispredicts             1096                       # The number of times a branch was mispredicted
system.cpu2.commit.commitCommittedInsts        315535                       # The number of committed instructions
system.cpu2.commit.commitNonSpecStalls           5463                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.commitSquashedInsts           8360                       # The number of squashed insts skipped by commit
system.cpu2.committedInsts                     264567                       # Number of Instructions Simulated
system.cpu2.committedInsts_total               264567                       # Number of Instructions Simulated
system.cpu2.cpi                              0.754365                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        0.754365                       # CPI: Total CPI of All Threads
system.cpu2.dcache.ReadReq_accesses             53583                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_avg_miss_latency 22410.944206                       # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 15243.827160                       # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_hits                 53117                       # number of ReadReq hits
system.cpu2.dcache.ReadReq_miss_latency      10443500                       # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_rate         0.008697                       # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_misses                 466                       # number of ReadReq misses
system.cpu2.dcache.ReadReq_mshr_hits              304                       # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_miss_latency      2469500                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate     0.003023                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_misses            162                       # number of ReadReq MSHR misses
system.cpu2.dcache.SwapReq_accesses                70                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_avg_miss_latency 24534.482759                       # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 21534.482759                       # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_hits                    12                       # number of SwapReq hits
system.cpu2.dcache.SwapReq_miss_latency       1423000                       # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_rate         0.828571                       # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_misses                  58                       # number of SwapReq misses
system.cpu2.dcache.SwapReq_mshr_miss_latency      1249000                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_rate     0.828571                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_misses             58                       # number of SwapReq MSHR misses
system.cpu2.dcache.WriteReq_accesses            44651                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_avg_miss_latency 23987.804878                       # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 15485.714286                       # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_hits                44528                       # number of WriteReq hits
system.cpu2.dcache.WriteReq_miss_latency      2950500                       # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_rate        0.002755                       # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_misses                123                       # number of WriteReq misses
system.cpu2.dcache.WriteReq_mshr_hits              18                       # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_miss_latency      1626000                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_rate     0.002352                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_misses           105                       # number of WriteReq MSHR misses
system.cpu2.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_refs               1682.766667                       # Average number of references to valid blocks.
system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu2.dcache.demand_accesses              98234                       # number of demand (read+write) accesses
system.cpu2.dcache.demand_avg_miss_latency 22740.237691                       # average overall miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency 15338.951311                       # average overall mshr miss latency
system.cpu2.dcache.demand_hits                  97645                       # number of demand (read+write) hits
system.cpu2.dcache.demand_miss_latency       13394000                       # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_rate          0.005996                       # miss rate for demand accesses
system.cpu2.dcache.demand_misses                  589                       # number of demand (read+write) misses
system.cpu2.dcache.demand_mshr_hits               322                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_miss_latency      4095500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_rate     0.002718                       # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_misses             267                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu2.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.dcache.occ_%::0                  0.052897                       # Average percentage of cache occupancy
system.cpu2.dcache.occ_%::1                 -0.018338                       # Average percentage of cache occupancy
system.cpu2.dcache.occ_blocks::0            27.083354                       # Average occupied blocks per context
system.cpu2.dcache.occ_blocks::1            -9.389236                       # Average occupied blocks per context
system.cpu2.dcache.overall_accesses             98234                       # number of overall (read+write) accesses
system.cpu2.dcache.overall_avg_miss_latency 22740.237691                       # average overall miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency 15338.951311                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu2.dcache.overall_hits                 97645                       # number of overall hits
system.cpu2.dcache.overall_miss_latency      13394000                       # number of overall miss cycles
system.cpu2.dcache.overall_miss_rate         0.005996                       # miss rate for overall accesses
system.cpu2.dcache.overall_misses                 589                       # number of overall misses
system.cpu2.dcache.overall_mshr_hits              322                       # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_miss_latency      4095500                       # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_rate     0.002718                       # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_misses            267                       # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu2.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu2.dcache.replacements                     2                       # number of replacements
system.cpu2.dcache.sampled_refs                    30                       # Sample count of references to valid blocks.
system.cpu2.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu2.dcache.tagsinuse                17.694118                       # Cycle average of tags in use
system.cpu2.dcache.total_refs                   50483                       # Total number of references to valid blocks.
system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.dcache.writebacks                       1                       # number of writebacks
system.cpu2.decode.DECODE:BlockedCycles         20050                       # Number of cycles decode is blocked
system.cpu2.decode.DECODE:DecodedInsts         327820                       # Number of instructions handled by decode
system.cpu2.decode.DECODE:IdleCycles            49005                       # Number of cycles decode is idle
system.cpu2.decode.DECODE:RunCycles            112255                       # Number of cycles decode is running
system.cpu2.decode.DECODE:SquashCycles           1781                       # Number of cycles decode is squashing
system.cpu2.decode.DECODE:UnblockCycles          4418                       # Number of cycles decode is unblocking
system.cpu2.fetch.Branches                      58228                       # Number of branches that fetch encountered
system.cpu2.fetch.CacheLines                    18194                       # Number of cache lines fetched
system.cpu2.fetch.Cycles                       117037                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.IcacheSquashes                  225                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.Insts                        328955                       # Number of instructions fetch has processed
system.cpu2.fetch.MiscStallCycles                  30                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.SquashCycles                   1170                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.branchRate                 0.291753                       # Number of branch fetches per cycle
system.cpu2.fetch.icacheStallCycles             18194                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.predictedBranches             55906                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.rate                       1.648236                       # Number of inst fetches per cycle
system.cpu2.fetch.rateDist::samples            194114                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.694649                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.084542                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                   77077     39.71%     39.71% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                   59674     30.74%     70.45% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                    5837      3.01%     73.46% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                    2794      1.44%     74.90% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                    1893      0.98%     75.87% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                   42627     21.96%     97.83% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                    2458      1.27%     99.10% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                     262      0.13%     99.23% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                    1492      0.77%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total              194114                       # Number of instructions fetched each cycle (Total)
system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu2.icache.ReadReq_accesses             18194                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_avg_miss_latency 21635.330579                       # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18220.454545                       # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_hits                 17710                       # number of ReadReq hits
system.cpu2.icache.ReadReq_miss_latency      10471500                       # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_rate         0.026602                       # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_misses                 484                       # number of ReadReq misses
system.cpu2.icache.ReadReq_mshr_hits               44                       # number of ReadReq MSHR hits
system.cpu2.icache.ReadReq_mshr_miss_latency      8017000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate     0.024184                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_misses            440                       # number of ReadReq MSHR misses
system.cpu2.icache.avg_blocked_cycles::no_mshrs        18250                       # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu2.icache.avg_refs                 40.250000                       # Average number of references to valid blocks.
system.cpu2.icache.blocked::no_mshrs                2                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_mshrs        36500                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
system.cpu2.icache.demand_accesses              18194                       # number of demand (read+write) accesses
system.cpu2.icache.demand_avg_miss_latency 21635.330579                       # average overall miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency 18220.454545                       # average overall mshr miss latency
system.cpu2.icache.demand_hits                  17710                       # number of demand (read+write) hits
system.cpu2.icache.demand_miss_latency       10471500                       # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_rate          0.026602                       # miss rate for demand accesses
system.cpu2.icache.demand_misses                  484                       # number of demand (read+write) misses
system.cpu2.icache.demand_mshr_hits                44                       # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_miss_latency      8017000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_rate     0.024184                       # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_misses             440                       # number of demand (read+write) MSHR misses
system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
system.cpu2.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.icache.occ_%::0                  0.176645                       # Average percentage of cache occupancy
system.cpu2.icache.occ_blocks::0            90.442244                       # Average occupied blocks per context
system.cpu2.icache.overall_accesses             18194                       # number of overall (read+write) accesses
system.cpu2.icache.overall_avg_miss_latency 21635.330579                       # average overall miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency 18220.454545                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu2.icache.overall_hits                 17710                       # number of overall hits
system.cpu2.icache.overall_miss_latency      10471500                       # number of overall miss cycles
system.cpu2.icache.overall_miss_rate         0.026602                       # miss rate for overall accesses
system.cpu2.icache.overall_misses                 484                       # number of overall misses
system.cpu2.icache.overall_mshr_hits               44                       # number of overall MSHR hits
system.cpu2.icache.overall_mshr_miss_latency      8017000                       # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_rate     0.024184                       # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_misses            440                       # number of overall MSHR misses
system.cpu2.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu2.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu2.icache.replacements                   330                       # number of replacements
system.cpu2.icache.sampled_refs                   440                       # Sample count of references to valid blocks.
system.cpu2.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu2.icache.tagsinuse                90.442244                       # Cycle average of tags in use
system.cpu2.icache.total_refs                   17710                       # Total number of references to valid blocks.
system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.icache.writebacks                       0                       # number of writebacks
system.cpu2.idleCycles                           5466                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.iew.EXEC:branches                   55984                       # Number of branches executed
system.cpu2.iew.EXEC:nop                        47025                       # number of nop insts executed
system.cpu2.iew.EXEC:rate                    1.368298                       # Inst execution rate
system.cpu2.iew.EXEC:refs                      139522                       # number of memory reference insts executed
system.cpu2.iew.EXEC:stores                     45069                       # Number of stores executed
system.cpu2.iew.EXEC:swp                            0                       # number of swp insts executed
system.cpu2.iew.WB:consumers                   159565                       # num instructions consuming a value
system.cpu2.iew.WB:count                       272710                       # cumulative count of insts written-back
system.cpu2.iew.WB:fanout                    0.977063                       # average fanout of values written-back
system.cpu2.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.iew.WB:producers                   155905                       # num instructions producing a value
system.cpu2.iew.WB:rate                      1.366419                       # insts written-back per cycle
system.cpu2.iew.WB:sent                        272842                       # cumulative count of insts sent to commit
system.cpu2.iew.branchMispredicts                1198                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewBlockCycles                   1731                       # Number of cycles IEW is blocking
system.cpu2.iew.iewDispLoadInsts                95225                       # Number of dispatched load instructions
system.cpu2.iew.iewDispNonSpecInsts               927                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewDispSquashedInsts              555                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispStoreInsts               45493                       # Number of dispatched store instructions
system.cpu2.iew.iewDispatchedInsts             323925                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewExecLoadInsts                94453                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts              959                       # Number of squashed instructions skipped in execute
system.cpu2.iew.iewExecutedInsts               273085                       # Number of executed instructions
system.cpu2.iew.iewIQFullEvents                    57                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.iewSquashCycles                  1781                       # Number of cycles IEW is squashing
system.cpu2.iew.iewUnblockCycles                   67                       # Number of cycles IEW is unblocking
system.cpu2.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread.0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.lsq.thread.0.forwLoads          40852                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread.0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread.0.memOrderViolation           29                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread.0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread.0.squashedLoads         1554                       # Number of loads squashed
system.cpu2.iew.lsq.thread.0.squashedStores          772                       # Number of stores squashed
system.cpu2.iew.memOrderViolationEvents            29                       # Number of memory order violations
system.cpu2.iew.predictedNotTakenIncorrect          202                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.predictedTakenIncorrect           996                       # Number of branches that were predicted taken incorrectly
system.cpu2.int_regfile_reads                  476036                       # number of integer regfile reads
system.cpu2.int_regfile_writes                 220349                       # number of integer regfile writes
system.cpu2.ipc                              1.325619                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        1.325619                       # IPC: Total IPC of All Threads
system.cpu2.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::IntAlu         129561     47.28%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::IntMult             0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatAdd            0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatDiv            0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdAdd             0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdAlu             0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdCmp             0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdCvt             0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdMisc            0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdMult            0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdSqrt            0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     47.28% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::MemRead         99383     36.27%     83.54% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::MemWrite        45100     16.46%    100.00% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::total          274044                       # Type of FU issued
system.cpu2.iq.ISSUE:fu_busy_cnt                  205                       # FU busy when requested
system.cpu2.iq.ISSUE:fu_busy_rate            0.000748                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::IntAlu               12      5.85%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::IntMult               0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::IntDiv                0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatAdd              0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatCmp              0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatCvt              0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatMult             0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatDiv              0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatSqrt             0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdAdd               0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdAddAcc            0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdAlu               0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdCmp               0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdCvt               0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdMisc              0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdMult              0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdShift             0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdSqrt              0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      5.85% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::MemRead              62     30.24%     36.10% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::MemWrite            131     63.90%    100.00% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.ISSUE:issued_per_cycle::samples       194114                       # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::mean     1.411768                       # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::stdev     1.293131                       # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::0        73286     37.75%     37.75% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::1        23867     12.30%     50.05% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::2        47309     24.37%     74.42% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::3        45216     23.29%     97.71% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::4         2634      1.36%     99.07% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::5         1540      0.79%     99.87% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::6          168      0.09%     99.95% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::7           85      0.04%    100.00% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::8            9      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::total       194114                       # Number of insts issued each cycle
system.cpu2.iq.ISSUE:rate                    1.373104                       # Inst issue rate
system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu2.iq.int_alu_accesses                274249                       # Number of integer alu accesses
system.cpu2.iq.int_inst_queue_reads            742408                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_wakeup_accesses       272710                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.int_inst_queue_writes           283590                       # Number of integer instruction queue writes
system.cpu2.iq.iqInstsAdded                    270836                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqInstsIssued                   274044                       # Number of instructions issued
system.cpu2.iq.iqNonSpecInstsAdded               6064                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqSquashedInstsExamined           6661                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedInstsIssued                1                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedNonSpecRemoved           601                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.iqSquashedOperandsExamined         6335                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.memDep0.conflictingLoads            46039                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores           41011                       # Number of conflicting stores.
system.cpu2.memDep0.insertedLoads               95225                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores              45493                       # Number of stores inserted to the mem dependence unit.
system.cpu2.misc_regfile_reads                 141060                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                   646                       # number of misc regfile writes
system.cpu2.numCycles                          199580                       # number of cpu cycles simulated
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.rename.RENAME:BlockCycles            6241                       # Number of cycles rename is blocking
system.cpu2.rename.RENAME:CommittedMaps        217715                       # Number of HB maps that are committed
system.cpu2.rename.RENAME:IQFullEvents             58                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.RENAME:IdleCycles            49628                       # Number of cycles rename is idle
system.cpu2.rename.RENAME:LSQFullEvents            58                       # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RENAME:RenameLookups        628783                       # Number of register rename lookups that rename has made
system.cpu2.rename.RENAME:RenamedInsts         326092                       # Number of instructions processed by rename
system.cpu2.rename.RENAME:RenamedOperands       225995                       # Number of destination operands rename has renamed
system.cpu2.rename.RENAME:RunCycles            116192                       # Number of cycles rename is running
system.cpu2.rename.RENAME:SquashCycles           1781                       # Number of cycles rename is squashing
system.cpu2.rename.RENAME:UnblockCycles           614                       # Number of cycles rename is unblocking
system.cpu2.rename.RENAME:UndoneMaps             8280                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.RENAME:int_rename_lookups       628783                       # Number of integer rename lookups
system.cpu2.rename.RENAME:serializeStallCycles        13053                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RENAME:serializingInsts          948                       # count of serializing insts renamed
system.cpu2.rename.RENAME:skidInsts              2856                       # count of insts added to the skid buffer
system.cpu2.rename.RENAME:tempSerializingInsts         1003                       # count of temporary serializing insts renamed
system.cpu2.rob.rob_reads                      508538                       # The number of ROB reads
system.cpu2.rob.rob_writes                     649574                       # The number of ROB writes
system.cpu2.timesIdled                            302                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.BPredUnit.BTBHits                   43772                       # Number of BTB hits
system.cpu3.BPredUnit.BTBLookups                45981                       # Number of BTB lookups
system.cpu3.BPredUnit.RASInCorrect                  0                       # Number of incorrect RAS predictions.
system.cpu3.BPredUnit.condIncorrect              1096                       # Number of conditional branches incorrect
system.cpu3.BPredUnit.condPredicted             46026                       # Number of conditional branches predicted
system.cpu3.BPredUnit.lookups                   46026                       # Number of BP lookups
system.cpu3.BPredUnit.usedRAS                       0                       # Number of times the RAS was used to get a target.
system.cpu3.commit.COM:branches                 43201                       # Number of branches committed
system.cpu3.commit.COM:bw_lim_events              486                       # number cycles where commit BW limit reached
system.cpu3.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
system.cpu3.commit.COM:committed_per_cycle::samples       187492                       # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::mean     1.251248                       # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::stdev     1.795283                       # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::0        96787     51.62%     51.62% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::1        44013     23.47%     75.10% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::2         7489      3.99%     79.09% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::3        10030      5.35%     84.44% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::4         2457      1.31%     85.75% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::5        25706     13.71%     99.46% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::6          396      0.21%     99.67% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::7          128      0.07%     99.74% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::8          486      0.26%    100.00% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::total       187492                       # Number of insts commited each cycle
system.cpu3.commit.COM:count                   234599                       # Number of instructions committed
system.cpu3.commit.COM:fp_insts                     0                       # Number of committed floating point instructions.
system.cpu3.commit.COM:function_calls               0                       # Number of function calls committed.
system.cpu3.commit.COM:int_insts               159474                       # Number of committed integer instructions.
system.cpu3.commit.COM:loads                    65432                       # Number of loads committed
system.cpu3.commit.COM:membars                   8520                       # Number of memory barriers committed
system.cpu3.commit.COM:refs                     94154                       # Number of memory references committed
system.cpu3.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
system.cpu3.commit.branchMispredicts             1096                       # The number of times a branch was mispredicted
system.cpu3.commit.commitCommittedInsts        234599                       # The number of committed instructions
system.cpu3.commit.commitNonSpecStalls           9238                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.commitSquashedInsts           8312                       # The number of squashed insts skipped by commit
system.cpu3.committedInsts                     192092                       # Number of Instructions Simulated
system.cpu3.committedInsts_total               192092                       # Number of Instructions Simulated
system.cpu3.cpi                              1.037576                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        1.037576                       # CPI: Total CPI of All Threads
system.cpu3.dcache.ReadReq_accesses             41296                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_avg_miss_latency 22460.431655                       # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 14148.484848                       # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_hits                 40879                       # number of ReadReq hits
system.cpu3.dcache.ReadReq_miss_latency       9366000                       # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_rate         0.010098                       # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_misses                 417                       # number of ReadReq misses
system.cpu3.dcache.ReadReq_mshr_hits              252                       # number of ReadReq MSHR hits
system.cpu3.dcache.ReadReq_mshr_miss_latency      2334500                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate     0.003996                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_misses            165                       # number of ReadReq MSHR misses
system.cpu3.dcache.SwapReq_accesses                72                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_avg_miss_latency 26552.631579                       # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 23552.631579                       # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_hits                    15                       # number of SwapReq hits
system.cpu3.dcache.SwapReq_miss_latency       1513500                       # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_rate         0.791667                       # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_misses                  57                       # number of SwapReq misses
system.cpu3.dcache.SwapReq_mshr_miss_latency      1342500                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_rate     0.791667                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_misses             57                       # number of SwapReq MSHR misses
system.cpu3.dcache.WriteReq_accesses            28650                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_avg_miss_latency 23359.504132                       # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 15274.509804                       # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_hits                28529                       # number of WriteReq hits
system.cpu3.dcache.WriteReq_miss_latency      2826500                       # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_rate        0.004223                       # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_misses                121                       # number of WriteReq misses
system.cpu3.dcache.WriteReq_mshr_hits              19                       # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_miss_latency      1558000                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_rate     0.003560                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_misses           102                       # number of WriteReq MSHR misses
system.cpu3.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_refs               1150.100000                       # Average number of references to valid blocks.
system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu3.dcache.demand_accesses              69946                       # number of demand (read+write) accesses
system.cpu3.dcache.demand_avg_miss_latency 22662.639405                       # average overall miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency 14578.651685                       # average overall mshr miss latency
system.cpu3.dcache.demand_hits                  69408                       # number of demand (read+write) hits
system.cpu3.dcache.demand_miss_latency       12192500                       # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_rate          0.007692                       # miss rate for demand accesses
system.cpu3.dcache.demand_misses                  538                       # number of demand (read+write) misses
system.cpu3.dcache.demand_mshr_hits               271                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_miss_latency      3892500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_rate     0.003817                       # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_misses             267                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu3.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.dcache.occ_%::0                  0.047232                       # Average percentage of cache occupancy
system.cpu3.dcache.occ_%::1                 -0.016274                       # Average percentage of cache occupancy
system.cpu3.dcache.occ_blocks::0            24.182757                       # Average occupied blocks per context
system.cpu3.dcache.occ_blocks::1            -8.332061                       # Average occupied blocks per context
system.cpu3.dcache.overall_accesses             69946                       # number of overall (read+write) accesses
system.cpu3.dcache.overall_avg_miss_latency 22662.639405                       # average overall miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency 14578.651685                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu3.dcache.overall_hits                 69408                       # number of overall hits
system.cpu3.dcache.overall_miss_latency      12192500                       # number of overall miss cycles
system.cpu3.dcache.overall_miss_rate         0.007692                       # miss rate for overall accesses
system.cpu3.dcache.overall_misses                 538                       # number of overall misses
system.cpu3.dcache.overall_mshr_hits              271                       # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_miss_latency      3892500                       # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_rate     0.003817                       # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_misses            267                       # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu3.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu3.dcache.replacements                     2                       # number of replacements
system.cpu3.dcache.sampled_refs                    30                       # Sample count of references to valid blocks.
system.cpu3.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu3.dcache.tagsinuse                15.850697                       # Cycle average of tags in use
system.cpu3.dcache.total_refs                   34503                       # Total number of references to valid blocks.
system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.dcache.writebacks                       1                       # number of writebacks
system.cpu3.decode.DECODE:BlockedCycles         23404                       # Number of cycles decode is blocked
system.cpu3.decode.DECODE:DecodedInsts         246917                       # Number of instructions handled by decode
system.cpu3.decode.DECODE:IdleCycles            67894                       # Number of cycles decode is idle
system.cpu3.decode.DECODE:RunCycles             88329                       # Number of cycles decode is running
system.cpu3.decode.DECODE:SquashCycles           1781                       # Number of cycles decode is squashing
system.cpu3.decode.DECODE:UnblockCycles          7864                       # Number of cycles decode is unblocking
system.cpu3.fetch.Branches                      46026                       # Number of branches that fetch encountered
system.cpu3.fetch.CacheLines                    26017                       # Number of cache lines fetched
system.cpu3.fetch.Cycles                        96566                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.IcacheSquashes                  224                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.Insts                        248038                       # Number of instructions fetch has processed
system.cpu3.fetch.MiscStallCycles                  24                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.SquashCycles                   1170                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.branchRate                 0.230927                       # Number of branch fetches per cycle
system.cpu3.fetch.icacheStallCycles             26017                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.predictedBranches             43772                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.rate                       1.244483                       # Number of inst fetches per cycle
system.cpu3.fetch.rateDist::samples            195889                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.266217                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            1.878921                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0                   99323     50.70%     50.70% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                   51378     26.23%     76.93% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                    9749      4.98%     81.91% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                    2746      1.40%     83.31% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                    1924      0.98%     84.29% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                   26575     13.57%     97.86% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                    2472      1.26%     99.12% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                     255      0.13%     99.25% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                    1467      0.75%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total              195889                       # Number of instructions fetched each cycle (Total)
system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu3.icache.ReadReq_accesses             26017                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_avg_miss_latency 14208.939709                       # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11549.661400                       # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_hits                 25536                       # number of ReadReq hits
system.cpu3.icache.ReadReq_miss_latency       6834500                       # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_rate         0.018488                       # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_misses                 481                       # number of ReadReq misses
system.cpu3.icache.ReadReq_mshr_hits               38                       # number of ReadReq MSHR hits
system.cpu3.icache.ReadReq_mshr_miss_latency      5116500                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate     0.017027                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_misses            443                       # number of ReadReq MSHR misses
system.cpu3.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu3.icache.avg_refs                 57.643341                       # Average number of references to valid blocks.
system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
system.cpu3.icache.demand_accesses              26017                       # number of demand (read+write) accesses
system.cpu3.icache.demand_avg_miss_latency 14208.939709                       # average overall miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency 11549.661400                       # average overall mshr miss latency
system.cpu3.icache.demand_hits                  25536                       # number of demand (read+write) hits
system.cpu3.icache.demand_miss_latency        6834500                       # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_rate          0.018488                       # miss rate for demand accesses
system.cpu3.icache.demand_misses                  481                       # number of demand (read+write) misses
system.cpu3.icache.demand_mshr_hits                38                       # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_miss_latency      5116500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_rate     0.017027                       # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_misses             443                       # number of demand (read+write) MSHR misses
system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
system.cpu3.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.icache.occ_%::0                  0.166919                       # Average percentage of cache occupancy
system.cpu3.icache.occ_blocks::0            85.462768                       # Average occupied blocks per context
system.cpu3.icache.overall_accesses             26017                       # number of overall (read+write) accesses
system.cpu3.icache.overall_avg_miss_latency 14208.939709                       # average overall miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency 11549.661400                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu3.icache.overall_hits                 25536                       # number of overall hits
system.cpu3.icache.overall_miss_latency       6834500                       # number of overall miss cycles
system.cpu3.icache.overall_miss_rate         0.018488                       # miss rate for overall accesses
system.cpu3.icache.overall_misses                 481                       # number of overall misses
system.cpu3.icache.overall_mshr_hits               38                       # number of overall MSHR hits
system.cpu3.icache.overall_mshr_miss_latency      5116500                       # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_rate     0.017027                       # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_misses            443                       # number of overall MSHR misses
system.cpu3.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu3.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu3.icache.replacements                   331                       # number of replacements
system.cpu3.icache.sampled_refs                   443                       # Sample count of references to valid blocks.
system.cpu3.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu3.icache.tagsinuse                85.462768                       # Cycle average of tags in use
system.cpu3.icache.total_refs                   25536                       # Total number of references to valid blocks.
system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.icache.writebacks                       0                       # number of writebacks
system.cpu3.idleCycles                           3421                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.iew.EXEC:branches                   43744                       # Number of branches executed
system.cpu3.iew.EXEC:nop                        34814                       # number of nop insts executed
system.cpu3.iew.EXEC:rate                    1.024765                       # Inst execution rate
system.cpu3.iew.EXEC:refs                       95207                       # number of memory reference insts executed
system.cpu3.iew.EXEC:stores                     29059                       # Number of stores executed
system.cpu3.iew.EXEC:swp                            0                       # number of swp insts executed
system.cpu3.iew.WB:consumers                   115240                       # num instructions consuming a value
system.cpu3.iew.WB:count                       203888                       # cumulative count of insts written-back
system.cpu3.iew.WB:fanout                    0.968327                       # average fanout of values written-back
system.cpu3.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu3.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.iew.WB:producers                   111590                       # num instructions producing a value
system.cpu3.iew.WB:rate                      1.022969                       # insts written-back per cycle
system.cpu3.iew.WB:sent                        204019                       # cumulative count of insts sent to commit
system.cpu3.iew.branchMispredicts                1193                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewBlockCycles                   1619                       # Number of cycles IEW is blocking
system.cpu3.iew.iewDispLoadInsts                66949                       # Number of dispatched load instructions
system.cpu3.iew.iewDispNonSpecInsts               934                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewDispSquashedInsts              572                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispStoreInsts               29464                       # Number of dispatched store instructions
system.cpu3.iew.iewDispatchedInsts             242942                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewExecLoadInsts                66148                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts              960                       # Number of squashed instructions skipped in execute
system.cpu3.iew.iewExecutedInsts               204246                       # Number of executed instructions
system.cpu3.iew.iewIQFullEvents                    42                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.iewSquashCycles                  1781                       # Number of cycles IEW is squashing
system.cpu3.iew.iewUnblockCycles                   47                       # Number of cycles IEW is unblocking
system.cpu3.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread.0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.lsq.thread.0.forwLoads          24834                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread.0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread.0.memOrderViolation           29                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread.0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread.0.squashedLoads         1517                       # Number of loads squashed
system.cpu3.iew.lsq.thread.0.squashedStores          742                       # Number of stores squashed
system.cpu3.iew.memOrderViolationEvents            29                       # Number of memory order violations
system.cpu3.iew.predictedNotTakenIncorrect          182                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.predictedTakenIncorrect          1011                       # Number of branches that were predicted taken incorrectly
system.cpu3.int_regfile_reads                  343072                       # number of integer regfile reads
system.cpu3.int_regfile_writes                 159978                       # number of integer regfile writes
system.cpu3.ipc                              0.963785                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        0.963785                       # IPC: Total IPC of All Threads
system.cpu3.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::IntAlu         101269     49.35%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::IntMult             0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatAdd            0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatDiv            0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdAdd             0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdAlu             0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdCmp             0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdCvt             0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdMisc            0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdMult            0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdSqrt            0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     49.35% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::MemRead         74848     36.47%     85.82% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::MemWrite        29089     14.18%    100.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::total          205206                       # Type of FU issued
system.cpu3.iq.ISSUE:fu_busy_cnt                  188                       # FU busy when requested
system.cpu3.iq.ISSUE:fu_busy_rate            0.000916                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::IntAlu               11      5.85%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::IntMult               0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::IntDiv                0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatAdd              0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatCmp              0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatCvt              0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatMult             0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatDiv              0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatSqrt             0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdAdd               0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdAddAcc            0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdAlu               0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdCmp               0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdCvt               0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdMisc              0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdMult              0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdShift             0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdSqrt              0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      5.85% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::MemRead              46     24.47%     30.32% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::MemWrite            131     69.68%    100.00% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.ISSUE:issued_per_cycle::samples       195889                       # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::mean     1.047563                       # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::stdev     1.235617                       # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::0        95806     48.91%     48.91% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::1        35106     17.92%     66.83% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::2        31374     16.02%     82.85% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::3        29208     14.91%     97.76% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::4         2591      1.32%     99.08% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::5         1562      0.80%     99.88% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::6          150      0.08%     99.95% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::7           82      0.04%     99.99% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::8           10      0.01%    100.00% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::total       195889                       # Number of insts issued each cycle
system.cpu3.iq.ISSUE:rate                    1.029582                       # Inst issue rate
system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu3.iq.int_alu_accesses                205394                       # Number of integer alu accesses
system.cpu3.iq.int_inst_queue_reads            606491                       # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_wakeup_accesses       203888                       # Number of integer instruction queue wakeup accesses
system.cpu3.iq.int_inst_queue_writes           214747                       # Number of integer instruction queue writes
system.cpu3.iq.iqInstsAdded                    198217                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqInstsIssued                   205206                       # Number of instructions issued
system.cpu3.iq.iqNonSpecInstsAdded               9911                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqSquashedInstsExamined           6590                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedInstsIssued                2                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedNonSpecRemoved           673                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.iqSquashedOperandsExamined         6253                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.memDep0.conflictingLoads            33826                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores           24974                       # Number of conflicting stores.
system.cpu3.memDep0.insertedLoads               66949                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores              29464                       # Number of stores inserted to the mem dependence unit.
system.cpu3.misc_regfile_reads                  96736                       # number of misc regfile reads
system.cpu3.misc_regfile_writes                   646                       # number of misc regfile writes
system.cpu3.numCycles                          199310                       # number of cpu cycles simulated
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.rename.RENAME:BlockCycles            9536                       # Number of cycles rename is blocking
system.cpu3.rename.RENAME:CommittedMaps        157468                       # Number of HB maps that are committed
system.cpu3.rename.RENAME:IQFullEvents             52                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.RENAME:IdleCycles            68516                       # Number of cycles rename is idle
system.cpu3.rename.RENAME:LSQFullEvents            39                       # Number of times rename has blocked due to LSQ full
system.cpu3.rename.RENAME:RenameLookups        451555                       # Number of register rename lookups that rename has made
system.cpu3.rename.RENAME:RenamedInsts         245166                       # Number of instructions processed by rename
system.cpu3.rename.RENAME:RenamedOperands       165603                       # Number of destination operands rename has renamed
system.cpu3.rename.RENAME:RunCycles             95731                       # Number of cycles rename is running
system.cpu3.rename.RENAME:SquashCycles           1781                       # Number of cycles rename is squashing
system.cpu3.rename.RENAME:UnblockCycles           570                       # Number of cycles rename is unblocking
system.cpu3.rename.RENAME:UndoneMaps             8135                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.RENAME:int_rename_lookups       451555                       # Number of integer rename lookups
system.cpu3.rename.RENAME:serializeStallCycles        13138                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RENAME:serializingInsts          958                       # count of serializing insts renamed
system.cpu3.rename.RENAME:skidInsts              2735                       # count of insts added to the skid buffer
system.cpu3.rename.RENAME:tempSerializingInsts         1009                       # count of temporary serializing insts renamed
system.cpu3.rob.rob_reads                      429330                       # The number of ROB reads
system.cpu3.rob.rob_writes                     487605                       # The number of ROB writes
system.cpu3.timesIdled                            294                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.l2c.ReadExReq_accesses::0                   94                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1                   12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::2                   13                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::3                   12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_avg_miss_latency::0 73164.893617                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1       573125                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::2 529038.461538                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::3       573125                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 1748453.355155                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40293.893130                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_miss_latency             6877500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate::0                   1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::1                   1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::2                   1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::3                   1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total               4                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses::0                     94                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::1                     12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::2                     13                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::3                     12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
system.l2c.ReadExReq_mshr_miss_latency        5278500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate::0       1.393617                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1      10.916667                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::2      10.076923                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::3      10.916667                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total    33.303873                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_misses                  131                       # number of ReadExReq MSHR misses
system.l2c.ReadReq_accesses::0                    689                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1                    453                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::2                    454                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::3                    456                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total               2052                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_avg_miss_latency::0   63645.879733                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1   1905133.333333                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::2         348500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::3        7144250                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 9461529.213066                       # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_hits::0                        240                       # number of ReadReq hits
system.l2c.ReadReq_hits::1                        438                       # number of ReadReq hits
system.l2c.ReadReq_hits::2                        372                       # number of ReadReq hits
system.l2c.ReadReq_hits::3                        452                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                   1502                       # number of ReadReq hits
system.l2c.ReadReq_miss_latency              28577000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate::0              0.651669                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1              0.033113                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::2              0.180617                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::3              0.008772                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.874170                       # miss rate for ReadReq accesses
system.l2c.ReadReq_misses::0                      449                       # number of ReadReq misses
system.l2c.ReadReq_misses::1                       15                       # number of ReadReq misses
system.l2c.ReadReq_misses::2                       82                       # number of ReadReq misses
system.l2c.ReadReq_misses::3                        4                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  550                       # number of ReadReq misses
system.l2c.ReadReq_mshr_hits                        7                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_miss_latency         21720000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::0         0.788099                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1         1.198675                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::2         1.196035                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::3         1.190789                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     4.373599                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses                    543                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_accesses::0                  29                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::1                  24                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::2                  23                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::3                  21                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              97                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_avg_miss_latency::0         6000                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1         6500                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::2  6782.608696                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::3  7428.571429                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 26711.180124                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_hits::0                       3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_miss_latency             156000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_rate::0           0.896552                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::1                  1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::2                  1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::3                  1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       3.896552                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses::0                    26                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::1                    24                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::2                    23                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::3                    21                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                94                       # number of UpgradeReq misses
system.l2c.UpgradeReq_mshr_miss_latency       3760000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate::0      3.241379                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1      3.916667                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::2      4.086957                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::3      4.476190                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total    15.721193                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_misses                  94                       # number of UpgradeReq MSHR misses
system.l2c.Writeback_accesses::0                    9                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total                9                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0                        9                       # number of Writeback hits
system.l2c.Writeback_hits::total                    9                       # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.avg_refs                          2.750459                       # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.demand_accesses::0                     783                       # number of demand (read+write) accesses
system.l2c.demand_accesses::1                     465                       # number of demand (read+write) accesses
system.l2c.demand_accesses::2                     467                       # number of demand (read+write) accesses
system.l2c.demand_accesses::3                     468                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total                2183                       # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency::0    65293.738490                       # average overall miss latency
system.l2c.demand_avg_miss_latency::1    1313129.629630                       # average overall miss latency
system.l2c.demand_avg_miss_latency::2    373205.263158                       # average overall miss latency
system.l2c.demand_avg_miss_latency::3    2215906.250000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 3967534.881277                       # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency  40057.121662                       # average overall mshr miss latency
system.l2c.demand_hits::0                         240                       # number of demand (read+write) hits
system.l2c.demand_hits::1                         438                       # number of demand (read+write) hits
system.l2c.demand_hits::2                         372                       # number of demand (read+write) hits
system.l2c.demand_hits::3                         452                       # number of demand (read+write) hits
system.l2c.demand_hits::total                    1502                       # number of demand (read+write) hits
system.l2c.demand_miss_latency               35454500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate::0               0.693487                       # miss rate for demand accesses
system.l2c.demand_miss_rate::1               0.058065                       # miss rate for demand accesses
system.l2c.demand_miss_rate::2               0.203426                       # miss rate for demand accesses
system.l2c.demand_miss_rate::3               0.034188                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.989165                       # miss rate for demand accesses
system.l2c.demand_misses::0                       543                       # number of demand (read+write) misses
system.l2c.demand_misses::1                        27                       # number of demand (read+write) misses
system.l2c.demand_misses::2                        95                       # number of demand (read+write) misses
system.l2c.demand_misses::3                        16                       # number of demand (read+write) misses
system.l2c.demand_misses::total                   681                       # number of demand (read+write) misses
system.l2c.demand_mshr_hits                         7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency          26998500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0          0.860792                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1          1.449462                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::2          1.443255                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::3          1.440171                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      5.193680                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses                     674                       # number of demand (read+write) MSHR misses
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.l2c.occ_%::0                          0.005562                       # Average percentage of cache occupancy
system.l2c.occ_%::1                          0.000156                       # Average percentage of cache occupancy
system.l2c.occ_%::2                          0.000959                       # Average percentage of cache occupancy
system.l2c.occ_%::3                          0.000038                       # Average percentage of cache occupancy
system.l2c.occ_%::4                          0.000079                       # Average percentage of cache occupancy
system.l2c.occ_blocks::0                   364.492731                       # Average occupied blocks per context
system.l2c.occ_blocks::1                    10.237276                       # Average occupied blocks per context
system.l2c.occ_blocks::2                    62.878855                       # Average occupied blocks per context
system.l2c.occ_blocks::3                     2.477387                       # Average occupied blocks per context
system.l2c.occ_blocks::4                     5.202251                       # Average occupied blocks per context
system.l2c.overall_accesses::0                    783                       # number of overall (read+write) accesses
system.l2c.overall_accesses::1                    465                       # number of overall (read+write) accesses
system.l2c.overall_accesses::2                    467                       # number of overall (read+write) accesses
system.l2c.overall_accesses::3                    468                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total               2183                       # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency::0   65293.738490                       # average overall miss latency
system.l2c.overall_avg_miss_latency::1   1313129.629630                       # average overall miss latency
system.l2c.overall_avg_miss_latency::2   373205.263158                       # average overall miss latency
system.l2c.overall_avg_miss_latency::3   2215906.250000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 3967534.881277                       # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 40057.121662                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.l2c.overall_hits::0                        240                       # number of overall hits
system.l2c.overall_hits::1                        438                       # number of overall hits
system.l2c.overall_hits::2                        372                       # number of overall hits
system.l2c.overall_hits::3                        452                       # number of overall hits
system.l2c.overall_hits::total                   1502                       # number of overall hits
system.l2c.overall_miss_latency              35454500                       # number of overall miss cycles
system.l2c.overall_miss_rate::0              0.693487                       # miss rate for overall accesses
system.l2c.overall_miss_rate::1              0.058065                       # miss rate for overall accesses
system.l2c.overall_miss_rate::2              0.203426                       # miss rate for overall accesses
system.l2c.overall_miss_rate::3              0.034188                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.989165                       # miss rate for overall accesses
system.l2c.overall_misses::0                      543                       # number of overall misses
system.l2c.overall_misses::1                       27                       # number of overall misses
system.l2c.overall_misses::2                       95                       # number of overall misses
system.l2c.overall_misses::3                       16                       # number of overall misses
system.l2c.overall_misses::total                  681                       # number of overall misses
system.l2c.overall_mshr_hits                        7                       # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency         26998500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0         0.860792                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1         1.449462                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::2         1.443255                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::3         1.440171                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     5.193680                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses                    674                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.replacements                             0                       # number of replacements
system.l2c.sampled_refs                           545                       # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse                       445.288501                       # Cycle average of tags in use
system.l2c.total_refs                            1499                       # Total number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.writebacks                               0                       # number of writebacks

---------- End Simulation Statistics   ----------