gem5/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

---------- Begin Simulation Statistics ----------
host_inst_rate                                 133732                       # Simulator instruction rate (inst/s)
host_mem_usage                                 214280                       # Number of bytes of host memory used
host_seconds                                     8.62                       # Real time elapsed on the host
host_tick_rate                               13623692                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                     1153323                       # Number of instructions simulated
sim_seconds                                  0.000117                       # Number of seconds simulated
sim_ticks                                   117496500                       # Number of ticks simulated
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.BTBHits                   89278                       # Number of BTB hits
system.cpu0.BPredUnit.BTBLookups                91911                       # Number of BTB lookups
system.cpu0.BPredUnit.RASInCorrect                  0                       # Number of incorrect RAS predictions.
system.cpu0.BPredUnit.condIncorrect              1075                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.condPredicted             92364                       # Number of conditional branches predicted
system.cpu0.BPredUnit.lookups                   92364                       # Number of BP lookups
system.cpu0.BPredUnit.usedRAS                       0                       # Number of times the RAS was used to get a target.
system.cpu0.commit.COM:branches                 89553                       # Number of branches committed
system.cpu0.commit.COM:bw_lim_events              219                       # number cycles where commit BW limit reached
system.cpu0.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
system.cpu0.commit.COM:committed_per_cycle::samples       214839                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::mean     2.488128                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::stdev     2.121442                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::0        33722     15.70%     15.70% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::1        90658     42.20%     57.89% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::2         2488      1.16%     59.05% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::3          738      0.34%     59.40% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::4          743      0.35%     59.74% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::5        85727     39.90%     99.64% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::6          468      0.22%     99.86% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::7           76      0.04%     99.90% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::8          219      0.10%    100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::total       214839                       # Number of insts commited each cycle
system.cpu0.commit.COM:count                   534547                       # Number of instructions committed
system.cpu0.commit.COM:loads                   174318                       # Number of loads committed
system.cpu0.commit.COM:membars                     84                       # Number of memory barriers committed
system.cpu0.commit.COM:refs                    261983                       # Number of memory references committed
system.cpu0.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
system.cpu0.commit.branchMispredicts             1075                       # The number of times a branch was mispredicted
system.cpu0.commit.commitCommittedInsts        534547                       # The number of committed instructions
system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.commitSquashedInsts           9542                       # The number of squashed insts skipped by commit
system.cpu0.committedInsts                     448179                       # Number of Instructions Simulated
system.cpu0.committedInsts_total               448179                       # Number of Instructions Simulated
system.cpu0.cpi                              0.524331                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        0.524331                       # CPI: Total CPI of All Threads
system.cpu0.dcache.ReadReq_accesses             89513                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_avg_miss_latency 27025.458248                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27734.972678                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_hits                 89022                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_miss_latency      13269500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_rate         0.005485                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_misses                 491                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_mshr_hits              308                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_miss_latency      5075500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate     0.002044                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_misses            183                       # number of ReadReq MSHR misses
system.cpu0.dcache.SwapReq_accesses                42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_avg_miss_latency 16807.692308                       # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 13807.692308                       # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_hits                    16                       # number of SwapReq hits
system.cpu0.dcache.SwapReq_miss_latency        437000                       # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_rate         0.619048                       # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_misses                  26                       # number of SwapReq misses
system.cpu0.dcache.SwapReq_mshr_miss_latency       359000                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_rate     0.619048                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_misses             26                       # number of SwapReq MSHR misses
system.cpu0.dcache.WriteReq_accesses            87623                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_avg_miss_latency 46095.340741                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36862.857143                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_hits                87083                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_miss_latency     24891484                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_rate        0.006163                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_misses                540                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_mshr_hits             365                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_miss_latency      6451000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_rate     0.001997                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_misses           175                       # number of WriteReq MSHR misses
system.cpu0.dcache.avg_blocked_cycles::no_mshrs  8595.238095                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs                607.620690                       # Average number of references to valid blocks.
system.cpu0.dcache.blocked::no_mshrs               21                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_mshrs       180500                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.demand_accesses             177136                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_avg_miss_latency 37013.563531                       # average overall miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency 32196.927374                       # average overall mshr miss latency
system.cpu0.dcache.demand_hits                 176105                       # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency       38160984                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_rate          0.005820                       # miss rate for demand accesses
system.cpu0.dcache.demand_misses                 1031                       # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits               673                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency     11526500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_rate     0.002021                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_misses             358                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.occ_%::0                  0.275951                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_%::1                 -0.002548                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_blocks::0           141.286787                       # Average occupied blocks per context
system.cpu0.dcache.occ_blocks::1            -1.304354                       # Average occupied blocks per context
system.cpu0.dcache.overall_accesses            177136                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency 37013.563531                       # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency 32196.927374                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_hits                176105                       # number of overall hits
system.cpu0.dcache.overall_miss_latency      38160984                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_rate         0.005820                       # miss rate for overall accesses
system.cpu0.dcache.overall_misses                1031                       # number of overall misses
system.cpu0.dcache.overall_mshr_hits              673                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency     11526500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_rate     0.002021                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_misses            358                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.replacements                     9                       # number of replacements
system.cpu0.dcache.sampled_refs                   174                       # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.dcache.tagsinuse               139.982434                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                  105726                       # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks                       6                       # number of writebacks
system.cpu0.decode.DECODE:BlockedCycles         13489                       # Number of cycles decode is blocked
system.cpu0.decode.DECODE:DecodedInsts         549068                       # Number of instructions handled by decode
system.cpu0.decode.DECODE:IdleCycles            20046                       # Number of cycles decode is idle
system.cpu0.decode.DECODE:RunCycles            181085                       # Number of cycles decode is running
system.cpu0.decode.DECODE:SquashCycles           2062                       # Number of cycles decode is squashing
system.cpu0.decode.DECODE:UnblockCycles           202                       # Number of cycles decode is unblocking
system.cpu0.fetch.Branches                      92364                       # Number of branches that fetch encountered
system.cpu0.fetch.CacheLines                     5264                       # Number of cache lines fetched
system.cpu0.fetch.Cycles                       181529                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.IcacheSquashes                  482                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.Insts                        550067                       # Number of instructions fetch has processed
system.cpu0.fetch.MiscStallCycles                  41                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.SquashCycles                   1232                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.branchRate                 0.393048                       # Number of branch fetches per cycle
system.cpu0.fetch.icacheStallCycles              5264                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.predictedBranches             89278                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.rate                       2.340770                       # Number of inst fetches per cycle
system.cpu0.fetch.rateDist::samples            216884                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             2.536227                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.186778                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                   35355     16.30%     16.30% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                   90192     41.59%     57.89% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                     488      0.23%     58.11% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                     808      0.37%     58.48% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                     588      0.27%     58.76% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                   86546     39.90%     98.66% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                     826      0.38%     99.04% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                     211      0.10%     99.14% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                    1870      0.86%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total              216884                       # Number of instructions fetched each cycle (Total)
system.cpu0.icache.ReadReq_accesses              5264                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_avg_miss_latency 39056.216931                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency 37012.315271                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_hits                  4508                       # number of ReadReq hits
system.cpu0.icache.ReadReq_miss_latency      29526500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_rate         0.143617                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_misses                 756                       # number of ReadReq misses
system.cpu0.icache.ReadReq_mshr_hits              147                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_miss_latency     22540500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate     0.115691                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_misses            609                       # number of ReadReq MSHR misses
system.cpu0.icache.avg_blocked_cycles::no_mshrs        11000                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.icache.avg_refs                  7.414474                       # Average number of references to valid blocks.
system.cpu0.icache.blocked::no_mshrs                2                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_mshrs        22000                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.demand_accesses               5264                       # number of demand (read+write) accesses
system.cpu0.icache.demand_avg_miss_latency 39056.216931                       # average overall miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency 37012.315271                       # average overall mshr miss latency
system.cpu0.icache.demand_hits                   4508                       # number of demand (read+write) hits
system.cpu0.icache.demand_miss_latency       29526500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_rate          0.143617                       # miss rate for demand accesses
system.cpu0.icache.demand_misses                  756                       # number of demand (read+write) misses
system.cpu0.icache.demand_mshr_hits               147                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_miss_latency     22540500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_rate     0.115691                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_misses             609                       # number of demand (read+write) MSHR misses
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.occ_%::0                  0.502840                       # Average percentage of cache occupancy
system.cpu0.icache.occ_blocks::0           257.454218                       # Average occupied blocks per context
system.cpu0.icache.overall_accesses              5264                       # number of overall (read+write) accesses
system.cpu0.icache.overall_avg_miss_latency 39056.216931                       # average overall miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency 37012.315271                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_hits                  4508                       # number of overall hits
system.cpu0.icache.overall_miss_latency      29526500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_rate         0.143617                       # miss rate for overall accesses
system.cpu0.icache.overall_misses                 756                       # number of overall misses
system.cpu0.icache.overall_mshr_hits              147                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_miss_latency     22540500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_rate     0.115691                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_misses            609                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.icache.replacements                   307                       # number of replacements
system.cpu0.icache.sampled_refs                   608                       # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.icache.tagsinuse               257.454218                       # Cycle average of tags in use
system.cpu0.icache.total_refs                    4508                       # Total number of references to valid blocks.
system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks                       0                       # number of writebacks
system.cpu0.idleCycles                          18110                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.iew.EXEC:branches                   90363                       # Number of branches executed
system.cpu0.iew.EXEC:nop                        86742                       # number of nop insts executed
system.cpu0.iew.EXEC:rate                    1.932130                       # Inst execution rate
system.cpu0.iew.EXEC:refs                      263654                       # number of memory reference insts executed
system.cpu0.iew.EXEC:stores                     88201                       # Number of stores executed
system.cpu0.iew.EXEC:swp                            0                       # number of swp insts executed
system.cpu0.iew.WB:consumers                   270968                       # num instructions consuming a value
system.cpu0.iew.WB:count                       453412                       # cumulative count of insts written-back
system.cpu0.iew.WB:fanout                    0.992922                       # average fanout of values written-back
system.cpu0.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.iew.WB:producers                   269050                       # num instructions producing a value
system.cpu0.iew.WB:rate                      1.929462                       # insts written-back per cycle
system.cpu0.iew.WB:sent                        453657                       # cumulative count of insts sent to commit
system.cpu0.iew.branchMispredicts                1246                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewBlockCycles                    822                       # Number of cycles IEW is blocking
system.cpu0.iew.iewDispLoadInsts               176000                       # Number of dispatched load instructions
system.cpu0.iew.iewDispNonSpecInsts               727                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewDispSquashedInsts              482                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispStoreInsts               88746                       # Number of dispatched store instructions
system.cpu0.iew.iewDispatchedInsts             544085                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewExecLoadInsts               175453                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts              917                       # Number of squashed instructions skipped in execute
system.cpu0.iew.iewExecutedInsts               454039                       # Number of executed instructions
system.cpu0.iew.iewIQFullEvents                    24                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.iewSquashCycles                  2062                       # Number of cycles IEW is squashing
system.cpu0.iew.iewUnblockCycles                   27                       # Number of cycles IEW is unblocking
system.cpu0.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread.0.cacheBlocked           18                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.lsq.thread.0.forwLoads          85889                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread.0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread.0.memOrderViolation           74                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread.0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread.0.squashedLoads         1682                       # Number of loads squashed
system.cpu0.iew.lsq.thread.0.squashedStores         1081                       # Number of stores squashed
system.cpu0.iew.memOrderViolationEvents            74                       # Number of memory order violations
system.cpu0.iew.predictedNotTakenIncorrect          821                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.predictedTakenIncorrect           425                       # Number of branches that were predicted taken incorrectly
system.cpu0.ipc                              1.907193                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        1.907193                       # IPC: Total IPC of All Threads
system.cpu0.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntAlu         190895     41.96%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntMult             0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatAdd            0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatDiv            0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdAdd             0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdAlu             0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdCmp             0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdCvt             0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdMisc            0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdMult            0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdSqrt            0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     41.96% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::MemRead        175746     38.63%     80.59% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::MemWrite        88315     19.41%    100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::total          454956                       # Type of FU issued
system.cpu0.iq.ISSUE:fu_busy_cnt                  227                       # FU busy when requested
system.cpu0.iq.ISSUE:fu_busy_rate            0.000499                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntAlu               33     14.54%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntMult               0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntDiv                0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatAdd              0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatCmp              0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatCvt              0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatMult             0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatDiv              0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatSqrt             0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdAdd               0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdAddAcc            0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdAlu               0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdCmp               0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdCvt               0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdMisc              0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdMult              0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdShift             0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdSqrt              0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%     14.54% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::MemRead              85     37.44%     51.98% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::MemWrite            109     48.02%    100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:issued_per_cycle::samples       216884                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::mean     2.097693                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::stdev     1.057244                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::0        33388     15.39%     15.39% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::1         5635      2.60%     17.99% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::2        88185     40.66%     58.65% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::3        87166     40.19%     98.84% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::4         1498      0.69%     99.53% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::5          719      0.33%     99.86% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::6          194      0.09%     99.95% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::7           90      0.04%    100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::8            9      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::total       216884                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:rate                    1.936032                       # Inst issue rate
system.cpu0.iq.iqInstsAdded                    456518                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqInstsIssued                   454956                       # Number of instructions issued
system.cpu0.iq.iqNonSpecInstsAdded                825                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqSquashedInstsExamined           8243                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedInstsIssued               90                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedNonSpecRemoved           266                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.iqSquashedOperandsExamined         6865                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.memDep0.conflictingLoads            86252                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores           86102                       # Number of conflicting stores.
system.cpu0.memDep0.insertedLoads              176000                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores              88746                       # Number of stores inserted to the mem dependence unit.
system.cpu0.numCycles                          234994                       # number of cpu cycles simulated
system.cpu0.rename.RENAME:BlockCycles            1211                       # Number of cycles rename is blocking
system.cpu0.rename.RENAME:CommittedMaps        361468                       # Number of HB maps that are committed
system.cpu0.rename.RENAME:IQFullEvents              6                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.RENAME:IdleCycles            20733                       # Number of cycles rename is idle
system.cpu0.rename.RENAME:LSQFullEvents           291                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RENAME:RenameLookups       1089130                       # Number of register rename lookups that rename has made
system.cpu0.rename.RENAME:RenamedInsts         545907                       # Number of instructions processed by rename
system.cpu0.rename.RENAME:RenamedOperands       371790                       # Number of destination operands rename has renamed
system.cpu0.rename.RENAME:RunCycles            180641                       # Number of cycles rename is running
system.cpu0.rename.RENAME:SquashCycles           2062                       # Number of cycles rename is squashing
system.cpu0.rename.RENAME:UnblockCycles           697                       # Number of cycles rename is unblocking
system.cpu0.rename.RENAME:UndoneMaps            10322                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.RENAME:serializeStallCycles        11540                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RENAME:serializingInsts          809                       # count of serializing insts renamed
system.cpu0.rename.RENAME:skidInsts              4202                       # count of insts added to the skid buffer
system.cpu0.rename.RENAME:tempSerializingInsts          812                       # count of temporary serializing insts renamed
system.cpu0.timesIdled                            337                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.workload.PROG:num_syscalls             89                       # Number of system calls
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.BTBHits                   41740                       # Number of BTB hits
system.cpu1.BPredUnit.BTBLookups                43967                       # Number of BTB lookups
system.cpu1.BPredUnit.RASInCorrect                  0                       # Number of incorrect RAS predictions.
system.cpu1.BPredUnit.condIncorrect              1106                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.condPredicted             44023                       # Number of conditional branches predicted
system.cpu1.BPredUnit.lookups                   44023                       # Number of BP lookups
system.cpu1.BPredUnit.usedRAS                       0                       # Number of times the RAS was used to get a target.
system.cpu1.commit.COM:branches                 41195                       # Number of branches committed
system.cpu1.commit.COM:bw_lim_events              485                       # number cycles where commit BW limit reached
system.cpu1.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
system.cpu1.commit.COM:committed_per_cycle::samples       187667                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::mean     1.179936                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::stdev     1.750960                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::0       100980     53.81%     53.81% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::1        41996     22.38%     76.19% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::2         7478      3.98%     80.17% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::3        10619      5.66%     85.83% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::4         2461      1.31%     87.14% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::5        23116     12.32%     99.46% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::6          402      0.21%     99.67% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::7          130      0.07%     99.74% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::8          485      0.26%    100.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::total       187667                       # Number of insts commited each cycle
system.cpu1.commit.COM:count                   221435                       # Number of instructions committed
system.cpu1.commit.COM:loads                    60856                       # Number of loads committed
system.cpu1.commit.COM:membars                   9088                       # Number of memory barriers committed
system.cpu1.commit.COM:refs                     87006                       # Number of memory references committed
system.cpu1.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
system.cpu1.commit.branchMispredicts             1106                       # The number of times a branch was mispredicted
system.cpu1.commit.commitCommittedInsts        221435                       # The number of committed instructions
system.cpu1.commit.commitNonSpecStalls           9806                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.commitSquashedInsts           8244                       # The number of squashed insts skipped by commit
system.cpu1.committedInsts                     180366                       # Number of Instructions Simulated
system.cpu1.committedInsts_total               180366                       # Number of Instructions Simulated
system.cpu1.cpi                              1.108479                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.108479                       # CPI: Total CPI of All Threads
system.cpu1.dcache.ReadReq_accesses             39263                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_avg_miss_latency 22504.819277                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 14511.904762                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_hits                 38848                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_miss_latency       9339500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_rate         0.010570                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_misses                 415                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_mshr_hits              247                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_miss_latency      2438000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate     0.004279                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_misses            168                       # number of ReadReq MSHR misses
system.cpu1.dcache.SwapReq_accesses                72                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_avg_miss_latency 25946.428571                       # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 22946.428571                       # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_hits                    16                       # number of SwapReq hits
system.cpu1.dcache.SwapReq_miss_latency       1453000                       # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_rate         0.777778                       # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_misses                  56                       # number of SwapReq misses
system.cpu1.dcache.SwapReq_mshr_miss_latency      1285000                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_rate     0.777778                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_misses             56                       # number of SwapReq MSHR misses
system.cpu1.dcache.WriteReq_accesses            26078                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_avg_miss_latency 24129.166667                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency        15810                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_hits                25958                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_miss_latency      2895500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_rate        0.004602                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_misses                120                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_mshr_hits              20                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_miss_latency      1581000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_rate     0.003835                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_misses           100                       # number of WriteReq MSHR misses
system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_refs               1063.866667                       # Average number of references to valid blocks.
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.demand_accesses              65341                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_avg_miss_latency 22869.158879                       # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency 14996.268657                       # average overall mshr miss latency
system.cpu1.dcache.demand_hits                  64806                       # number of demand (read+write) hits
system.cpu1.dcache.demand_miss_latency       12235000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_rate          0.008188                       # miss rate for demand accesses
system.cpu1.dcache.demand_misses                  535                       # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits               267                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency      4019000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate     0.004102                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_misses             268                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.occ_%::0                  0.047224                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_%::1                 -0.015258                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_blocks::0            24.178499                       # Average occupied blocks per context
system.cpu1.dcache.occ_blocks::1            -7.812139                       # Average occupied blocks per context
system.cpu1.dcache.overall_accesses             65341                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_avg_miss_latency 22869.158879                       # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency 14996.268657                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_hits                 64806                       # number of overall hits
system.cpu1.dcache.overall_miss_latency      12235000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_rate         0.008188                       # miss rate for overall accesses
system.cpu1.dcache.overall_misses                 535                       # number of overall misses
system.cpu1.dcache.overall_mshr_hits              267                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_miss_latency      4019000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate     0.004102                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_misses            268                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.replacements                     2                       # number of replacements
system.cpu1.dcache.sampled_refs                    30                       # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.dcache.tagsinuse                16.366360                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                   31916                       # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.writebacks                       1                       # number of writebacks
system.cpu1.decode.DECODE:BlockedCycles         23978                       # Number of cycles decode is blocked
system.cpu1.decode.DECODE:DecodedInsts         233739                       # Number of instructions handled by decode
system.cpu1.decode.DECODE:IdleCycles            70922                       # Number of cycles decode is idle
system.cpu1.decode.DECODE:RunCycles             84431                       # Number of cycles decode is running
system.cpu1.decode.DECODE:SquashCycles           1784                       # Number of cycles decode is squashing
system.cpu1.decode.DECODE:UnblockCycles          8335                       # Number of cycles decode is unblocking
system.cpu1.fetch.Branches                      44023                       # Number of branches that fetch encountered
system.cpu1.fetch.CacheLines                    27242                       # Number of cache lines fetched
system.cpu1.fetch.Cycles                        93139                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.IcacheSquashes                  219                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.Insts                        234880                       # Number of instructions fetch has processed
system.cpu1.fetch.MiscStallCycles                  23                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.SquashCycles                   1183                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.branchRate                 0.220190                       # Number of branch fetches per cycle
system.cpu1.fetch.icacheStallCycles             27242                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.predictedBranches             41740                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.rate                       1.174799                       # Number of inst fetches per cycle
system.cpu1.fetch.rateDist::samples            196087                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.197836                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            1.836209                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                  102948     52.50%     52.50% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                   49979     25.49%     77.99% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                   10332      5.27%     83.26% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                    2701      1.38%     84.64% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                    1922      0.98%     85.62% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   23991     12.23%     97.85% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                    2480      1.26%     99.12% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                     261      0.13%     99.25% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                    1473      0.75%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total              196087                       # Number of instructions fetched each cycle (Total)
system.cpu1.icache.ReadReq_accesses             27242                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_avg_miss_latency 15144.329897                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12327.702703                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_hits                 26757                       # number of ReadReq hits
system.cpu1.icache.ReadReq_miss_latency       7345000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_rate         0.017803                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_misses                 485                       # number of ReadReq misses
system.cpu1.icache.ReadReq_mshr_hits               41                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_miss_latency      5473500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate     0.016298                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_misses            444                       # number of ReadReq MSHR misses
system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.icache.avg_refs                 60.263514                       # Average number of references to valid blocks.
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.demand_accesses              27242                       # number of demand (read+write) accesses
system.cpu1.icache.demand_avg_miss_latency 15144.329897                       # average overall miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency 12327.702703                       # average overall mshr miss latency
system.cpu1.icache.demand_hits                  26757                       # number of demand (read+write) hits
system.cpu1.icache.demand_miss_latency        7345000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_rate          0.017803                       # miss rate for demand accesses
system.cpu1.icache.demand_misses                  485                       # number of demand (read+write) misses
system.cpu1.icache.demand_mshr_hits                41                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_miss_latency      5473500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_rate     0.016298                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_misses             444                       # number of demand (read+write) MSHR misses
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.occ_%::0                  0.166395                       # Average percentage of cache occupancy
system.cpu1.icache.occ_blocks::0            85.194355                       # Average occupied blocks per context
system.cpu1.icache.overall_accesses             27242                       # number of overall (read+write) accesses
system.cpu1.icache.overall_avg_miss_latency 15144.329897                       # average overall miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency 12327.702703                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_hits                 26757                       # number of overall hits
system.cpu1.icache.overall_miss_latency       7345000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_rate         0.017803                       # miss rate for overall accesses
system.cpu1.icache.overall_misses                 485                       # number of overall misses
system.cpu1.icache.overall_mshr_hits               41                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_miss_latency      5473500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_rate     0.016298                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_misses            444                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.icache.replacements                   332                       # number of replacements
system.cpu1.icache.sampled_refs                   444                       # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.icache.tagsinuse                85.194355                       # Cycle average of tags in use
system.cpu1.icache.total_refs                   26757                       # Total number of references to valid blocks.
system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks                       0                       # number of writebacks
system.cpu1.idleCycles                           3845                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.iew.EXEC:branches                   41746                       # Number of branches executed
system.cpu1.iew.EXEC:nop                        32789                       # number of nop insts executed
system.cpu1.iew.EXEC:rate                    0.965868                       # Inst execution rate
system.cpu1.iew.EXEC:refs                       88018                       # number of memory reference insts executed
system.cpu1.iew.EXEC:stores                     26481                       # Number of stores executed
system.cpu1.iew.EXEC:swp                            0                       # number of swp insts executed
system.cpu1.iew.WB:consumers                   108078                       # num instructions consuming a value
system.cpu1.iew.WB:count                       192754                       # cumulative count of insts written-back
system.cpu1.iew.WB:fanout                    0.966228                       # average fanout of values written-back
system.cpu1.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.iew.WB:producers                   104428                       # num instructions producing a value
system.cpu1.iew.WB:rate                      0.964098                       # insts written-back per cycle
system.cpu1.iew.WB:sent                        192883                       # cumulative count of insts sent to commit
system.cpu1.iew.branchMispredicts                1199                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewBlockCycles                   1512                       # Number of cycles IEW is blocking
system.cpu1.iew.iewDispLoadInsts                62331                       # Number of dispatched load instructions
system.cpu1.iew.iewDispNonSpecInsts               947                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewDispSquashedInsts              594                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispStoreInsts               26882                       # Number of dispatched store instructions
system.cpu1.iew.iewDispatchedInsts             229712                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewExecLoadInsts                61537                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts              953                       # Number of squashed instructions skipped in execute
system.cpu1.iew.iewExecutedInsts               193108                       # Number of executed instructions
system.cpu1.iew.iewIQFullEvents                    40                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.iewSquashCycles                  1784                       # Number of cycles IEW is squashing
system.cpu1.iew.iewUnblockCycles                   44                       # Number of cycles IEW is unblocking
system.cpu1.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread.0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.lsq.thread.0.forwLoads          22259                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread.0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread.0.memOrderViolation           35                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread.0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread.0.squashedLoads         1475                       # Number of loads squashed
system.cpu1.iew.lsq.thread.0.squashedStores          732                       # Number of stores squashed
system.cpu1.iew.memOrderViolationEvents            35                       # Number of memory order violations
system.cpu1.iew.predictedNotTakenIncorrect          189                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.predictedTakenIncorrect          1010                       # Number of branches that were predicted taken incorrectly
system.cpu1.ipc                              0.902137                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.902137                       # IPC: Total IPC of All Threads
system.cpu1.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntAlu          96746     49.85%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntMult             0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatAdd            0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatDiv            0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdAdd             0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdAlu             0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdCmp             0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdCvt             0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdMisc            0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdMult            0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt            0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     49.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::MemRead         70805     36.49%     86.34% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::MemWrite        26510     13.66%    100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::total          194061                       # Type of FU issued
system.cpu1.iq.ISSUE:fu_busy_cnt                  185                       # FU busy when requested
system.cpu1.iq.ISSUE:fu_busy_rate            0.000953                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntAlu               11      5.95%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntMult               0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntDiv                0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatAdd              0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatCmp              0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatCvt              0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatMult             0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatDiv              0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatSqrt             0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdAdd               0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdAddAcc            0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdAlu               0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdCmp               0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdCvt               0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdMisc              0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdMult              0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdShift             0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdSqrt              0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      5.95% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::MemRead              43     23.24%     29.19% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::MemWrite            131     70.81%    100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:issued_per_cycle::samples       196087                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::mean     0.989668                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::stdev     1.215562                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::0        99332     50.66%     50.66% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::1        36909     18.82%     69.48% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::2        28876     14.73%     84.21% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::3        26632     13.58%     97.79% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::4         2531      1.29%     99.08% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::5         1564      0.80%     99.88% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::6          151      0.08%     99.95% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::7           82      0.04%     99.99% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::8           10      0.01%    100.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::total       196087                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:rate                    0.970635                       # Inst issue rate
system.cpu1.iq.iqInstsAdded                    186439                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqInstsIssued                   194061                       # Number of instructions issued
system.cpu1.iq.iqNonSpecInstsAdded              10484                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqSquashedInstsExamined           6548                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedInstsIssued                2                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedNonSpecRemoved           678                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.iqSquashedOperandsExamined         6090                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.memDep0.conflictingLoads            31889                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores           22377                       # Number of conflicting stores.
system.cpu1.memDep0.insertedLoads               62331                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores              26882                       # Number of stores inserted to the mem dependence unit.
system.cpu1.numCycles                          199932                       # number of cpu cycles simulated
system.cpu1.rename.RENAME:BlockCycles            9891                       # Number of cycles rename is blocking
system.cpu1.rename.RENAME:CommittedMaps        147748                       # Number of HB maps that are committed
system.cpu1.rename.RENAME:IQFullEvents             48                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.RENAME:IdleCycles            71551                       # Number of cycles rename is idle
system.cpu1.rename.RENAME:LSQFullEvents            40                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RENAME:RenameLookups        422855                       # Number of register rename lookups that rename has made
system.cpu1.rename.RENAME:RenamedInsts         231943                       # Number of instructions processed by rename
system.cpu1.rename.RENAME:RenamedOperands       155885                       # Number of destination operands rename has renamed
system.cpu1.rename.RENAME:RunCycles             92302                       # Number of cycles rename is running
system.cpu1.rename.RENAME:SquashCycles           1784                       # Number of cycles rename is squashing
system.cpu1.rename.RENAME:UnblockCycles           562                       # Number of cycles rename is unblocking
system.cpu1.rename.RENAME:UndoneMaps             8137                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.RENAME:serializeStallCycles        13360                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RENAME:serializingInsts          970                       # count of serializing insts renamed
system.cpu1.rename.RENAME:skidInsts              2743                       # count of insts added to the skid buffer
system.cpu1.rename.RENAME:tempSerializingInsts         1022                       # count of temporary serializing insts renamed
system.cpu1.timesIdled                            297                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.BPredUnit.BTBHits                   58194                       # Number of BTB hits
system.cpu2.BPredUnit.BTBLookups                60389                       # Number of BTB lookups
system.cpu2.BPredUnit.RASInCorrect                  0                       # Number of incorrect RAS predictions.
system.cpu2.BPredUnit.condIncorrect              1085                       # Number of conditional branches incorrect
system.cpu2.BPredUnit.condPredicted             60491                       # Number of conditional branches predicted
system.cpu2.BPredUnit.lookups                   60491                       # Number of BP lookups
system.cpu2.BPredUnit.usedRAS                       0                       # Number of times the RAS was used to get a target.
system.cpu2.commit.COM:branches                 57782                       # Number of branches committed
system.cpu2.commit.COM:bw_lim_events              501                       # number cycles where commit BW limit reached
system.cpu2.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
system.cpu2.commit.COM:committed_per_cycle::samples       185916                       # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::mean     1.779174                       # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::stdev     2.020750                       # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::0        66151     35.58%     35.58% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::1        58504     31.47%     67.05% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::2         7458      4.01%     71.06% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::3         5724      3.08%     74.14% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::4         2452      1.32%     75.46% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::5        44514     23.94%     99.40% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::6          485      0.26%     99.66% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::7          127      0.07%     99.73% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::8          501      0.27%    100.00% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::total       185916                       # Number of insts commited each cycle
system.cpu2.commit.COM:count                   330777                       # Number of instructions committed
system.cpu2.commit.COM:loads                    98945                       # Number of loads committed
system.cpu2.commit.COM:membars                   4183                       # Number of memory barriers committed
system.cpu2.commit.COM:refs                    146579                       # Number of memory references committed
system.cpu2.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
system.cpu2.commit.branchMispredicts             1085                       # The number of times a branch was mispredicted
system.cpu2.commit.commitCommittedInsts        330777                       # The number of committed instructions
system.cpu2.commit.commitNonSpecStalls           4895                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.commitSquashedInsts           8092                       # The number of squashed insts skipped by commit
system.cpu2.committedInsts                     278020                       # Number of Instructions Simulated
system.cpu2.committedInsts_total               278020                       # Number of Instructions Simulated
system.cpu2.cpi                              0.718078                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        0.718078                       # CPI: Total CPI of All Threads
system.cpu2.dcache.ReadReq_accesses             55923                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_avg_miss_latency 22046.336207                       # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 14829.113924                       # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_hits                 55459                       # number of ReadReq hits
system.cpu2.dcache.ReadReq_miss_latency      10229500                       # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_rate         0.008297                       # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_misses                 464                       # number of ReadReq misses
system.cpu2.dcache.ReadReq_mshr_hits              306                       # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_miss_latency      2343000                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate     0.002825                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_misses            158                       # number of ReadReq MSHR misses
system.cpu2.dcache.SwapReq_accesses                66                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_avg_miss_latency 24990.740741                       # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 21990.740741                       # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_hits                    12                       # number of SwapReq hits
system.cpu2.dcache.SwapReq_miss_latency       1349500                       # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_rate         0.818182                       # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_misses                  54                       # number of SwapReq misses
system.cpu2.dcache.SwapReq_mshr_miss_latency      1187500                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_rate     0.818182                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_misses             54                       # number of SwapReq MSHR misses
system.cpu2.dcache.WriteReq_accesses            47568                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_avg_miss_latency 23770.161290                       # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 15316.037736                       # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_hits                47444                       # number of WriteReq hits
system.cpu2.dcache.WriteReq_miss_latency      2947500                       # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_rate        0.002607                       # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_misses                124                       # number of WriteReq misses
system.cpu2.dcache.WriteReq_mshr_hits              18                       # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_miss_latency      1623500                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_rate     0.002228                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_misses           106                       # number of WriteReq MSHR misses
system.cpu2.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_refs               1779.400000                       # Average number of references to valid blocks.
system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu2.dcache.demand_accesses             103491                       # number of demand (read+write) accesses
system.cpu2.dcache.demand_avg_miss_latency 22409.863946                       # average overall miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency 15024.621212                       # average overall mshr miss latency
system.cpu2.dcache.demand_hits                 102903                       # number of demand (read+write) hits
system.cpu2.dcache.demand_miss_latency       13177000                       # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_rate          0.005682                       # miss rate for demand accesses
system.cpu2.dcache.demand_misses                  588                       # number of demand (read+write) misses
system.cpu2.dcache.demand_mshr_hits               324                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_miss_latency      3966500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_rate     0.002551                       # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_misses             264                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu2.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.dcache.occ_%::0                  0.052851                       # Average percentage of cache occupancy
system.cpu2.dcache.occ_%::1                 -0.017878                       # Average percentage of cache occupancy
system.cpu2.dcache.occ_blocks::0            27.059534                       # Average occupied blocks per context
system.cpu2.dcache.occ_blocks::1            -9.153554                       # Average occupied blocks per context
system.cpu2.dcache.overall_accesses            103491                       # number of overall (read+write) accesses
system.cpu2.dcache.overall_avg_miss_latency 22409.863946                       # average overall miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency 15024.621212                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu2.dcache.overall_hits                102903                       # number of overall hits
system.cpu2.dcache.overall_miss_latency      13177000                       # number of overall miss cycles
system.cpu2.dcache.overall_miss_rate         0.005682                       # miss rate for overall accesses
system.cpu2.dcache.overall_misses                 588                       # number of overall misses
system.cpu2.dcache.overall_mshr_hits              324                       # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_miss_latency      3966500                       # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_rate     0.002551                       # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_misses            264                       # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu2.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu2.dcache.replacements                     2                       # number of replacements
system.cpu2.dcache.sampled_refs                    30                       # Sample count of references to valid blocks.
system.cpu2.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu2.dcache.tagsinuse                17.905980                       # Cycle average of tags in use
system.cpu2.dcache.total_refs                   53382                       # Total number of references to valid blocks.
system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.dcache.writebacks                       1                       # number of writebacks
system.cpu2.decode.DECODE:BlockedCycles         19187                       # Number of cycles decode is blocked
system.cpu2.decode.DECODE:DecodedInsts         342711                       # Number of instructions handled by decode
system.cpu2.decode.DECODE:IdleCycles            46061                       # Number of cycles decode is idle
system.cpu2.decode.DECODE:RunCycles            116769                       # Number of cycles decode is running
system.cpu2.decode.DECODE:SquashCycles           1740                       # Number of cycles decode is squashing
system.cpu2.decode.DECODE:UnblockCycles          3898                       # Number of cycles decode is unblocking
system.cpu2.fetch.Branches                      60491                       # Number of branches that fetch encountered
system.cpu2.fetch.CacheLines                    17027                       # Number of cache lines fetched
system.cpu2.fetch.Cycles                       121028                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.IcacheSquashes                  224                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.Insts                        343825                       # Number of instructions fetch has processed
system.cpu2.fetch.MiscStallCycles                  31                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.SquashCycles                   1162                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.branchRate                 0.303000                       # Number of branch fetches per cycle
system.cpu2.fetch.icacheStallCycles             17027                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.predictedBranches             58194                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.rate                       1.722225                       # Number of inst fetches per cycle
system.cpu2.fetch.rateDist::samples            194280                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.769740                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.108066                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                   73252     37.70%     37.70% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                   61385     31.60%     69.30% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                    5275      2.72%     72.02% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                    2733      1.41%     73.42% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                    1902      0.98%     74.40% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                   45539     23.44%     97.84% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                    2450      1.26%     99.10% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                     264      0.14%     99.24% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                    1480      0.76%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total              194280                       # Number of instructions fetched each cycle (Total)
system.cpu2.icache.ReadReq_accesses             17027                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_avg_miss_latency 21608.921162                       # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18272.935780                       # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_hits                 16545                       # number of ReadReq hits
system.cpu2.icache.ReadReq_miss_latency      10415500                       # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_rate         0.028308                       # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_misses                 482                       # number of ReadReq misses
system.cpu2.icache.ReadReq_mshr_hits               46                       # number of ReadReq MSHR hits
system.cpu2.icache.ReadReq_mshr_miss_latency      7967000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate     0.025606                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_misses            436                       # number of ReadReq MSHR misses
system.cpu2.icache.avg_blocked_cycles::no_mshrs        18250                       # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu2.icache.avg_refs                 37.947248                       # Average number of references to valid blocks.
system.cpu2.icache.blocked::no_mshrs                2                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_mshrs        36500                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
system.cpu2.icache.demand_accesses              17027                       # number of demand (read+write) accesses
system.cpu2.icache.demand_avg_miss_latency 21608.921162                       # average overall miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency 18272.935780                       # average overall mshr miss latency
system.cpu2.icache.demand_hits                  16545                       # number of demand (read+write) hits
system.cpu2.icache.demand_miss_latency       10415500                       # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_rate          0.028308                       # miss rate for demand accesses
system.cpu2.icache.demand_misses                  482                       # number of demand (read+write) misses
system.cpu2.icache.demand_mshr_hits                46                       # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_miss_latency      7967000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_rate     0.025606                       # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_misses             436                       # number of demand (read+write) MSHR misses
system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
system.cpu2.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.icache.occ_%::0                  0.176617                       # Average percentage of cache occupancy
system.cpu2.icache.occ_blocks::0            90.427890                       # Average occupied blocks per context
system.cpu2.icache.overall_accesses             17027                       # number of overall (read+write) accesses
system.cpu2.icache.overall_avg_miss_latency 21608.921162                       # average overall miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency 18272.935780                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu2.icache.overall_hits                 16545                       # number of overall hits
system.cpu2.icache.overall_miss_latency      10415500                       # number of overall miss cycles
system.cpu2.icache.overall_miss_rate         0.028308                       # miss rate for overall accesses
system.cpu2.icache.overall_misses                 482                       # number of overall misses
system.cpu2.icache.overall_mshr_hits               46                       # number of overall MSHR hits
system.cpu2.icache.overall_mshr_miss_latency      7967000                       # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_rate     0.025606                       # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_misses            436                       # number of overall MSHR misses
system.cpu2.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu2.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu2.icache.replacements                   326                       # number of replacements
system.cpu2.icache.sampled_refs                   436                       # Sample count of references to valid blocks.
system.cpu2.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu2.icache.tagsinuse                90.427890                       # Cycle average of tags in use
system.cpu2.icache.total_refs                   16545                       # Total number of references to valid blocks.
system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.icache.writebacks                       0                       # number of writebacks
system.cpu2.idleCycles                           5360                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.iew.EXEC:branches                   58330                       # Number of branches executed
system.cpu2.iew.EXEC:nop                        49308                       # number of nop insts executed
system.cpu2.iew.EXEC:rate                    1.432328                       # Inst execution rate
system.cpu2.iew.EXEC:refs                      147694                       # number of memory reference insts executed
system.cpu2.iew.EXEC:stores                     47984                       # Number of stores executed
system.cpu2.iew.EXEC:swp                            0                       # number of swp insts executed
system.cpu2.iew.WB:consumers                   167735                       # num instructions consuming a value
system.cpu2.iew.WB:count                       285574                       # cumulative count of insts written-back
system.cpu2.iew.WB:fanout                    0.978186                       # average fanout of values written-back
system.cpu2.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.iew.WB:producers                   164076                       # num instructions producing a value
system.cpu2.iew.WB:rate                      1.430445                       # insts written-back per cycle
system.cpu2.iew.WB:sent                        285706                       # cumulative count of insts sent to commit
system.cpu2.iew.branchMispredicts                1190                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewBlockCycles                   1666                       # Number of cycles IEW is blocking
system.cpu2.iew.iewDispLoadInsts               100435                       # Number of dispatched load instructions
system.cpu2.iew.iewDispNonSpecInsts               918                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewDispSquashedInsts              521                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispStoreInsts               48400                       # Number of dispatched store instructions
system.cpu2.iew.iewDispatchedInsts             338900                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewExecLoadInsts                99710                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts              966                       # Number of squashed instructions skipped in execute
system.cpu2.iew.iewExecutedInsts               285950                       # Number of executed instructions
system.cpu2.iew.iewIQFullEvents                    50                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.iewSquashCycles                  1740                       # Number of cycles IEW is squashing
system.cpu2.iew.iewUnblockCycles                   60                       # Number of cycles IEW is unblocking
system.cpu2.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread.0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.lsq.thread.0.forwLoads          43769                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread.0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread.0.memOrderViolation           35                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread.0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread.0.squashedLoads         1490                       # Number of loads squashed
system.cpu2.iew.lsq.thread.0.squashedStores          766                       # Number of stores squashed
system.cpu2.iew.memOrderViolationEvents            35                       # Number of memory order violations
system.cpu2.iew.predictedNotTakenIncorrect          199                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.predictedTakenIncorrect           991                       # Number of branches that were predicted taken incorrectly
system.cpu2.ipc                              1.392607                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        1.392607                       # IPC: Total IPC of All Threads
system.cpu2.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::IntAlu         134825     46.99%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::IntMult             0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatAdd            0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatDiv            0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdAdd             0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdAlu             0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdCmp             0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdCvt             0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdMisc            0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdMult            0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdSqrt            0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     46.99% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::MemRead        104076     36.27%     83.27% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::MemWrite        48015     16.73%    100.00% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::total          286916                       # Type of FU issued
system.cpu2.iq.ISSUE:fu_busy_cnt                  198                       # FU busy when requested
system.cpu2.iq.ISSUE:fu_busy_rate            0.000690                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::IntAlu               12      6.06%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::IntMult               0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::IntDiv                0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatAdd              0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatCmp              0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatCvt              0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatMult             0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatDiv              0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatSqrt             0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdAdd               0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdAddAcc            0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdAlu               0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdCmp               0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdCvt               0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdMisc              0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdMult              0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdShift             0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdSqrt              0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      6.06% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::MemRead              55     27.78%     33.84% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::MemWrite            131     66.16%    100.00% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.ISSUE:issued_per_cycle::samples       194280                       # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::mean     1.476817                       # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::stdev     1.291045                       # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::0        69262     35.65%     35.65% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::1        22249     11.45%     47.10% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::2        50270     25.88%     72.98% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::3        48052     24.73%     97.71% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::4         2627      1.35%     99.06% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::5         1560      0.80%     99.87% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::6          166      0.09%     99.95% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::7           85      0.04%    100.00% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::8            9      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::total       194280                       # Number of insts issued each cycle
system.cpu2.iq.ISSUE:rate                    1.437167                       # Inst issue rate
system.cpu2.iq.iqInstsAdded                    284164                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqInstsIssued                   286916                       # Number of instructions issued
system.cpu2.iq.iqNonSpecInstsAdded               5428                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqSquashedInstsExamined           6474                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedInstsIssued                1                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedNonSpecRemoved           533                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.iqSquashedOperandsExamined         6110                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.memDep0.conflictingLoads            48437                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores           43927                       # Number of conflicting stores.
system.cpu2.memDep0.insertedLoads              100435                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores              48400                       # Number of stores inserted to the mem dependence unit.
system.cpu2.numCycles                          199640                       # number of cpu cycles simulated
system.cpu2.rename.RENAME:BlockCycles            5634                       # Number of cycles rename is blocking
system.cpu2.rename.RENAME:CommittedMaps        228819                       # Number of HB maps that are committed
system.cpu2.rename.RENAME:IQFullEvents             67                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.RENAME:IdleCycles            46667                       # Number of cycles rename is idle
system.cpu2.rename.RENAME:LSQFullEvents            60                       # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RENAME:RenameLookups        661216                       # Number of register rename lookups that rename has made
system.cpu2.rename.RENAME:RenamedInsts         341037                       # Number of instructions processed by rename
system.cpu2.rename.RENAME:RenamedOperands       237006                       # Number of destination operands rename has renamed
system.cpu2.rename.RENAME:RunCycles            120203                       # Number of cycles rename is running
system.cpu2.rename.RENAME:SquashCycles           1740                       # Number of cycles rename is squashing
system.cpu2.rename.RENAME:UnblockCycles           620                       # Number of cycles rename is unblocking
system.cpu2.rename.RENAME:UndoneMaps             8187                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.RENAME:serializeStallCycles        12791                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RENAME:serializingInsts          940                       # count of serializing insts renamed
system.cpu2.rename.RENAME:skidInsts              2775                       # count of insts added to the skid buffer
system.cpu2.rename.RENAME:tempSerializingInsts          995                       # count of temporary serializing insts renamed
system.cpu2.timesIdled                            296                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.BPredUnit.BTBHits                   53101                       # Number of BTB hits
system.cpu3.BPredUnit.BTBLookups                55313                       # Number of BTB lookups
system.cpu3.BPredUnit.RASInCorrect                  0                       # Number of incorrect RAS predictions.
system.cpu3.BPredUnit.condIncorrect              1094                       # Number of conditional branches incorrect
system.cpu3.BPredUnit.condPredicted             55399                       # Number of conditional branches predicted
system.cpu3.BPredUnit.lookups                   55399                       # Number of BP lookups
system.cpu3.BPredUnit.usedRAS                       0                       # Number of times the RAS was used to get a target.
system.cpu3.commit.COM:branches                 52563                       # Number of branches committed
system.cpu3.commit.COM:bw_lim_events              486                       # number cycles where commit BW limit reached
system.cpu3.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
system.cpu3.commit.COM:committed_per_cycle::samples       187872                       # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::mean     1.575583                       # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::stdev     1.953160                       # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::0        78438     41.75%     41.75% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::1        53385     28.42%     70.17% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::2         7469      3.98%     74.14% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::3         7434      3.96%     78.10% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::4         2454      1.31%     79.41% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::5        37686     20.06%     99.46% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::6          391      0.21%     99.67% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::7          129      0.07%     99.74% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::8          486      0.26%    100.00% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::total       187872                       # Number of insts commited each cycle
system.cpu3.commit.COM:count                   296008                       # Number of instructions committed
system.cpu3.commit.COM:loads                    86777                       # Number of loads committed
system.cpu3.commit.COM:membars                   5899                       # Number of memory barriers committed
system.cpu3.commit.COM:refs                    127476                       # Number of memory references committed
system.cpu3.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
system.cpu3.commit.branchMispredicts             1094                       # The number of times a branch was mispredicted
system.cpu3.commit.commitCommittedInsts        296008                       # The number of committed instructions
system.cpu3.commit.commitNonSpecStalls           6615                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.commitSquashedInsts           8397                       # The number of squashed insts skipped by commit
system.cpu3.committedInsts                     246758                       # Number of Instructions Simulated
system.cpu3.committedInsts_total               246758                       # Number of Instructions Simulated
system.cpu3.cpi                              0.807958                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        0.807958                       # CPI: Total CPI of All Threads
system.cpu3.dcache.ReadReq_accesses             50677                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_avg_miss_latency 21660.356347                       # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency        13875                       # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_hits                 50228                       # number of ReadReq hits
system.cpu3.dcache.ReadReq_miss_latency       9725500                       # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_rate         0.008860                       # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_misses                 449                       # number of ReadReq misses
system.cpu3.dcache.ReadReq_mshr_hits              289                       # number of ReadReq MSHR hits
system.cpu3.dcache.ReadReq_mshr_miss_latency      2220000                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate     0.003157                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_misses            160                       # number of ReadReq MSHR misses
system.cpu3.dcache.SwapReq_accesses                70                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_avg_miss_latency 26068.965517                       # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 23068.965517                       # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_hits                    12                       # number of SwapReq hits
system.cpu3.dcache.SwapReq_miss_latency       1512000                       # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_rate         0.828571                       # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_misses                  58                       # number of SwapReq misses
system.cpu3.dcache.SwapReq_mshr_miss_latency      1338000                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_rate     0.828571                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_misses             58                       # number of SwapReq MSHR misses
system.cpu3.dcache.WriteReq_accesses            40629                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_avg_miss_latency 23540.650407                       # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 15301.886792                       # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_hits                40506                       # number of WriteReq hits
system.cpu3.dcache.WriteReq_miss_latency      2895500                       # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_rate        0.003027                       # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_misses                123                       # number of WriteReq misses
system.cpu3.dcache.WriteReq_mshr_hits              17                       # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_miss_latency      1622000                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_rate     0.002609                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_misses           106                       # number of WriteReq MSHR misses
system.cpu3.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_refs               1601.034483                       # Average number of references to valid blocks.
system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu3.dcache.demand_accesses              91306                       # number of demand (read+write) accesses
system.cpu3.dcache.demand_avg_miss_latency 22064.685315                       # average overall miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency 14443.609023                       # average overall mshr miss latency
system.cpu3.dcache.demand_hits                  90734                       # number of demand (read+write) hits
system.cpu3.dcache.demand_miss_latency       12621000                       # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_rate          0.006265                       # miss rate for demand accesses
system.cpu3.dcache.demand_misses                  572                       # number of demand (read+write) misses
system.cpu3.dcache.demand_mshr_hits               306                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_miss_latency      3842000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_rate     0.002913                       # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_misses             266                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu3.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.dcache.occ_%::0                  0.048988                       # Average percentage of cache occupancy
system.cpu3.dcache.occ_%::1                 -0.020365                       # Average percentage of cache occupancy
system.cpu3.dcache.occ_blocks::0            25.081960                       # Average occupied blocks per context
system.cpu3.dcache.occ_blocks::1           -10.426668                       # Average occupied blocks per context
system.cpu3.dcache.overall_accesses             91306                       # number of overall (read+write) accesses
system.cpu3.dcache.overall_avg_miss_latency 22064.685315                       # average overall miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency 14443.609023                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu3.dcache.overall_hits                 90734                       # number of overall hits
system.cpu3.dcache.overall_miss_latency      12621000                       # number of overall miss cycles
system.cpu3.dcache.overall_miss_rate         0.006265                       # miss rate for overall accesses
system.cpu3.dcache.overall_misses                 572                       # number of overall misses
system.cpu3.dcache.overall_mshr_hits              306                       # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_miss_latency      3842000                       # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_rate     0.002913                       # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_misses            266                       # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu3.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu3.dcache.replacements                     2                       # number of replacements
system.cpu3.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
system.cpu3.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu3.dcache.tagsinuse                14.655292                       # Cycle average of tags in use
system.cpu3.dcache.total_refs                   46430                       # Total number of references to valid blocks.
system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.dcache.writebacks                       1                       # number of writebacks
system.cpu3.decode.DECODE:BlockedCycles         21089                       # Number of cycles decode is blocked
system.cpu3.decode.DECODE:DecodedInsts         308413                       # Number of instructions handled by decode
system.cpu3.decode.DECODE:IdleCycles            54614                       # Number of cycles decode is idle
system.cpu3.decode.DECODE:RunCycles            106676                       # Number of cycles decode is running
system.cpu3.decode.DECODE:SquashCycles           1792                       # Number of cycles decode is squashing
system.cpu3.decode.DECODE:UnblockCycles          5492                       # Number of cycles decode is unblocking
system.cpu3.fetch.Branches                      55399                       # Number of branches that fetch encountered
system.cpu3.fetch.CacheLines                    20572                       # Number of cache lines fetched
system.cpu3.fetch.Cycles                       112541                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.IcacheSquashes                  221                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.Insts                        309543                       # Number of instructions fetch has processed
system.cpu3.fetch.MiscStallCycles                  25                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.SquashCycles                   1170                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.branchRate                 0.277870                       # Number of branch fetches per cycle
system.cpu3.fetch.icacheStallCycles             20572                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.predictedBranches             53101                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.rate                       1.552606                       # Number of inst fetches per cycle
system.cpu3.fetch.rateDist::samples            196296                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.576920                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            2.037630                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0                   83755     42.67%     42.67% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                   58002     29.55%     72.22% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                    7019      3.58%     75.79% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                    2809      1.43%     77.22% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                    1911      0.97%     78.20% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                   38598     19.66%     97.86% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                    2463      1.25%     99.11% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                     248      0.13%     99.24% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                    1491      0.76%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total              196296                       # Number of instructions fetched each cycle (Total)
system.cpu3.icache.ReadReq_accesses             20572                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_avg_miss_latency 14541.928721                       # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11822.799097                       # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_hits                 20095                       # number of ReadReq hits
system.cpu3.icache.ReadReq_miss_latency       6936500                       # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_rate         0.023187                       # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_misses                 477                       # number of ReadReq misses
system.cpu3.icache.ReadReq_mshr_hits               34                       # number of ReadReq MSHR hits
system.cpu3.icache.ReadReq_mshr_miss_latency      5237500                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate     0.021534                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_misses            443                       # number of ReadReq MSHR misses
system.cpu3.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu3.icache.avg_refs                 45.361174                       # Average number of references to valid blocks.
system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
system.cpu3.icache.demand_accesses              20572                       # number of demand (read+write) accesses
system.cpu3.icache.demand_avg_miss_latency 14541.928721                       # average overall miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency 11822.799097                       # average overall mshr miss latency
system.cpu3.icache.demand_hits                  20095                       # number of demand (read+write) hits
system.cpu3.icache.demand_miss_latency        6936500                       # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_rate          0.023187                       # miss rate for demand accesses
system.cpu3.icache.demand_misses                  477                       # number of demand (read+write) misses
system.cpu3.icache.demand_mshr_hits                34                       # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_miss_latency      5237500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_rate     0.021534                       # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_misses             443                       # number of demand (read+write) MSHR misses
system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
system.cpu3.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.icache.occ_%::0                  0.172973                       # Average percentage of cache occupancy
system.cpu3.icache.occ_blocks::0            88.562021                       # Average occupied blocks per context
system.cpu3.icache.overall_accesses             20572                       # number of overall (read+write) accesses
system.cpu3.icache.overall_avg_miss_latency 14541.928721                       # average overall miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency 11822.799097                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu3.icache.overall_hits                 20095                       # number of overall hits
system.cpu3.icache.overall_miss_latency       6936500                       # number of overall miss cycles
system.cpu3.icache.overall_miss_rate         0.023187                       # miss rate for overall accesses
system.cpu3.icache.overall_misses                 477                       # number of overall misses
system.cpu3.icache.overall_mshr_hits               34                       # number of overall MSHR hits
system.cpu3.icache.overall_mshr_miss_latency      5237500                       # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_rate     0.021534                       # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_misses            443                       # number of overall MSHR misses
system.cpu3.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu3.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu3.icache.replacements                   331                       # number of replacements
system.cpu3.icache.sampled_refs                   443                       # Sample count of references to valid blocks.
system.cpu3.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu3.icache.tagsinuse                88.562021                       # Cycle average of tags in use
system.cpu3.icache.total_refs                   20095                       # Total number of references to valid blocks.
system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.icache.writebacks                       0                       # number of writebacks
system.cpu3.idleCycles                           3074                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.iew.EXEC:branches                   53119                       # Number of branches executed
system.cpu3.iew.EXEC:nop                        44175                       # number of nop insts executed
system.cpu3.iew.EXEC:rate                    1.285981                       # Inst execution rate
system.cpu3.iew.EXEC:refs                      128575                       # number of memory reference insts executed
system.cpu3.iew.EXEC:stores                     41051                       # Number of stores executed
system.cpu3.iew.EXEC:swp                            0                       # number of swp insts executed
system.cpu3.iew.WB:consumers                   148618                       # num instructions consuming a value
system.cpu3.iew.WB:count                       256019                       # cumulative count of insts written-back
system.cpu3.iew.WB:fanout                    0.975407                       # average fanout of values written-back
system.cpu3.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu3.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.iew.WB:producers                   144963                       # num instructions producing a value
system.cpu3.iew.WB:rate                      1.284140                       # insts written-back per cycle
system.cpu3.iew.WB:sent                        256153                       # cumulative count of insts sent to commit
system.cpu3.iew.branchMispredicts                1196                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewBlockCycles                   1671                       # Number of cycles IEW is blocking
system.cpu3.iew.iewDispLoadInsts                88323                       # Number of dispatched load instructions
system.cpu3.iew.iewDispNonSpecInsts               935                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewDispSquashedInsts              564                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispStoreInsts               41481                       # Number of dispatched store instructions
system.cpu3.iew.iewDispatchedInsts             304435                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewExecLoadInsts                87524                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts              961                       # Number of squashed instructions skipped in execute
system.cpu3.iew.iewExecutedInsts               256386                       # Number of executed instructions
system.cpu3.iew.iewIQFullEvents                    55                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.iewSquashCycles                  1792                       # Number of cycles IEW is squashing
system.cpu3.iew.iewUnblockCycles                   64                       # Number of cycles IEW is unblocking
system.cpu3.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread.0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.lsq.thread.0.forwLoads          36829                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread.0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread.0.memOrderViolation           34                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread.0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread.0.squashedLoads         1546                       # Number of loads squashed
system.cpu3.iew.lsq.thread.0.squashedStores          782                       # Number of stores squashed
system.cpu3.iew.memOrderViolationEvents            34                       # Number of memory order violations
system.cpu3.iew.predictedNotTakenIncorrect          194                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.predictedTakenIncorrect          1002                       # Number of branches that were predicted taken incorrectly
system.cpu3.ipc                              1.237689                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        1.237689                       # IPC: Total IPC of All Threads
system.cpu3.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::IntAlu         122656     47.66%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::IntMult             0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatAdd            0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatDiv            0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdAdd             0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdAlu             0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdCmp             0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdCvt             0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdMisc            0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdMult            0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdSqrt            0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     47.66% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::MemRead         93608     36.37%     84.04% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::MemWrite        41083     15.96%    100.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::total          257347                       # Type of FU issued
system.cpu3.iq.ISSUE:fu_busy_cnt                  199                       # FU busy when requested
system.cpu3.iq.ISSUE:fu_busy_rate            0.000773                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::IntAlu               11      5.53%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::IntMult               0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::IntDiv                0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatAdd              0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatCmp              0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatCvt              0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatMult             0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatDiv              0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatSqrt             0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdAdd               0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdAddAcc            0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdAlu               0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdCmp               0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdCvt               0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdMisc              0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdMult              0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdShift             0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdSqrt              0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      5.53% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::MemRead              57     28.64%     34.17% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::MemWrite            131     65.83%    100.00% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.ISSUE:issued_per_cycle::samples       196296                       # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::mean     1.311015                       # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::stdev     1.285531                       # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::0        79991     40.75%     40.75% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::1        27327     13.92%     54.67% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::2        43412     22.12%     76.79% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::3        41220     21.00%     97.79% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::4         2543      1.30%     99.08% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::5         1556      0.79%     99.87% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::6          155      0.08%     99.95% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::7           82      0.04%     99.99% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::8           10      0.01%    100.00% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::total       196296                       # Number of insts issued each cycle
system.cpu3.iq.ISSUE:rate                    1.290801                       # Inst issue rate
system.cpu3.iq.iqInstsAdded                    253019                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqInstsIssued                   257347                       # Number of instructions issued
system.cpu3.iq.iqNonSpecInstsAdded               7241                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqSquashedInstsExamined           6661                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedInstsIssued                2                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedNonSpecRemoved           626                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.iqSquashedOperandsExamined         6379                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.memDep0.conflictingLoads            43278                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores           36990                       # Number of conflicting stores.
system.cpu3.memDep0.insertedLoads               88323                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores              41481                       # Number of stores inserted to the mem dependence unit.
system.cpu3.numCycles                          199370                       # number of cpu cycles simulated
system.cpu3.rename.RENAME:BlockCycles            7226                       # Number of cycles rename is blocking
system.cpu3.rename.RENAME:CommittedMaps        202775                       # Number of HB maps that are committed
system.cpu3.rename.RENAME:IQFullEvents             58                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.RENAME:IdleCycles            55235                       # Number of cycles rename is idle
system.cpu3.rename.RENAME:LSQFullEvents            44                       # Number of times rename has blocked due to LSQ full
system.cpu3.rename.RENAME:RenameLookups        585183                       # Number of register rename lookups that rename has made
system.cpu3.rename.RENAME:RenamedInsts         306652                       # Number of instructions processed by rename
system.cpu3.rename.RENAME:RenamedOperands       211061                       # Number of destination operands rename has renamed
system.cpu3.rename.RENAME:RunCycles            111693                       # Number of cycles rename is running
system.cpu3.rename.RENAME:SquashCycles           1792                       # Number of cycles rename is squashing
system.cpu3.rename.RENAME:UnblockCycles           593                       # Number of cycles rename is unblocking
system.cpu3.rename.RENAME:UndoneMaps             8286                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.RENAME:serializeStallCycles        13124                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RENAME:serializingInsts          957                       # count of serializing insts renamed
system.cpu3.rename.RENAME:skidInsts              2808                       # count of insts added to the skid buffer
system.cpu3.rename.RENAME:tempSerializingInsts         1009                       # count of temporary serializing insts renamed
system.cpu3.timesIdled                            290                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.l2c.ReadExReq_accesses::0                   94                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1                   12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::2                   13                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::3                   12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_avg_miss_latency::0 73159.574468                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 573083.333333                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::2       529000                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::3 573083.333333                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 1748326.241135                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40290.076336                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_miss_latency             6877000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate::0                   1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::1                   1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::2                   1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::3                   1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total               4                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses::0                     94                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::1                     12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::2                     13                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::3                     12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
system.l2c.ReadExReq_mshr_miss_latency        5278000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate::0       1.393617                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1      10.916667                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::2      10.076923                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::3      10.916667                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total    33.303873                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_misses                  131                       # number of ReadExReq MSHR misses
system.l2c.ReadReq_accesses::0                    689                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1                    457                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::2                    450                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::3                    456                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total               2052                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_avg_miss_latency::0   63653.674833                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1   2381708.333333                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::2   348542.682927                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::3   4082928.571429                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 6876833.262522                       # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency 40001.841621                       # average ReadReq mshr miss latency
system.l2c.ReadReq_hits::0                        240                       # number of ReadReq hits
system.l2c.ReadReq_hits::1                        445                       # number of ReadReq hits
system.l2c.ReadReq_hits::2                        368                       # number of ReadReq hits
system.l2c.ReadReq_hits::3                        449                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                   1502                       # number of ReadReq hits
system.l2c.ReadReq_miss_latency              28580500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate::0              0.651669                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1              0.026258                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::2              0.182222                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::3              0.015351                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.875500                       # miss rate for ReadReq accesses
system.l2c.ReadReq_misses::0                      449                       # number of ReadReq misses
system.l2c.ReadReq_misses::1                       12                       # number of ReadReq misses
system.l2c.ReadReq_misses::2                       82                       # number of ReadReq misses
system.l2c.ReadReq_misses::3                        7                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  550                       # number of ReadReq misses
system.l2c.ReadReq_mshr_hits                        7                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_miss_latency         21721000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::0         0.788099                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1         1.188184                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::2         1.206667                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::3         1.190789                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     4.373739                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses                    543                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_accesses::0                  29                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::1                  21                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::2                  23                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::3                  24                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              97                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_avg_miss_latency::0         6000                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1  7428.571429                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::2  6782.608696                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::3         6500                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 26711.180124                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_hits::0                       3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_miss_latency             156000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_rate::0           0.896552                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::1                  1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::2                  1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::3                  1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       3.896552                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses::0                    26                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::1                    21                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::2                    23                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::3                    24                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                94                       # number of UpgradeReq misses
system.l2c.UpgradeReq_mshr_miss_latency       3760000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate::0      3.241379                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1      4.476190                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::2      4.086957                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::3      3.916667                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total    15.721193                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_misses                  94                       # number of UpgradeReq MSHR misses
system.l2c.Writeback_accesses::0                    9                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total                9                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0                        9                       # number of Writeback hits
system.l2c.Writeback_hits::total                    9                       # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.avg_refs                          2.750459                       # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.demand_accesses::0                     783                       # number of demand (read+write) accesses
system.l2c.demand_accesses::1                     469                       # number of demand (read+write) accesses
system.l2c.demand_accesses::2                     463                       # number of demand (read+write) accesses
system.l2c.demand_accesses::3                     468                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total                2183                       # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency::0    65299.263352                       # average overall miss latency
system.l2c.demand_avg_miss_latency::1    1477395.833333                       # average overall miss latency
system.l2c.demand_avg_miss_latency::2    373236.842105                       # average overall miss latency
system.l2c.demand_avg_miss_latency::3    1866184.210526                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 3782116.149317                       # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency  40057.863501                       # average overall mshr miss latency
system.l2c.demand_hits::0                         240                       # number of demand (read+write) hits
system.l2c.demand_hits::1                         445                       # number of demand (read+write) hits
system.l2c.demand_hits::2                         368                       # number of demand (read+write) hits
system.l2c.demand_hits::3                         449                       # number of demand (read+write) hits
system.l2c.demand_hits::total                    1502                       # number of demand (read+write) hits
system.l2c.demand_miss_latency               35457500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate::0               0.693487                       # miss rate for demand accesses
system.l2c.demand_miss_rate::1               0.051173                       # miss rate for demand accesses
system.l2c.demand_miss_rate::2               0.205184                       # miss rate for demand accesses
system.l2c.demand_miss_rate::3               0.040598                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.990441                       # miss rate for demand accesses
system.l2c.demand_misses::0                       543                       # number of demand (read+write) misses
system.l2c.demand_misses::1                        24                       # number of demand (read+write) misses
system.l2c.demand_misses::2                        95                       # number of demand (read+write) misses
system.l2c.demand_misses::3                        19                       # number of demand (read+write) misses
system.l2c.demand_misses::total                   681                       # number of demand (read+write) misses
system.l2c.demand_mshr_hits                         7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency          26999000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0          0.860792                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1          1.437100                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::2          1.455724                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::3          1.440171                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      5.193787                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses                     674                       # number of demand (read+write) MSHR misses
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.l2c.occ_%::0                          0.005561                       # Average percentage of cache occupancy
system.l2c.occ_%::1                          0.000141                       # Average percentage of cache occupancy
system.l2c.occ_%::2                          0.000959                       # Average percentage of cache occupancy
system.l2c.occ_%::3                          0.000053                       # Average percentage of cache occupancy
system.l2c.occ_%::4                          0.000079                       # Average percentage of cache occupancy
system.l2c.occ_blocks::0                   364.466495                       # Average occupied blocks per context
system.l2c.occ_blocks::1                     9.271638                       # Average occupied blocks per context
system.l2c.occ_blocks::2                    62.868915                       # Average occupied blocks per context
system.l2c.occ_blocks::3                     3.440920                       # Average occupied blocks per context
system.l2c.occ_blocks::4                     5.201108                       # Average occupied blocks per context
system.l2c.overall_accesses::0                    783                       # number of overall (read+write) accesses
system.l2c.overall_accesses::1                    469                       # number of overall (read+write) accesses
system.l2c.overall_accesses::2                    463                       # number of overall (read+write) accesses
system.l2c.overall_accesses::3                    468                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total               2183                       # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency::0   65299.263352                       # average overall miss latency
system.l2c.overall_avg_miss_latency::1   1477395.833333                       # average overall miss latency
system.l2c.overall_avg_miss_latency::2   373236.842105                       # average overall miss latency
system.l2c.overall_avg_miss_latency::3   1866184.210526                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 3782116.149317                       # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 40057.863501                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.l2c.overall_hits::0                        240                       # number of overall hits
system.l2c.overall_hits::1                        445                       # number of overall hits
system.l2c.overall_hits::2                        368                       # number of overall hits
system.l2c.overall_hits::3                        449                       # number of overall hits
system.l2c.overall_hits::total                   1502                       # number of overall hits
system.l2c.overall_miss_latency              35457500                       # number of overall miss cycles
system.l2c.overall_miss_rate::0              0.693487                       # miss rate for overall accesses
system.l2c.overall_miss_rate::1              0.051173                       # miss rate for overall accesses
system.l2c.overall_miss_rate::2              0.205184                       # miss rate for overall accesses
system.l2c.overall_miss_rate::3              0.040598                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.990441                       # miss rate for overall accesses
system.l2c.overall_misses::0                      543                       # number of overall misses
system.l2c.overall_misses::1                       24                       # number of overall misses
system.l2c.overall_misses::2                       95                       # number of overall misses
system.l2c.overall_misses::3                       19                       # number of overall misses
system.l2c.overall_misses::total                  681                       # number of overall misses
system.l2c.overall_mshr_hits                        7                       # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency         26999000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0         0.860792                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1         1.437100                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::2         1.455724                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::3         1.440171                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     5.193787                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses                    674                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.replacements                             0                       # number of replacements
system.l2c.sampled_refs                           545                       # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse                       445.249076                       # Cycle average of tags in use
system.l2c.total_refs                            1499                       # Total number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.writebacks                               0                       # number of writebacks

---------- End Simulation Statistics   ----------