2009-04-21 17:37:50 +02:00
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---------- Begin Simulation Statistics ----------
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2011-01-16 00:30:34 +01:00
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sim_seconds 0.000117 # Number of seconds simulated
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2011-06-11 04:15:34 +02:00
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sim_ticks 117354500 # Number of ticks simulated
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 90067 # Simulator instruction rate (inst/s)
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host_tick_rate 9199514 # Simulator tick rate (ticks/s)
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host_mem_usage 171836 # Number of bytes of host memory used
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host_seconds 12.76 # Real time elapsed on the host
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sim_insts 1148940 # Number of instructions simulated
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system.cpu0.workload.num_syscalls 89 # Number of system calls
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system.cpu0.numCycles 234710 # number of cpu cycles simulated
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu0.BPredUnit.lookups 91844 # Number of BP lookups
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system.cpu0.BPredUnit.condPredicted 90062 # Number of conditional branches predicted
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system.cpu0.BPredUnit.condIncorrect 1094 # Number of conditional branches incorrect
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system.cpu0.BPredUnit.BTBLookups 91032 # Number of BTB lookups
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system.cpu0.BPredUnit.BTBHits 88645 # Number of BTB hits
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2009-04-21 17:37:50 +02:00
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system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-06-11 04:15:34 +02:00
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system.cpu0.BPredUnit.usedRAS 397 # Number of times the RAS was used to get a target.
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system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions.
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system.cpu0.fetch.icacheStallCycles 5189 # Number of cycles fetch is stalled on an Icache miss
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system.cpu0.fetch.Insts 547166 # Number of instructions fetch has processed
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system.cpu0.fetch.Branches 91844 # Number of branches that fetch encountered
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system.cpu0.fetch.predictedBranches 89042 # Number of branches that fetch has predicted taken
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system.cpu0.fetch.Cycles 180871 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu0.fetch.SquashCycles 1241 # Number of cycles fetch has spent squashing
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system.cpu0.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu0.fetch.CacheLines 5189 # Number of cache lines fetched
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system.cpu0.fetch.IcacheSquashes 438 # Number of outstanding Icache misses that were squashed
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system.cpu0.fetch.rateDist::samples 216259 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::mean 2.530142 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::stdev 2.183723 # Number of instructions fetched each cycle (Total)
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2009-07-07 00:49:48 +02:00
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system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-06-11 04:15:34 +02:00
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system.cpu0.fetch.rateDist::0 35388 16.36% 16.36% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::1 90011 41.62% 57.99% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::2 494 0.23% 58.21% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::3 785 0.36% 58.58% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::4 592 0.27% 58.85% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::5 86207 39.86% 98.71% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::6 812 0.38% 99.09% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::7 223 0.10% 99.19% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::8 1747 0.81% 100.00% # Number of instructions fetched each cycle (Total)
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2009-07-07 00:49:48 +02:00
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system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-06-11 04:15:34 +02:00
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system.cpu0.fetch.rateDist::total 216259 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.branchRate 0.391308 # Number of branch fetches per cycle
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system.cpu0.fetch.rate 2.331243 # Number of inst fetches per cycle
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system.cpu0.decode.IdleCycles 20008 # Number of cycles decode is idle
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system.cpu0.decode.BlockedCycles 13629 # Number of cycles decode is blocked
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system.cpu0.decode.RunCycles 180385 # Number of cycles decode is running
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system.cpu0.decode.UnblockCycles 202 # Number of cycles decode is unblocking
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system.cpu0.decode.SquashCycles 2035 # Number of cycles decode is squashing
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system.cpu0.decode.DecodedInsts 546099 # Number of instructions handled by decode
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system.cpu0.rename.SquashCycles 2035 # Number of cycles rename is squashing
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system.cpu0.rename.IdleCycles 20667 # Number of cycles rename is idle
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system.cpu0.rename.BlockCycles 1184 # Number of cycles rename is blocking
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system.cpu0.rename.serializeStallCycles 11729 # count of cycles rename stalled for serializing inst
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system.cpu0.rename.RunCycles 179959 # Number of cycles rename is running
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system.cpu0.rename.UnblockCycles 685 # Number of cycles rename is unblocking
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system.cpu0.rename.RenamedInsts 543550 # Number of instructions processed by rename
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system.cpu0.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
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system.cpu0.rename.LSQFullEvents 277 # Number of times rename has blocked due to LSQ full
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system.cpu0.rename.RenamedOperands 370143 # Number of destination operands rename has renamed
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system.cpu0.rename.RenameLookups 1084537 # Number of register rename lookups that rename has made
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system.cpu0.rename.int_rename_lookups 1084537 # Number of integer rename lookups
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system.cpu0.rename.CommittedMaps 360120 # Number of HB maps that are committed
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system.cpu0.rename.UndoneMaps 10023 # Number of HB maps that are undone due to squashing
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system.cpu0.rename.serializingInsts 796 # count of serializing insts renamed
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system.cpu0.rename.tempSerializingInsts 810 # count of temporary serializing insts renamed
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system.cpu0.rename.skidInsts 3593 # count of insts added to the skid buffer
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system.cpu0.memDep0.insertedLoads 175288 # Number of loads inserted to the mem dependence unit.
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system.cpu0.memDep0.insertedStores 88379 # Number of stores inserted to the mem dependence unit.
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system.cpu0.memDep0.conflictingLoads 85877 # Number of conflicting loads.
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system.cpu0.memDep0.conflictingStores 85749 # Number of conflicting stores.
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system.cpu0.iq.iqInstsAdded 454609 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu0.iq.iqNonSpecInstsAdded 808 # Number of non-speculative instructions added to the IQ
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system.cpu0.iq.iqInstsIssued 453072 # Number of instructions issued
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system.cpu0.iq.iqSquashedInstsIssued 92 # Number of squashed instructions issued
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system.cpu0.iq.iqSquashedInstsExamined 8037 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu0.iq.iqSquashedOperandsExamined 6746 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu0.iq.iqSquashedNonSpecRemoved 249 # Number of squashed non-spec instructions that were removed
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system.cpu0.iq.issued_per_cycle::samples 216259 # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::mean 2.095043 # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::stdev 1.058701 # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::0 33498 15.49% 15.49% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::1 5606 2.59% 18.08% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::2 87868 40.63% 58.71% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::3 86822 40.15% 98.86% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::4 1462 0.68% 99.54% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::5 715 0.33% 99.87% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::6 184 0.09% 99.95% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::7 95 0.04% 100.00% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::8 9 0.00% 100.00% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::total 216259 # Number of insts issued each cycle
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system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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system.cpu0.iq.fu_full::IntAlu 33 15.71% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::IntMult 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::IntDiv 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::FloatAdd 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::FloatCmp 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::FloatCvt 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::FloatMult 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::FloatDiv 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdAdd 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdAlu 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdCmp 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdCvt 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdMisc 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdMult 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdShift 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 15.71% # attempts to use FU when none available
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system.cpu0.iq.fu_full::MemRead 75 35.71% 51.43% # attempts to use FU when none available
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system.cpu0.iq.fu_full::MemWrite 102 48.57% 100.00% # attempts to use FU when none available
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system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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2011-04-20 03:45:23 +02:00
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system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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2011-06-11 04:15:34 +02:00
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system.cpu0.iq.FU_type_0::IntAlu 190073 41.95% 41.95% # Type of FU issued
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2011-04-20 03:45:23 +02:00
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system.cpu0.iq.FU_type_0::IntMult 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 41.95% # Type of FU issued
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system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 41.95% # Type of FU issued
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2011-06-11 04:15:34 +02:00
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system.cpu0.iq.FU_type_0::MemRead 175045 38.64% 80.59% # Type of FU issued
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system.cpu0.iq.FU_type_0::MemWrite 87954 19.41% 100.00% # Type of FU issued
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2011-04-20 03:45:23 +02:00
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system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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2011-06-11 04:15:34 +02:00
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system.cpu0.iq.FU_type_0::total 453072 # Type of FU issued
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system.cpu0.iq.rate 1.930348 # Inst issue rate
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system.cpu0.iq.fu_busy_cnt 210 # FU busy when requested
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system.cpu0.iq.fu_busy_rate 0.000464 # FU busy rate (busy events/executed inst)
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system.cpu0.iq.int_inst_queue_reads 1122705 # Number of integer instruction queue reads
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system.cpu0.iq.int_inst_queue_writes 463496 # Number of integer instruction queue writes
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system.cpu0.iq.int_inst_queue_wakeup_accesses 451578 # Number of integer instruction queue wakeup accesses
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2011-02-08 04:23:13 +01:00
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system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
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system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
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2011-06-11 04:15:34 +02:00
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system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
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system.cpu0.iq.int_alu_accesses 453282 # Number of integer alu accesses
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|
|
system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
|
|
|
|
system.cpu0.iew.lsq.thread0.forwLoads 85551 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu0.iew.lsq.thread0.squashedLoads 1644 # Number of loads squashed
|
|
|
|
|
system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu0.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations
|
|
|
|
|
system.cpu0.iew.lsq.thread0.squashedStores 1051 # Number of stores squashed
|
|
|
|
|
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu0.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
|
|
|
system.cpu0.iew.iewSquashCycles 2035 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu0.iew.iewBlockCycles 809 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu0.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu0.iew.iewDispatchedInsts 541811 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu0.iew.iewDispSquashedInsts 507 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu0.iew.iewDispLoadInsts 175288 # Number of dispatched load instructions
|
|
|
|
|
system.cpu0.iew.iewDispStoreInsts 88379 # Number of dispatched store instructions
|
|
|
|
|
system.cpu0.iew.iewDispNonSpecInsts 716 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu0.iew.iewIQFullEvents 21 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations
|
|
|
|
|
system.cpu0.iew.predictedTakenIncorrect 486 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu0.iew.predictedNotTakenIncorrect 773 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu0.iew.branchMispredicts 1259 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu0.iew.iewExecutedInsts 452172 # Number of executed instructions
|
|
|
|
|
system.cpu0.iew.iewExecLoadInsts 174750 # Number of load instructions executed
|
|
|
|
|
system.cpu0.iew.iewExecSquashedInsts 900 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu0.iew.exec_swp 0 # number of swp insts executed
|
|
|
|
|
system.cpu0.iew.exec_nop 86394 # number of nop insts executed
|
|
|
|
|
system.cpu0.iew.exec_refs 262594 # number of memory reference insts executed
|
|
|
|
|
system.cpu0.iew.exec_branches 89995 # Number of branches executed
|
|
|
|
|
system.cpu0.iew.exec_stores 87844 # Number of stores executed
|
|
|
|
|
system.cpu0.iew.exec_rate 1.926514 # Inst execution rate
|
|
|
|
|
system.cpu0.iew.wb_sent 451822 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu0.iew.wb_count 451578 # cumulative count of insts written-back
|
|
|
|
|
system.cpu0.iew.wb_producers 267957 # num instructions producing a value
|
|
|
|
|
system.cpu0.iew.wb_consumers 269862 # num instructions consuming a value
|
|
|
|
|
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu0.iew.wb_rate 1.923983 # insts written-back per cycle
|
|
|
|
|
system.cpu0.iew.wb_fanout 0.992941 # average fanout of values written-back
|
|
|
|
|
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
|
|
|
system.cpu0.commit.commitCommittedInsts 532525 # The number of committed instructions
|
|
|
|
|
system.cpu0.commit.commitSquashedInsts 9290 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu0.commit.branchMispredicts 1094 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::samples 214241 # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::mean 2.485635 # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::stdev 2.121796 # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::0 33798 15.78% 15.78% # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::1 90322 42.16% 57.93% # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::2 2486 1.16% 59.10% # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::3 740 0.35% 59.44% # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::4 737 0.34% 59.78% # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::5 85412 39.87% 99.65% # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::6 444 0.21% 99.86% # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::7 77 0.04% 99.89% # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::8 225 0.11% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.committed_per_cycle::total 214241 # Number of insts commited each cycle
|
|
|
|
|
system.cpu0.commit.count 532525 # Number of instructions committed
|
|
|
|
|
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu0.commit.refs 260972 # Number of memory references committed
|
|
|
|
|
system.cpu0.commit.loads 173644 # Number of loads committed
|
|
|
|
|
system.cpu0.commit.membars 84 # Number of memory barriers committed
|
|
|
|
|
system.cpu0.commit.branches 89216 # Number of branches committed
|
|
|
|
|
system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu0.commit.int_insts 358450 # Number of committed integer instructions.
|
|
|
|
|
system.cpu0.commit.function_calls 223 # Number of function calls committed.
|
|
|
|
|
system.cpu0.commit.bw_lim_events 225 # number cycles where commit BW limit reached
|
|
|
|
|
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
|
|
|
system.cpu0.rob.rob_reads 754670 # The number of ROB reads
|
|
|
|
|
system.cpu0.rob.rob_writes 1085676 # The number of ROB writes
|
|
|
|
|
system.cpu0.timesIdled 336 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu0.idleCycles 18451 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu0.committedInsts 446494 # Number of Instructions Simulated
|
|
|
|
|
system.cpu0.committedInsts_total 446494 # Number of Instructions Simulated
|
|
|
|
|
system.cpu0.cpi 0.525673 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu0.cpi_total 0.525673 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu0.ipc 1.902322 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu0.ipc_total 1.902322 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu0.int_regfile_reads 809682 # number of integer regfile reads
|
|
|
|
|
system.cpu0.int_regfile_writes 364308 # number of integer regfile writes
|
|
|
|
|
system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
|
|
|
|
|
system.cpu0.misc_regfile_reads 264341 # number of misc regfile reads
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu0.icache.replacements 291 # number of replacements
|
|
|
|
|
system.cpu0.icache.tagsinuse 245.354699 # Cycle average of tags in use
|
|
|
|
|
system.cpu0.icache.total_refs 4480 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu0.icache.sampled_refs 576 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu0.icache.avg_refs 7.777778 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu0.icache.occ_blocks::0 245.354699 # Average occupied blocks per context
|
|
|
|
|
system.cpu0.icache.occ_percent::0 0.479208 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu0.icache.ReadReq_hits 4480 # number of ReadReq hits
|
|
|
|
|
system.cpu0.icache.demand_hits 4480 # number of demand (read+write) hits
|
|
|
|
|
system.cpu0.icache.overall_hits 4480 # number of overall hits
|
|
|
|
|
system.cpu0.icache.ReadReq_misses 709 # number of ReadReq misses
|
|
|
|
|
system.cpu0.icache.demand_misses 709 # number of demand (read+write) misses
|
|
|
|
|
system.cpu0.icache.overall_misses 709 # number of overall misses
|
|
|
|
|
system.cpu0.icache.ReadReq_miss_latency 27352000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu0.icache.demand_miss_latency 27352000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu0.icache.overall_miss_latency 27352000 # number of overall miss cycles
|
|
|
|
|
system.cpu0.icache.ReadReq_accesses 5189 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.icache.demand_accesses 5189 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu0.icache.overall_accesses 5189 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu0.icache.ReadReq_miss_rate 0.136635 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.icache.demand_miss_rate 0.136635 # miss rate for demand accesses
|
|
|
|
|
system.cpu0.icache.overall_miss_rate 0.136635 # miss rate for overall accesses
|
|
|
|
|
system.cpu0.icache.ReadReq_avg_miss_latency 38578.279267 # average ReadReq miss latency
|
|
|
|
|
system.cpu0.icache.demand_avg_miss_latency 38578.279267 # average overall miss latency
|
|
|
|
|
system.cpu0.icache.overall_avg_miss_latency 38578.279267 # average overall miss latency
|
|
|
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 16000 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 16000 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu0.icache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_hits 132 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu0.icache.demand_mshr_hits 132 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu0.icache.overall_mshr_hits 132 # number of overall MSHR hits
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_misses 577 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu0.icache.demand_mshr_misses 577 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu0.icache.overall_mshr_misses 577 # number of overall MSHR misses
|
|
|
|
|
system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency 21152000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu0.icache.demand_mshr_miss_latency 21152000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu0.icache.overall_mshr_miss_latency 21152000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate 0.111197 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.icache.demand_mshr_miss_rate 0.111197 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu0.icache.overall_mshr_miss_rate 0.111197 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36658.578856 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency 36658.578856 # average overall mshr miss latency
|
|
|
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency 36658.578856 # average overall mshr miss latency
|
|
|
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu0.dcache.replacements 9 # number of replacements
|
|
|
|
|
system.cpu0.dcache.tagsinuse 140.104909 # Cycle average of tags in use
|
|
|
|
|
system.cpu0.dcache.total_refs 105362 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu0.dcache.avg_refs 605.528736 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu0.dcache.occ_blocks::0 141.224248 # Average occupied blocks per context
|
|
|
|
|
system.cpu0.dcache.occ_blocks::1 -1.119339 # Average occupied blocks per context
|
|
|
|
|
system.cpu0.dcache.occ_percent::0 0.275829 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu0.dcache.occ_percent::1 -0.002186 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu0.dcache.ReadReq_hits 88681 # number of ReadReq hits
|
|
|
|
|
system.cpu0.dcache.WriteReq_hits 86746 # number of WriteReq hits
|
|
|
|
|
system.cpu0.dcache.SwapReq_hits 16 # number of SwapReq hits
|
|
|
|
|
system.cpu0.dcache.demand_hits 175427 # number of demand (read+write) hits
|
|
|
|
|
system.cpu0.dcache.overall_hits 175427 # number of overall hits
|
|
|
|
|
system.cpu0.dcache.ReadReq_misses 467 # number of ReadReq misses
|
|
|
|
|
system.cpu0.dcache.WriteReq_misses 540 # number of WriteReq misses
|
|
|
|
|
system.cpu0.dcache.SwapReq_misses 26 # number of SwapReq misses
|
|
|
|
|
system.cpu0.dcache.demand_misses 1007 # number of demand (read+write) misses
|
|
|
|
|
system.cpu0.dcache.overall_misses 1007 # number of overall misses
|
|
|
|
|
system.cpu0.dcache.ReadReq_miss_latency 13105000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu0.dcache.WriteReq_miss_latency 24852484 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu0.dcache.SwapReq_miss_latency 437000 # number of SwapReq miss cycles
|
|
|
|
|
system.cpu0.dcache.demand_miss_latency 37957484 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu0.dcache.overall_miss_latency 37957484 # number of overall miss cycles
|
|
|
|
|
system.cpu0.dcache.ReadReq_accesses 89148 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.WriteReq_accesses 87286 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.demand_accesses 176434 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu0.dcache.overall_accesses 176434 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu0.dcache.ReadReq_miss_rate 0.005238 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.dcache.WriteReq_miss_rate 0.006187 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu0.dcache.SwapReq_miss_rate 0.619048 # miss rate for SwapReq accesses
|
|
|
|
|
system.cpu0.dcache.demand_miss_rate 0.005708 # miss rate for demand accesses
|
|
|
|
|
system.cpu0.dcache.overall_miss_rate 0.005708 # miss rate for overall accesses
|
|
|
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency 28062.098501 # average ReadReq miss latency
|
|
|
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency 46023.118519 # average WriteReq miss latency
|
|
|
|
|
system.cpu0.dcache.SwapReq_avg_miss_latency 16807.692308 # average SwapReq miss latency
|
|
|
|
|
system.cpu0.dcache.demand_avg_miss_latency 37693.628600 # average overall miss latency
|
|
|
|
|
system.cpu0.dcache.overall_avg_miss_latency 37693.628600 # average overall miss latency
|
|
|
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 173500 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.dcache.blocked::no_mshrs 26 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 6673.076923 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu0.dcache.writebacks 6 # number of writebacks
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_hits 284 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_hits 365 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu0.dcache.demand_mshr_hits 649 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu0.dcache.overall_mshr_hits 649 # number of overall MSHR hits
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_misses 183 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_misses 175 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu0.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses
|
|
|
|
|
system.cpu0.dcache.demand_mshr_misses 358 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu0.dcache.overall_mshr_misses 358 # number of overall MSHR misses
|
|
|
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency 5054000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency 6424000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.SwapReq_mshr_miss_latency 359000 # number of SwapReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.demand_mshr_miss_latency 11478000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.overall_mshr_miss_latency 11478000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002053 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate 0.002005 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu0.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses
|
|
|
|
|
system.cpu0.dcache.demand_mshr_miss_rate 0.002029 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu0.dcache.overall_mshr_miss_rate 0.002029 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27617.486339 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36708.571429 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 13807.692308 # average SwapReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency 32061.452514 # average overall mshr miss latency
|
|
|
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency 32061.452514 # average overall mshr miss latency
|
|
|
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu1.numCycles 199395 # number of cpu cycles simulated
|
|
|
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
|
|
|
system.cpu1.BPredUnit.lookups 54492 # Number of BP lookups
|
|
|
|
|
system.cpu1.BPredUnit.condPredicted 52165 # Number of conditional branches predicted
|
|
|
|
|
system.cpu1.BPredUnit.condIncorrect 1102 # Number of conditional branches incorrect
|
|
|
|
|
system.cpu1.BPredUnit.BTBLookups 53937 # Number of BTB lookups
|
|
|
|
|
system.cpu1.BPredUnit.BTBHits 51730 # Number of BTB hits
|
2009-04-21 17:37:50 +02:00
|
|
|
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu1.BPredUnit.usedRAS 504 # Number of times the RAS was used to get a target.
|
|
|
|
|
system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
|
|
|
|
|
system.cpu1.fetch.icacheStallCycles 21267 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu1.fetch.Insts 303560 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu1.fetch.Branches 54492 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu1.fetch.predictedBranches 52234 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu1.fetch.Cycles 111140 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu1.fetch.SquashCycles 1177 # Number of cycles fetch has spent squashing
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu1.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu1.fetch.CacheLines 21267 # Number of cache lines fetched
|
|
|
|
|
system.cpu1.fetch.IcacheSquashes 240 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu1.fetch.rateDist::samples 196288 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::mean 1.546503 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::stdev 2.023941 # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu1.fetch.rateDist::0 85148 43.38% 43.38% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::1 57550 29.32% 72.70% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::2 7358 3.75% 76.45% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::3 2678 1.36% 77.81% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::4 1913 0.97% 78.79% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::5 37446 19.08% 97.86% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::6 2461 1.25% 99.12% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::7 260 0.13% 99.25% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::8 1474 0.75% 100.00% # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu1.fetch.rateDist::total 196288 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.branchRate 0.273287 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu1.fetch.rate 1.522405 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu1.decode.IdleCycles 56178 # Number of cycles decode is idle
|
|
|
|
|
system.cpu1.decode.BlockedCycles 20903 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu1.decode.RunCycles 104877 # Number of cycles decode is running
|
|
|
|
|
system.cpu1.decode.UnblockCycles 5862 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu1.decode.SquashCycles 1747 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu1.decode.DecodedInsts 302339 # Number of instructions handled by decode
|
|
|
|
|
system.cpu1.rename.SquashCycles 1747 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu1.rename.IdleCycles 56804 # Number of cycles rename is idle
|
|
|
|
|
system.cpu1.rename.BlockCycles 7350 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu1.rename.serializeStallCycles 12853 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu1.rename.RunCycles 110244 # Number of cycles rename is running
|
|
|
|
|
system.cpu1.rename.UnblockCycles 569 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu1.rename.RenamedInsts 300619 # Number of instructions processed by rename
|
|
|
|
|
system.cpu1.rename.IQFullEvents 47 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu1.rename.LSQFullEvents 45 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu1.rename.RenamedOperands 206640 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu1.rename.RenameLookups 572225 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu1.rename.int_rename_lookups 572225 # Number of integer rename lookups
|
|
|
|
|
system.cpu1.rename.CommittedMaps 198555 # Number of HB maps that are committed
|
|
|
|
|
system.cpu1.rename.UndoneMaps 8085 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu1.rename.serializingInsts 945 # count of serializing insts renamed
|
|
|
|
|
system.cpu1.rename.tempSerializingInsts 1003 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu1.rename.skidInsts 2692 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu1.memDep0.insertedLoads 86261 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu1.memDep0.insertedStores 40322 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu1.memDep0.conflictingLoads 42289 # Number of conflicting loads.
|
|
|
|
|
system.cpu1.memDep0.conflictingStores 35840 # Number of conflicting stores.
|
|
|
|
|
system.cpu1.iq.iqInstsAdded 247735 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu1.iq.iqNonSpecInstsAdded 7474 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu1.iq.iqInstsIssued 252580 # Number of instructions issued
|
2011-01-16 00:30:34 +01:00
|
|
|
system.cpu1.iq.iqSquashedInstsIssued 2 # Number of squashed instructions issued
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu1.iq.iqSquashedInstsExamined 6388 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu1.iq.iqSquashedOperandsExamined 5920 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu1.iq.iqSquashedNonSpecRemoved 555 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::samples 196288 # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::mean 1.286783 # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::stdev 1.284176 # Number of insts issued each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu1.iq.issued_per_cycle::0 81418 41.48% 41.48% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::1 28257 14.40% 55.87% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::2 42150 21.47% 77.35% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::3 39998 20.38% 97.73% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::4 2642 1.35% 99.07% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::5 1578 0.80% 99.88% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::6 154 0.08% 99.95% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::7 81 0.04% 99.99% # Number of insts issued each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu1.iq.issued_per_cycle::8 10 0.01% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu1.iq.issued_per_cycle::total 196288 # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::IntAlu 11 5.79% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::IntMult 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::MemRead 48 25.26% 31.05% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::MemWrite 131 68.95% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::IntAlu 120684 47.78% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::MemRead 91955 36.41% 84.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::MemWrite 39941 15.81% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.FU_type_0::total 252580 # Type of FU issued
|
|
|
|
|
system.cpu1.iq.rate 1.266732 # Inst issue rate
|
|
|
|
|
system.cpu1.iq.fu_busy_cnt 190 # FU busy when requested
|
|
|
|
|
system.cpu1.iq.fu_busy_rate 0.000752 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu1.iq.int_inst_queue_reads 701640 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu1.iq.int_inst_queue_writes 261627 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu1.iq.int_inst_queue_wakeup_accesses 251253 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu1.iq.int_alu_accesses 252770 # Number of integer alu accesses
|
|
|
|
|
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
|
|
|
|
system.cpu1.iew.lsq.thread0.forwLoads 35691 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu1.iew.lsq.thread0.squashedLoads 1436 # Number of loads squashed
|
|
|
|
|
system.cpu1.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu1.iew.lsq.thread0.memOrderViolation 30 # Number of memory ordering violations
|
|
|
|
|
system.cpu1.iew.lsq.thread0.squashedStores 758 # Number of stores squashed
|
|
|
|
|
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
|
|
|
system.cpu1.iew.iewSquashCycles 1747 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu1.iew.iewBlockCycles 1477 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu1.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu1.iew.iewDispatchedInsts 298452 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu1.iew.iewDispSquashedInsts 533 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu1.iew.iewDispLoadInsts 86261 # Number of dispatched load instructions
|
|
|
|
|
system.cpu1.iew.iewDispStoreInsts 40322 # Number of dispatched store instructions
|
|
|
|
|
system.cpu1.iew.iewDispNonSpecInsts 920 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu1.iew.memOrderViolationEvents 30 # Number of memory order violations
|
|
|
|
|
system.cpu1.iew.predictedTakenIncorrect 1025 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu1.iew.predictedNotTakenIncorrect 178 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu1.iew.branchMispredicts 1203 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu1.iew.iewExecutedInsts 251613 # Number of executed instructions
|
|
|
|
|
system.cpu1.iew.iewExecLoadInsts 85566 # Number of load instructions executed
|
|
|
|
|
system.cpu1.iew.iewExecSquashedInsts 967 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu1.iew.exec_swp 0 # number of swp insts executed
|
|
|
|
|
system.cpu1.iew.exec_nop 43243 # number of nop insts executed
|
|
|
|
|
system.cpu1.iew.exec_refs 125476 # number of memory reference insts executed
|
|
|
|
|
system.cpu1.iew.exec_branches 52279 # Number of branches executed
|
|
|
|
|
system.cpu1.iew.exec_stores 39910 # Number of stores executed
|
|
|
|
|
system.cpu1.iew.exec_rate 1.261882 # Inst execution rate
|
|
|
|
|
system.cpu1.iew.wb_sent 251386 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu1.iew.wb_count 251253 # cumulative count of insts written-back
|
|
|
|
|
system.cpu1.iew.wb_producers 141847 # num instructions producing a value
|
|
|
|
|
system.cpu1.iew.wb_consumers 145498 # num instructions consuming a value
|
|
|
|
|
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu1.iew.wb_rate 1.260077 # insts written-back per cycle
|
|
|
|
|
system.cpu1.iew.wb_fanout 0.974907 # average fanout of values written-back
|
|
|
|
|
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
|
|
|
system.cpu1.commit.commitCommittedInsts 290439 # The number of committed instructions
|
|
|
|
|
system.cpu1.commit.commitSquashedInsts 8011 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu1.commit.commitNonSpecStalls 6919 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu1.commit.branchMispredicts 1102 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::samples 187821 # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::mean 1.546361 # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::stdev 1.941498 # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::0 80077 42.63% 42.63% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::1 52511 27.96% 70.59% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::2 7488 3.99% 74.58% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::3 7738 4.12% 78.70% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::4 2462 1.31% 80.01% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::5 36475 19.42% 99.43% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::6 459 0.24% 99.67% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::7 127 0.07% 99.74% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::8 484 0.26% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.committed_per_cycle::total 187821 # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.count 290439 # Number of instructions committed
|
|
|
|
|
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu1.commit.refs 124389 # Number of memory references committed
|
|
|
|
|
system.cpu1.commit.loads 84825 # Number of loads committed
|
|
|
|
|
system.cpu1.commit.membars 6207 # Number of memory barriers committed
|
|
|
|
|
system.cpu1.commit.branches 51732 # Number of branches committed
|
|
|
|
|
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu1.commit.int_insts 198246 # Number of committed integer instructions.
|
|
|
|
|
system.cpu1.commit.function_calls 322 # Number of function calls committed.
|
|
|
|
|
system.cpu1.commit.bw_lim_events 484 # number cycles where commit BW limit reached
|
|
|
|
|
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
|
|
|
system.cpu1.rob.rob_reads 485200 # The number of ROB reads
|
|
|
|
|
system.cpu1.rob.rob_writes 598649 # The number of ROB writes
|
|
|
|
|
system.cpu1.timesIdled 276 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu1.idleCycles 3107 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu1.committedInsts 241708 # Number of Instructions Simulated
|
|
|
|
|
system.cpu1.committedInsts_total 241708 # Number of Instructions Simulated
|
|
|
|
|
system.cpu1.cpi 0.824942 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu1.cpi_total 0.824942 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu1.ipc 1.212207 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu1.ipc_total 1.212207 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu1.int_regfile_reads 433901 # number of integer regfile reads
|
|
|
|
|
system.cpu1.int_regfile_writes 201135 # number of integer regfile writes
|
|
|
|
|
system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
|
|
|
|
|
system.cpu1.misc_regfile_reads 127021 # number of misc regfile reads
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu1.misc_regfile_writes 646 # number of misc regfile writes
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu1.icache.replacements 335 # number of replacements
|
|
|
|
|
system.cpu1.icache.tagsinuse 81.445548 # Cycle average of tags in use
|
|
|
|
|
system.cpu1.icache.total_refs 20780 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu1.icache.sampled_refs 442 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu1.icache.avg_refs 47.013575 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu1.icache.occ_blocks::0 81.445548 # Average occupied blocks per context
|
|
|
|
|
system.cpu1.icache.occ_percent::0 0.159073 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu1.icache.ReadReq_hits 20780 # number of ReadReq hits
|
|
|
|
|
system.cpu1.icache.demand_hits 20780 # number of demand (read+write) hits
|
|
|
|
|
system.cpu1.icache.overall_hits 20780 # number of overall hits
|
|
|
|
|
system.cpu1.icache.ReadReq_misses 487 # number of ReadReq misses
|
|
|
|
|
system.cpu1.icache.demand_misses 487 # number of demand (read+write) misses
|
|
|
|
|
system.cpu1.icache.overall_misses 487 # number of overall misses
|
|
|
|
|
system.cpu1.icache.ReadReq_miss_latency 7348000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu1.icache.demand_miss_latency 7348000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu1.icache.overall_miss_latency 7348000 # number of overall miss cycles
|
|
|
|
|
system.cpu1.icache.ReadReq_accesses 21267 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.icache.demand_accesses 21267 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu1.icache.overall_accesses 21267 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu1.icache.ReadReq_miss_rate 0.022899 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.icache.demand_miss_rate 0.022899 # miss rate for demand accesses
|
|
|
|
|
system.cpu1.icache.overall_miss_rate 0.022899 # miss rate for overall accesses
|
|
|
|
|
system.cpu1.icache.ReadReq_avg_miss_latency 15088.295688 # average ReadReq miss latency
|
|
|
|
|
system.cpu1.icache.demand_avg_miss_latency 15088.295688 # average overall miss latency
|
|
|
|
|
system.cpu1.icache.overall_avg_miss_latency 15088.295688 # average overall miss latency
|
|
|
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu1.icache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_hits 45 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu1.icache.demand_mshr_hits 45 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu1.icache.overall_mshr_hits 45 # number of overall MSHR hits
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_misses 442 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu1.icache.demand_mshr_misses 442 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu1.icache.overall_mshr_misses 442 # number of overall MSHR misses
|
|
|
|
|
system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency 5515000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.demand_mshr_miss_latency 5515000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.overall_mshr_miss_latency 5515000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate 0.020783 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.icache.demand_mshr_miss_rate 0.020783 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu1.icache.overall_mshr_miss_rate 0.020783 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12477.375566 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency 12477.375566 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency 12477.375566 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu1.dcache.replacements 2 # number of replacements
|
|
|
|
|
system.cpu1.dcache.tagsinuse 15.853389 # Cycle average of tags in use
|
|
|
|
|
system.cpu1.dcache.total_refs 45287 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu1.dcache.avg_refs 1561.620690 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu1.dcache.occ_blocks::0 24.109583 # Average occupied blocks per context
|
|
|
|
|
system.cpu1.dcache.occ_blocks::1 -8.256194 # Average occupied blocks per context
|
|
|
|
|
system.cpu1.dcache.occ_percent::0 0.047089 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu1.dcache.occ_percent::1 -0.016125 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu1.dcache.ReadReq_hits 49422 # number of ReadReq hits
|
|
|
|
|
system.cpu1.dcache.WriteReq_hits 39377 # number of WriteReq hits
|
|
|
|
|
system.cpu1.dcache.SwapReq_hits 14 # number of SwapReq hits
|
|
|
|
|
system.cpu1.dcache.demand_hits 88799 # number of demand (read+write) hits
|
|
|
|
|
system.cpu1.dcache.overall_hits 88799 # number of overall hits
|
|
|
|
|
system.cpu1.dcache.ReadReq_misses 438 # number of ReadReq misses
|
|
|
|
|
system.cpu1.dcache.WriteReq_misses 121 # number of WriteReq misses
|
|
|
|
|
system.cpu1.dcache.SwapReq_misses 52 # number of SwapReq misses
|
|
|
|
|
system.cpu1.dcache.demand_misses 559 # number of demand (read+write) misses
|
|
|
|
|
system.cpu1.dcache.overall_misses 559 # number of overall misses
|
|
|
|
|
system.cpu1.dcache.ReadReq_miss_latency 9255000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu1.dcache.WriteReq_miss_latency 2991000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu1.dcache.SwapReq_miss_latency 1250500 # number of SwapReq miss cycles
|
|
|
|
|
system.cpu1.dcache.demand_miss_latency 12246000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu1.dcache.overall_miss_latency 12246000 # number of overall miss cycles
|
|
|
|
|
system.cpu1.dcache.ReadReq_accesses 49860 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.WriteReq_accesses 39498 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.SwapReq_accesses 66 # number of SwapReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.demand_accesses 89358 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu1.dcache.overall_accesses 89358 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu1.dcache.ReadReq_miss_rate 0.008785 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.dcache.WriteReq_miss_rate 0.003063 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu1.dcache.SwapReq_miss_rate 0.787879 # miss rate for SwapReq accesses
|
|
|
|
|
system.cpu1.dcache.demand_miss_rate 0.006256 # miss rate for demand accesses
|
|
|
|
|
system.cpu1.dcache.overall_miss_rate 0.006256 # miss rate for overall accesses
|
|
|
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency 21130.136986 # average ReadReq miss latency
|
|
|
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency 24719.008264 # average WriteReq miss latency
|
|
|
|
|
system.cpu1.dcache.SwapReq_avg_miss_latency 24048.076923 # average SwapReq miss latency
|
|
|
|
|
system.cpu1.dcache.demand_avg_miss_latency 21906.976744 # average overall miss latency
|
|
|
|
|
system.cpu1.dcache.overall_avg_miss_latency 21906.976744 # average overall miss latency
|
|
|
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu1.dcache.writebacks 1 # number of writebacks
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_hits 282 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu1.dcache.demand_mshr_hits 300 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu1.dcache.overall_mshr_hits 300 # number of overall MSHR hits
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_misses 156 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_misses 103 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.SwapReq_mshr_misses 52 # number of SwapReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.demand_mshr_misses 259 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu1.dcache.overall_mshr_misses 259 # number of overall MSHR misses
|
|
|
|
|
system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency 2111500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency 1675000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.SwapReq_mshr_miss_latency 1094500 # number of SwapReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.demand_mshr_miss_latency 3786500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.overall_mshr_miss_latency 3786500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate 0.003129 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate 0.002608 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu1.dcache.SwapReq_mshr_miss_rate 0.787879 # mshr miss rate for SwapReq accesses
|
|
|
|
|
system.cpu1.dcache.demand_mshr_miss_rate 0.002898 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu1.dcache.overall_mshr_miss_rate 0.002898 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13535.256410 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 16262.135922 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 21048.076923 # average SwapReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency 14619.691120 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency 14619.691120 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu2.numCycles 199106 # number of cpu cycles simulated
|
|
|
|
|
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
|
|
|
system.cpu2.BPredUnit.lookups 57971 # Number of BP lookups
|
|
|
|
|
system.cpu2.BPredUnit.condPredicted 55658 # Number of conditional branches predicted
|
|
|
|
|
system.cpu2.BPredUnit.condIncorrect 1119 # Number of conditional branches incorrect
|
|
|
|
|
system.cpu2.BPredUnit.BTBLookups 57356 # Number of BTB lookups
|
|
|
|
|
system.cpu2.BPredUnit.BTBHits 55221 # Number of BTB hits
|
|
|
|
|
system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
|
|
|
system.cpu2.BPredUnit.usedRAS 508 # Number of times the RAS was used to get a target.
|
|
|
|
|
system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
|
|
|
|
|
system.cpu2.fetch.icacheStallCycles 18228 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu2.fetch.Insts 327195 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu2.fetch.Branches 57971 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu2.fetch.predictedBranches 55729 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu2.fetch.Cycles 116612 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu2.fetch.SquashCycles 1192 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu2.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
|
|
|
system.cpu2.fetch.CacheLines 18228 # Number of cache lines fetched
|
|
|
|
|
system.cpu2.fetch.IcacheSquashes 237 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu2.fetch.rateDist::samples 193972 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu2.fetch.rateDist::mean 1.686816 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu2.fetch.rateDist::stdev 2.080601 # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu2.fetch.rateDist::0 77360 39.88% 39.88% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu2.fetch.rateDist::1 59528 30.69% 70.57% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu2.fetch.rateDist::2 5848 3.01% 73.59% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu2.fetch.rateDist::3 2830 1.46% 75.04% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu2.fetch.rateDist::4 1905 0.98% 76.03% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu2.fetch.rateDist::5 42329 21.82% 97.85% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu2.fetch.rateDist::6 2448 1.26% 99.11% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu2.fetch.rateDist::7 264 0.14% 99.25% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu2.fetch.rateDist::8 1460 0.75% 100.00% # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu2.fetch.rateDist::total 193972 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu2.fetch.branchRate 0.291156 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu2.fetch.rate 1.643321 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu2.decode.IdleCycles 48904 # Number of cycles decode is idle
|
|
|
|
|
system.cpu2.decode.BlockedCycles 20328 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu2.decode.RunCycles 111841 # Number of cycles decode is running
|
|
|
|
|
system.cpu2.decode.UnblockCycles 4382 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu2.decode.SquashCycles 1806 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu2.decode.DecodedInsts 325997 # Number of instructions handled by decode
|
|
|
|
|
system.cpu2.rename.SquashCycles 1806 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu2.rename.IdleCycles 49533 # Number of cycles rename is idle
|
|
|
|
|
system.cpu2.rename.BlockCycles 6147 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu2.rename.serializeStallCycles 13457 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu2.rename.RunCycles 115712 # Number of cycles rename is running
|
|
|
|
|
system.cpu2.rename.UnblockCycles 606 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu2.rename.RenamedInsts 324330 # Number of instructions processed by rename
|
|
|
|
|
system.cpu2.rename.IQFullEvents 65 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu2.rename.LSQFullEvents 45 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu2.rename.RenamedOperands 224740 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu2.rename.RenameLookups 625107 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu2.rename.int_rename_lookups 625107 # Number of integer rename lookups
|
|
|
|
|
system.cpu2.rename.CommittedMaps 216561 # Number of HB maps that are committed
|
|
|
|
|
system.cpu2.rename.UndoneMaps 8179 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu2.rename.serializingInsts 949 # count of serializing insts renamed
|
|
|
|
|
system.cpu2.rename.tempSerializingInsts 1011 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu2.rename.skidInsts 2760 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu2.memDep0.insertedLoads 94652 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu2.memDep0.insertedStores 45182 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu2.memDep0.conflictingLoads 45774 # Number of conflicting loads.
|
|
|
|
|
system.cpu2.memDep0.conflictingStores 40713 # Number of conflicting stores.
|
|
|
|
|
system.cpu2.iq.iqInstsAdded 269361 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu2.iq.iqNonSpecInstsAdded 6099 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu2.iq.iqInstsIssued 272571 # Number of instructions issued
|
2011-01-16 00:30:34 +01:00
|
|
|
system.cpu2.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu2.iq.iqSquashedInstsExamined 6651 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu2.iq.iqSquashedOperandsExamined 6299 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu2.iq.iqSquashedNonSpecRemoved 621 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu2.iq.issued_per_cycle::samples 193972 # Number of insts issued each cycle
|
|
|
|
|
system.cpu2.iq.issued_per_cycle::mean 1.405208 # Number of insts issued each cycle
|
|
|
|
|
system.cpu2.iq.issued_per_cycle::stdev 1.293243 # Number of insts issued each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu2.iq.issued_per_cycle::0 73708 38.00% 38.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu2.iq.issued_per_cycle::1 23872 12.31% 50.31% # Number of insts issued each cycle
|
|
|
|
|
system.cpu2.iq.issued_per_cycle::2 47052 24.26% 74.56% # Number of insts issued each cycle
|
|
|
|
|
system.cpu2.iq.issued_per_cycle::3 44924 23.16% 97.72% # Number of insts issued each cycle
|
|
|
|
|
system.cpu2.iq.issued_per_cycle::4 2620 1.35% 99.07% # Number of insts issued each cycle
|
|
|
|
|
system.cpu2.iq.issued_per_cycle::5 1535 0.79% 99.87% # Number of insts issued each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu2.iq.issued_per_cycle::6 168 0.09% 99.95% # Number of insts issued each cycle
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu2.iq.issued_per_cycle::7 84 0.04% 100.00% # Number of insts issued each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu2.iq.issued_per_cycle::8 9 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu2.iq.issued_per_cycle::total 193972 # Number of insts issued each cycle
|
|
|
|
|
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::IntAlu 12 5.97% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::IntMult 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::MemRead 58 28.86% 34.83% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::MemWrite 131 65.17% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::IntAlu 128963 47.31% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::IntMult 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.31% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::MemRead 98810 36.25% 83.56% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::MemWrite 44798 16.44% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu2.iq.FU_type_0::total 272571 # Type of FU issued
|
|
|
|
|
system.cpu2.iq.rate 1.368974 # Inst issue rate
|
|
|
|
|
system.cpu2.iq.fu_busy_cnt 201 # FU busy when requested
|
|
|
|
|
system.cpu2.iq.fu_busy_rate 0.000737 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu2.iq.int_inst_queue_reads 739316 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu2.iq.int_inst_queue_writes 282139 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu2.iq.int_inst_queue_wakeup_accesses 271248 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu2.iq.int_alu_accesses 272772 # Number of integer alu accesses
|
|
|
|
|
system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
|
|
|
|
system.cpu2.iew.lsq.thread0.forwLoads 40559 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu2.iew.lsq.thread0.squashedLoads 1552 # Number of loads squashed
|
|
|
|
|
system.cpu2.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu2.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations
|
|
|
|
|
system.cpu2.iew.lsq.thread0.squashedStores 752 # Number of stores squashed
|
|
|
|
|
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
|
|
|
system.cpu2.iew.iewSquashCycles 1806 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu2.iew.iewBlockCycles 1706 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu2.iew.iewUnblockCycles 63 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu2.iew.iewDispatchedInsts 322227 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu2.iew.iewDispSquashedInsts 522 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu2.iew.iewDispLoadInsts 94652 # Number of dispatched load instructions
|
|
|
|
|
system.cpu2.iew.iewDispStoreInsts 45182 # Number of dispatched store instructions
|
|
|
|
|
system.cpu2.iew.iewDispNonSpecInsts 927 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu2.iew.iewIQFullEvents 55 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu2.iew.memOrderViolationEvents 28 # Number of memory order violations
|
|
|
|
|
system.cpu2.iew.predictedTakenIncorrect 1035 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu2.iew.predictedNotTakenIncorrect 187 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu2.iew.branchMispredicts 1222 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu2.iew.iewExecutedInsts 271613 # Number of executed instructions
|
|
|
|
|
system.cpu2.iew.iewExecLoadInsts 93867 # Number of load instructions executed
|
|
|
|
|
system.cpu2.iew.iewExecSquashedInsts 958 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu2.iew.exec_swp 0 # number of swp insts executed
|
|
|
|
|
system.cpu2.iew.exec_nop 46767 # number of nop insts executed
|
|
|
|
|
system.cpu2.iew.exec_refs 138637 # number of memory reference insts executed
|
|
|
|
|
system.cpu2.iew.exec_branches 55708 # Number of branches executed
|
|
|
|
|
system.cpu2.iew.exec_stores 44770 # Number of stores executed
|
|
|
|
|
system.cpu2.iew.exec_rate 1.364163 # Inst execution rate
|
|
|
|
|
system.cpu2.iew.wb_sent 271381 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu2.iew.wb_count 271248 # cumulative count of insts written-back
|
|
|
|
|
system.cpu2.iew.wb_producers 155012 # num instructions producing a value
|
|
|
|
|
system.cpu2.iew.wb_consumers 158673 # num instructions consuming a value
|
|
|
|
|
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu2.iew.wb_rate 1.362330 # insts written-back per cycle
|
|
|
|
|
system.cpu2.iew.wb_fanout 0.976927 # average fanout of values written-back
|
|
|
|
|
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
|
|
|
system.cpu2.commit.commitCommittedInsts 313840 # The number of committed instructions
|
|
|
|
|
system.cpu2.commit.commitSquashedInsts 8384 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu2.commit.commitNonSpecStalls 5478 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu2.commit.branchMispredicts 1119 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu2.commit.committed_per_cycle::samples 185456 # Number of insts commited each cycle
|
|
|
|
|
system.cpu2.commit.committed_per_cycle::mean 1.692261 # Number of insts commited each cycle
|
|
|
|
|
system.cpu2.commit.committed_per_cycle::stdev 1.994391 # Number of insts commited each cycle
|
|
|
|
|
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu2.commit.committed_per_cycle::0 70838 38.20% 38.20% # Number of insts commited each cycle
|
|
|
|
|
system.cpu2.commit.committed_per_cycle::1 55984 30.19% 68.38% # Number of insts commited each cycle
|
|
|
|
|
system.cpu2.commit.committed_per_cycle::2 7465 4.03% 72.41% # Number of insts commited each cycle
|
|
|
|
|
system.cpu2.commit.committed_per_cycle::3 6288 3.39% 75.80% # Number of insts commited each cycle
|
|
|
|
|
system.cpu2.commit.committed_per_cycle::4 2454 1.32% 77.12% # Number of insts commited each cycle
|
|
|
|
|
system.cpu2.commit.committed_per_cycle::5 41414 22.33% 99.45% # Number of insts commited each cycle
|
|
|
|
|
system.cpu2.commit.committed_per_cycle::6 401 0.22% 99.67% # Number of insts commited each cycle
|
|
|
|
|
system.cpu2.commit.committed_per_cycle::7 126 0.07% 99.74% # Number of insts commited each cycle
|
|
|
|
|
system.cpu2.commit.committed_per_cycle::8 486 0.26% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
|
|
|
system.cpu2.commit.committed_per_cycle::total 185456 # Number of insts commited each cycle
|
|
|
|
|
system.cpu2.commit.count 313840 # Number of instructions committed
|
|
|
|
|
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu2.commit.refs 137530 # Number of memory references committed
|
|
|
|
|
system.cpu2.commit.loads 93100 # Number of loads committed
|
|
|
|
|
system.cpu2.commit.membars 4761 # Number of memory barriers committed
|
|
|
|
|
system.cpu2.commit.branches 55156 # Number of branches committed
|
|
|
|
|
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu2.commit.int_insts 214804 # Number of committed integer instructions.
|
|
|
|
|
system.cpu2.commit.function_calls 322 # Number of function calls committed.
|
|
|
|
|
system.cpu2.commit.bw_lim_events 486 # number cycles where commit BW limit reached
|
|
|
|
|
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
|
|
|
system.cpu2.rob.rob_reads 506607 # The number of ROB reads
|
|
|
|
|
system.cpu2.rob.rob_writes 646257 # The number of ROB writes
|
|
|
|
|
system.cpu2.timesIdled 280 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu2.idleCycles 5134 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu2.committedInsts 263136 # Number of Instructions Simulated
|
|
|
|
|
system.cpu2.committedInsts_total 263136 # Number of Instructions Simulated
|
|
|
|
|
system.cpu2.cpi 0.756666 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu2.cpi_total 0.756666 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu2.ipc 1.321587 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu2.ipc_total 1.321587 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu2.int_regfile_reads 473358 # number of integer regfile reads
|
|
|
|
|
system.cpu2.int_regfile_writes 219156 # number of integer regfile writes
|
|
|
|
|
system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
|
|
|
|
|
system.cpu2.misc_regfile_reads 140181 # number of misc regfile reads
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu2.misc_regfile_writes 646 # number of misc regfile writes
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu2.icache.replacements 333 # number of replacements
|
|
|
|
|
system.cpu2.icache.tagsinuse 86.095246 # Cycle average of tags in use
|
|
|
|
|
system.cpu2.icache.total_refs 17739 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu2.icache.sampled_refs 438 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu2.icache.avg_refs 40.500000 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu2.icache.occ_blocks::0 86.095246 # Average occupied blocks per context
|
|
|
|
|
system.cpu2.icache.occ_percent::0 0.168155 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu2.icache.ReadReq_hits 17739 # number of ReadReq hits
|
|
|
|
|
system.cpu2.icache.demand_hits 17739 # number of demand (read+write) hits
|
|
|
|
|
system.cpu2.icache.overall_hits 17739 # number of overall hits
|
|
|
|
|
system.cpu2.icache.ReadReq_misses 489 # number of ReadReq misses
|
|
|
|
|
system.cpu2.icache.demand_misses 489 # number of demand (read+write) misses
|
|
|
|
|
system.cpu2.icache.overall_misses 489 # number of overall misses
|
|
|
|
|
system.cpu2.icache.ReadReq_miss_latency 10440000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu2.icache.demand_miss_latency 10440000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu2.icache.overall_miss_latency 10440000 # number of overall miss cycles
|
|
|
|
|
system.cpu2.icache.ReadReq_accesses 18228 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu2.icache.demand_accesses 18228 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu2.icache.overall_accesses 18228 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu2.icache.ReadReq_miss_rate 0.026827 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu2.icache.demand_miss_rate 0.026827 # miss rate for demand accesses
|
|
|
|
|
system.cpu2.icache.overall_miss_rate 0.026827 # miss rate for overall accesses
|
|
|
|
|
system.cpu2.icache.ReadReq_avg_miss_latency 21349.693252 # average ReadReq miss latency
|
|
|
|
|
system.cpu2.icache.demand_avg_miss_latency 21349.693252 # average overall miss latency
|
|
|
|
|
system.cpu2.icache.overall_avg_miss_latency 21349.693252 # average overall miss latency
|
|
|
|
|
system.cpu2.icache.blocked_cycles::no_mshrs 32500 # number of cycles access was blocked
|
|
|
|
|
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
|
|
|
|
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu2.icache.avg_blocked_cycles::no_mshrs 32500 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu2.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu2.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu2.icache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu2.icache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu2.icache.demand_mshr_hits 51 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu2.icache.overall_mshr_hits 51 # number of overall MSHR hits
|
|
|
|
|
system.cpu2.icache.ReadReq_mshr_misses 438 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu2.icache.demand_mshr_misses 438 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu2.icache.overall_mshr_misses 438 # number of overall MSHR misses
|
|
|
|
|
system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency 8036500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu2.icache.demand_mshr_miss_latency 8036500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu2.icache.overall_mshr_miss_latency 8036500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate 0.024029 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu2.icache.demand_mshr_miss_rate 0.024029 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu2.icache.overall_mshr_miss_rate 0.024029 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18348.173516 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency 18348.173516 # average overall mshr miss latency
|
|
|
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency 18348.173516 # average overall mshr miss latency
|
|
|
|
|
system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu2.dcache.replacements 2 # number of replacements
|
|
|
|
|
system.cpu2.dcache.tagsinuse 18.718664 # Cycle average of tags in use
|
|
|
|
|
system.cpu2.dcache.total_refs 50172 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu2.dcache.sampled_refs 30 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu2.dcache.avg_refs 1672.400000 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu2.dcache.occ_blocks::0 27.030706 # Average occupied blocks per context
|
|
|
|
|
system.cpu2.dcache.occ_blocks::1 -8.312042 # Average occupied blocks per context
|
|
|
|
|
system.cpu2.dcache.occ_percent::0 0.052794 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu2.dcache.occ_percent::1 -0.016234 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu2.dcache.ReadReq_hits 52844 # number of ReadReq hits
|
|
|
|
|
system.cpu2.dcache.WriteReq_hits 44237 # number of WriteReq hits
|
|
|
|
|
system.cpu2.dcache.SwapReq_hits 12 # number of SwapReq hits
|
|
|
|
|
system.cpu2.dcache.demand_hits 97081 # number of demand (read+write) hits
|
|
|
|
|
system.cpu2.dcache.overall_hits 97081 # number of overall hits
|
|
|
|
|
system.cpu2.dcache.ReadReq_misses 446 # number of ReadReq misses
|
|
|
|
|
system.cpu2.dcache.WriteReq_misses 122 # number of WriteReq misses
|
|
|
|
|
system.cpu2.dcache.SwapReq_misses 59 # number of SwapReq misses
|
|
|
|
|
system.cpu2.dcache.demand_misses 568 # number of demand (read+write) misses
|
|
|
|
|
system.cpu2.dcache.overall_misses 568 # number of overall misses
|
|
|
|
|
system.cpu2.dcache.ReadReq_miss_latency 10164500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu2.dcache.WriteReq_miss_latency 2987000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu2.dcache.SwapReq_miss_latency 1380500 # number of SwapReq miss cycles
|
|
|
|
|
system.cpu2.dcache.demand_miss_latency 13151500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu2.dcache.overall_miss_latency 13151500 # number of overall miss cycles
|
|
|
|
|
system.cpu2.dcache.ReadReq_accesses 53290 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu2.dcache.WriteReq_accesses 44359 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu2.dcache.SwapReq_accesses 71 # number of SwapReq accesses(hits+misses)
|
|
|
|
|
system.cpu2.dcache.demand_accesses 97649 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu2.dcache.overall_accesses 97649 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu2.dcache.ReadReq_miss_rate 0.008369 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu2.dcache.WriteReq_miss_rate 0.002750 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu2.dcache.SwapReq_miss_rate 0.830986 # miss rate for SwapReq accesses
|
|
|
|
|
system.cpu2.dcache.demand_miss_rate 0.005817 # miss rate for demand accesses
|
|
|
|
|
system.cpu2.dcache.overall_miss_rate 0.005817 # miss rate for overall accesses
|
|
|
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency 22790.358744 # average ReadReq miss latency
|
|
|
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency 24483.606557 # average WriteReq miss latency
|
|
|
|
|
system.cpu2.dcache.SwapReq_avg_miss_latency 23398.305085 # average SwapReq miss latency
|
|
|
|
|
system.cpu2.dcache.demand_avg_miss_latency 23154.049296 # average overall miss latency
|
|
|
|
|
system.cpu2.dcache.overall_avg_miss_latency 23154.049296 # average overall miss latency
|
|
|
|
|
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu2.dcache.writebacks 1 # number of writebacks
|
|
|
|
|
system.cpu2.dcache.ReadReq_mshr_hits 286 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu2.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu2.dcache.demand_mshr_hits 304 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu2.dcache.overall_mshr_hits 304 # number of overall MSHR hits
|
|
|
|
|
system.cpu2.dcache.ReadReq_mshr_misses 160 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu2.dcache.WriteReq_mshr_misses 104 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu2.dcache.SwapReq_mshr_misses 59 # number of SwapReq MSHR misses
|
|
|
|
|
system.cpu2.dcache.demand_mshr_misses 264 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu2.dcache.overall_mshr_misses 264 # number of overall MSHR misses
|
|
|
|
|
system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency 2394500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency 1669000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu2.dcache.SwapReq_mshr_miss_latency 1203500 # number of SwapReq MSHR miss cycles
|
|
|
|
|
system.cpu2.dcache.demand_mshr_miss_latency 4063500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu2.dcache.overall_mshr_miss_latency 4063500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003002 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate 0.002345 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu2.dcache.SwapReq_mshr_miss_rate 0.830986 # mshr miss rate for SwapReq accesses
|
|
|
|
|
system.cpu2.dcache.demand_mshr_miss_rate 0.002704 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu2.dcache.overall_mshr_miss_rate 0.002704 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 14965.625000 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 16048.076923 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 20398.305085 # average SwapReq mshr miss latency
|
|
|
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency 15392.045455 # average overall mshr miss latency
|
|
|
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency 15392.045455 # average overall mshr miss latency
|
|
|
|
|
system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu3.numCycles 198838 # number of cpu cycles simulated
|
|
|
|
|
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
|
|
|
system.cpu3.BPredUnit.lookups 46930 # Number of BP lookups
|
|
|
|
|
system.cpu3.BPredUnit.condPredicted 44609 # Number of conditional branches predicted
|
|
|
|
|
system.cpu3.BPredUnit.condIncorrect 1124 # Number of conditional branches incorrect
|
|
|
|
|
system.cpu3.BPredUnit.BTBLookups 46370 # Number of BTB lookups
|
|
|
|
|
system.cpu3.BPredUnit.BTBHits 44223 # Number of BTB hits
|
2009-04-21 17:37:50 +02:00
|
|
|
system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu3.BPredUnit.usedRAS 506 # Number of times the RAS was used to get a target.
|
|
|
|
|
system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
|
|
|
|
|
system.cpu3.fetch.icacheStallCycles 25370 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu3.fetch.Insts 254105 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu3.fetch.Branches 46930 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu3.fetch.predictedBranches 44729 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu3.fetch.Cycles 98091 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu3.fetch.SquashCycles 1197 # Number of cycles fetch has spent squashing
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu3.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu3.fetch.CacheLines 25370 # Number of cache lines fetched
|
|
|
|
|
system.cpu3.fetch.IcacheSquashes 235 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu3.fetch.rateDist::samples 195684 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu3.fetch.rateDist::mean 1.298548 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu3.fetch.rateDist::stdev 1.898359 # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu3.fetch.rateDist::0 97593 49.87% 49.87% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu3.fetch.rateDist::1 52035 26.59% 76.46% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu3.fetch.rateDist::2 9385 4.80% 81.26% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu3.fetch.rateDist::3 2730 1.40% 82.66% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu3.fetch.rateDist::4 1923 0.98% 83.64% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu3.fetch.rateDist::5 27840 14.23% 97.86% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu3.fetch.rateDist::6 2474 1.26% 99.13% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu3.fetch.rateDist::7 258 0.13% 99.26% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu3.fetch.rateDist::8 1446 0.74% 100.00% # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu3.fetch.rateDist::total 195684 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu3.fetch.branchRate 0.236021 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu3.fetch.rate 1.277950 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu3.decode.IdleCycles 66043 # Number of cycles decode is idle
|
|
|
|
|
system.cpu3.decode.BlockedCycles 23415 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu3.decode.RunCycles 90085 # Number of cycles decode is running
|
|
|
|
|
system.cpu3.decode.UnblockCycles 7606 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu3.decode.SquashCycles 1806 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu3.decode.DecodedInsts 252876 # Number of instructions handled by decode
|
|
|
|
|
system.cpu3.rename.SquashCycles 1806 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu3.rename.IdleCycles 66691 # Number of cycles rename is idle
|
|
|
|
|
system.cpu3.rename.BlockCycles 9403 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu3.rename.serializeStallCycles 13294 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu3.rename.RunCycles 97176 # Number of cycles rename is running
|
|
|
|
|
system.cpu3.rename.UnblockCycles 585 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu3.rename.RenamedInsts 251157 # Number of instructions processed by rename
|
|
|
|
|
system.cpu3.rename.IQFullEvents 61 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu3.rename.LSQFullEvents 39 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu3.rename.RenamedOperands 170213 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu3.rename.RenameLookups 465014 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu3.rename.int_rename_lookups 465014 # Number of integer rename lookups
|
|
|
|
|
system.cpu3.rename.CommittedMaps 162080 # Number of HB maps that are committed
|
|
|
|
|
system.cpu3.rename.UndoneMaps 8133 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu3.rename.serializingInsts 958 # count of serializing insts renamed
|
|
|
|
|
system.cpu3.rename.tempSerializingInsts 1016 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu3.rename.skidInsts 2718 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu3.memDep0.insertedLoads 69072 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu3.memDep0.insertedStores 30693 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu3.memDep0.conflictingLoads 34709 # Number of conflicting loads.
|
|
|
|
|
system.cpu3.memDep0.conflictingStores 26217 # Number of conflicting stores.
|
|
|
|
|
system.cpu3.iq.iqInstsAdded 203693 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu3.iq.iqNonSpecInstsAdded 9545 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu3.iq.iqInstsIssued 210364 # Number of instructions issued
|
2011-01-16 00:30:34 +01:00
|
|
|
system.cpu3.iq.iqSquashedInstsIssued 2 # Number of squashed instructions issued
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu3.iq.iqSquashedInstsExamined 6526 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu3.iq.iqSquashedOperandsExamined 6179 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu3.iq.iqSquashedNonSpecRemoved 647 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu3.iq.issued_per_cycle::samples 195684 # Number of insts issued each cycle
|
|
|
|
|
system.cpu3.iq.issued_per_cycle::mean 1.075019 # Number of insts issued each cycle
|
|
|
|
|
system.cpu3.iq.issued_per_cycle::stdev 1.244116 # Number of insts issued each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu3.iq.issued_per_cycle::0 94148 48.11% 48.11% # Number of insts issued each cycle
|
|
|
|
|
system.cpu3.iq.issued_per_cycle::1 34086 17.42% 65.53% # Number of insts issued each cycle
|
|
|
|
|
system.cpu3.iq.issued_per_cycle::2 32603 16.66% 82.19% # Number of insts issued each cycle
|
|
|
|
|
system.cpu3.iq.issued_per_cycle::3 30459 15.57% 97.76% # Number of insts issued each cycle
|
|
|
|
|
system.cpu3.iq.issued_per_cycle::4 2587 1.32% 99.08% # Number of insts issued each cycle
|
|
|
|
|
system.cpu3.iq.issued_per_cycle::5 1559 0.80% 99.88% # Number of insts issued each cycle
|
|
|
|
|
system.cpu3.iq.issued_per_cycle::6 152 0.08% 99.95% # Number of insts issued each cycle
|
|
|
|
|
system.cpu3.iq.issued_per_cycle::7 80 0.04% 99.99% # Number of insts issued each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu3.iq.issued_per_cycle::8 10 0.01% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu3.iq.issued_per_cycle::total 195684 # Number of insts issued each cycle
|
|
|
|
|
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::IntAlu 11 5.67% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::IntMult 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::IntDiv 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::FloatAdd 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::FloatCmp 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::FloatCvt 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::FloatMult 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::FloatDiv 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::SimdAdd 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::SimdAlu 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::SimdCmp 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::SimdCvt 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::SimdMisc 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::SimdMult 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::SimdShift 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::MemRead 52 26.80% 32.47% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::MemWrite 131 67.53% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::IntAlu 103392 49.15% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.15% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::MemRead 76648 36.44% 85.58% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::MemWrite 30324 14.42% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu3.iq.FU_type_0::total 210364 # Type of FU issued
|
|
|
|
|
system.cpu3.iq.rate 1.057967 # Inst issue rate
|
|
|
|
|
system.cpu3.iq.fu_busy_cnt 194 # FU busy when requested
|
|
|
|
|
system.cpu3.iq.fu_busy_rate 0.000922 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu3.iq.int_inst_queue_reads 616608 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu3.iq.int_inst_queue_writes 219792 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu3.iq.int_inst_queue_wakeup_accesses 209060 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu3.iq.int_alu_accesses 210558 # Number of integer alu accesses
|
|
|
|
|
system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
|
|
|
|
system.cpu3.iew.lsq.thread0.forwLoads 26077 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu3.iew.lsq.thread0.squashedLoads 1504 # Number of loads squashed
|
|
|
|
|
system.cpu3.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu3.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations
|
|
|
|
|
system.cpu3.iew.lsq.thread0.squashedStores 734 # Number of stores squashed
|
|
|
|
|
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
|
|
|
system.cpu3.iew.iewSquashCycles 1806 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu3.iew.iewBlockCycles 1713 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu3.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu3.iew.iewDispatchedInsts 248952 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu3.iew.iewDispSquashedInsts 576 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu3.iew.iewDispLoadInsts 69072 # Number of dispatched load instructions
|
|
|
|
|
system.cpu3.iew.iewDispStoreInsts 30693 # Number of dispatched store instructions
|
|
|
|
|
system.cpu3.iew.iewDispNonSpecInsts 930 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu3.iew.iewIQFullEvents 49 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu3.iew.memOrderViolationEvents 28 # Number of memory order violations
|
|
|
|
|
system.cpu3.iew.predictedTakenIncorrect 1047 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu3.iew.predictedNotTakenIncorrect 172 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu3.iew.branchMispredicts 1219 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu3.iew.iewExecutedInsts 209414 # Number of executed instructions
|
|
|
|
|
system.cpu3.iew.iewExecLoadInsts 68288 # Number of load instructions executed
|
|
|
|
|
system.cpu3.iew.iewExecSquashedInsts 950 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu3.iew.exec_swp 0 # number of swp insts executed
|
|
|
|
|
system.cpu3.iew.exec_nop 35714 # number of nop insts executed
|
|
|
|
|
system.cpu3.iew.exec_refs 98584 # number of memory reference insts executed
|
|
|
|
|
system.cpu3.iew.exec_branches 44648 # Number of branches executed
|
|
|
|
|
system.cpu3.iew.exec_stores 30296 # Number of stores executed
|
|
|
|
|
system.cpu3.iew.exec_rate 1.053189 # Inst execution rate
|
|
|
|
|
system.cpu3.iew.wb_sent 209192 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu3.iew.wb_count 209060 # cumulative count of insts written-back
|
|
|
|
|
system.cpu3.iew.wb_producers 114958 # num instructions producing a value
|
|
|
|
|
system.cpu3.iew.wb_consumers 118605 # num instructions consuming a value
|
|
|
|
|
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu3.iew.wb_rate 1.051409 # insts written-back per cycle
|
|
|
|
|
system.cpu3.iew.wb_fanout 0.969251 # average fanout of values written-back
|
|
|
|
|
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
|
|
|
system.cpu3.commit.commitCommittedInsts 240668 # The number of committed instructions
|
|
|
|
|
system.cpu3.commit.commitSquashedInsts 8282 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu3.commit.commitNonSpecStalls 8898 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu3.commit.branchMispredicts 1124 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu3.commit.committed_per_cycle::samples 187150 # Number of insts commited each cycle
|
|
|
|
|
system.cpu3.commit.committed_per_cycle::mean 1.285963 # Number of insts commited each cycle
|
|
|
|
|
system.cpu3.commit.committed_per_cycle::stdev 1.815684 # Number of insts commited each cycle
|
|
|
|
|
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu3.commit.committed_per_cycle::0 94628 50.56% 50.56% # Number of insts commited each cycle
|
|
|
|
|
system.cpu3.commit.committed_per_cycle::1 44931 24.01% 74.57% # Number of insts commited each cycle
|
|
|
|
|
system.cpu3.commit.committed_per_cycle::2 7495 4.00% 78.58% # Number of insts commited each cycle
|
|
|
|
|
system.cpu3.commit.committed_per_cycle::3 9690 5.18% 83.75% # Number of insts commited each cycle
|
|
|
|
|
system.cpu3.commit.committed_per_cycle::4 2458 1.31% 85.07% # Number of insts commited each cycle
|
|
|
|
|
system.cpu3.commit.committed_per_cycle::5 26940 14.39% 99.46% # Number of insts commited each cycle
|
|
|
|
|
system.cpu3.commit.committed_per_cycle::6 395 0.21% 99.67% # Number of insts commited each cycle
|
|
|
|
|
system.cpu3.commit.committed_per_cycle::7 129 0.07% 99.74% # Number of insts commited each cycle
|
|
|
|
|
system.cpu3.commit.committed_per_cycle::8 484 0.26% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
|
|
|
system.cpu3.commit.committed_per_cycle::total 187150 # Number of insts commited each cycle
|
|
|
|
|
system.cpu3.commit.count 240668 # Number of instructions committed
|
|
|
|
|
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu3.commit.refs 97527 # Number of memory references committed
|
|
|
|
|
system.cpu3.commit.loads 67568 # Number of loads committed
|
|
|
|
|
system.cpu3.commit.membars 8180 # Number of memory barriers committed
|
|
|
|
|
system.cpu3.commit.branches 44100 # Number of branches committed
|
|
|
|
|
system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu3.commit.int_insts 163745 # Number of committed integer instructions.
|
|
|
|
|
system.cpu3.commit.function_calls 322 # Number of function calls committed.
|
|
|
|
|
system.cpu3.commit.bw_lim_events 484 # number cycles where commit BW limit reached
|
|
|
|
|
system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
|
|
|
system.cpu3.rob.rob_reads 435029 # The number of ROB reads
|
|
|
|
|
system.cpu3.rob.rob_writes 499708 # The number of ROB writes
|
|
|
|
|
system.cpu3.timesIdled 278 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu3.idleCycles 3154 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu3.committedInsts 197602 # Number of Instructions Simulated
|
|
|
|
|
system.cpu3.committedInsts_total 197602 # Number of Instructions Simulated
|
|
|
|
|
system.cpu3.cpi 1.006255 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu3.cpi_total 1.006255 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu3.ipc 0.993784 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu3.ipc_total 0.993784 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu3.int_regfile_reads 353198 # number of integer regfile reads
|
|
|
|
|
system.cpu3.int_regfile_writes 164587 # number of integer regfile writes
|
|
|
|
|
system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
|
|
|
|
|
system.cpu3.misc_regfile_reads 100115 # number of misc regfile reads
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu3.misc_regfile_writes 646 # number of misc regfile writes
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu3.icache.replacements 334 # number of replacements
|
|
|
|
|
system.cpu3.icache.tagsinuse 83.539668 # Cycle average of tags in use
|
|
|
|
|
system.cpu3.icache.total_refs 24889 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu3.icache.sampled_refs 440 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu3.icache.avg_refs 56.565909 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu3.icache.occ_blocks::0 83.539668 # Average occupied blocks per context
|
|
|
|
|
system.cpu3.icache.occ_percent::0 0.163163 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu3.icache.ReadReq_hits 24889 # number of ReadReq hits
|
|
|
|
|
system.cpu3.icache.demand_hits 24889 # number of demand (read+write) hits
|
|
|
|
|
system.cpu3.icache.overall_hits 24889 # number of overall hits
|
|
|
|
|
system.cpu3.icache.ReadReq_misses 481 # number of ReadReq misses
|
|
|
|
|
system.cpu3.icache.demand_misses 481 # number of demand (read+write) misses
|
|
|
|
|
system.cpu3.icache.overall_misses 481 # number of overall misses
|
|
|
|
|
system.cpu3.icache.ReadReq_miss_latency 6766000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu3.icache.demand_miss_latency 6766000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu3.icache.overall_miss_latency 6766000 # number of overall miss cycles
|
|
|
|
|
system.cpu3.icache.ReadReq_accesses 25370 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu3.icache.demand_accesses 25370 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu3.icache.overall_accesses 25370 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu3.icache.ReadReq_miss_rate 0.018959 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu3.icache.demand_miss_rate 0.018959 # miss rate for demand accesses
|
|
|
|
|
system.cpu3.icache.overall_miss_rate 0.018959 # miss rate for overall accesses
|
|
|
|
|
system.cpu3.icache.ReadReq_avg_miss_latency 14066.528067 # average ReadReq miss latency
|
|
|
|
|
system.cpu3.icache.demand_avg_miss_latency 14066.528067 # average overall miss latency
|
|
|
|
|
system.cpu3.icache.overall_avg_miss_latency 14066.528067 # average overall miss latency
|
|
|
|
|
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu3.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu3.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu3.icache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu3.icache.ReadReq_mshr_hits 41 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu3.icache.demand_mshr_hits 41 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu3.icache.overall_mshr_hits 41 # number of overall MSHR hits
|
|
|
|
|
system.cpu3.icache.ReadReq_mshr_misses 440 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu3.icache.demand_mshr_misses 440 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu3.icache.overall_mshr_misses 440 # number of overall MSHR misses
|
|
|
|
|
system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency 5068000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu3.icache.demand_mshr_miss_latency 5068000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu3.icache.overall_mshr_miss_latency 5068000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate 0.017343 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu3.icache.demand_mshr_miss_rate 0.017343 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu3.icache.overall_mshr_miss_rate 0.017343 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11518.181818 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency 11518.181818 # average overall mshr miss latency
|
|
|
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency 11518.181818 # average overall mshr miss latency
|
|
|
|
|
system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu3.dcache.replacements 2 # number of replacements
|
|
|
|
|
system.cpu3.dcache.tagsinuse 16.417900 # Cycle average of tags in use
|
|
|
|
|
system.cpu3.dcache.total_refs 35718 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu3.dcache.avg_refs 1190.600000 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu3.dcache.occ_blocks::0 24.989455 # Average occupied blocks per context
|
|
|
|
|
system.cpu3.dcache.occ_blocks::1 -8.571555 # Average occupied blocks per context
|
|
|
|
|
system.cpu3.dcache.occ_percent::0 0.048808 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu3.dcache.occ_percent::1 -0.016741 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu3.dcache.ReadReq_hits 41747 # number of ReadReq hits
|
|
|
|
|
system.cpu3.dcache.WriteReq_hits 29763 # number of WriteReq hits
|
|
|
|
|
system.cpu3.dcache.SwapReq_hits 14 # number of SwapReq hits
|
|
|
|
|
system.cpu3.dcache.demand_hits 71510 # number of demand (read+write) hits
|
|
|
|
|
system.cpu3.dcache.overall_hits 71510 # number of overall hits
|
|
|
|
|
system.cpu3.dcache.ReadReq_misses 446 # number of ReadReq misses
|
|
|
|
|
system.cpu3.dcache.WriteReq_misses 124 # number of WriteReq misses
|
|
|
|
|
system.cpu3.dcache.SwapReq_misses 58 # number of SwapReq misses
|
|
|
|
|
system.cpu3.dcache.demand_misses 570 # number of demand (read+write) misses
|
|
|
|
|
system.cpu3.dcache.overall_misses 570 # number of overall misses
|
|
|
|
|
system.cpu3.dcache.ReadReq_miss_latency 9927500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu3.dcache.WriteReq_miss_latency 2778000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu3.dcache.SwapReq_miss_latency 1471000 # number of SwapReq miss cycles
|
|
|
|
|
system.cpu3.dcache.demand_miss_latency 12705500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu3.dcache.overall_miss_latency 12705500 # number of overall miss cycles
|
|
|
|
|
system.cpu3.dcache.ReadReq_accesses 42193 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu3.dcache.WriteReq_accesses 29887 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu3.dcache.SwapReq_accesses 72 # number of SwapReq accesses(hits+misses)
|
|
|
|
|
system.cpu3.dcache.demand_accesses 72080 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu3.dcache.overall_accesses 72080 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu3.dcache.ReadReq_miss_rate 0.010570 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu3.dcache.WriteReq_miss_rate 0.004149 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu3.dcache.SwapReq_miss_rate 0.805556 # miss rate for SwapReq accesses
|
|
|
|
|
system.cpu3.dcache.demand_miss_rate 0.007908 # miss rate for demand accesses
|
|
|
|
|
system.cpu3.dcache.overall_miss_rate 0.007908 # miss rate for overall accesses
|
|
|
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency 22258.968610 # average ReadReq miss latency
|
|
|
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency 22403.225806 # average WriteReq miss latency
|
|
|
|
|
system.cpu3.dcache.SwapReq_avg_miss_latency 25362.068966 # average SwapReq miss latency
|
|
|
|
|
system.cpu3.dcache.demand_avg_miss_latency 22290.350877 # average overall miss latency
|
|
|
|
|
system.cpu3.dcache.overall_avg_miss_latency 22290.350877 # average overall miss latency
|
|
|
|
|
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu3.dcache.writebacks 1 # number of writebacks
|
|
|
|
|
system.cpu3.dcache.ReadReq_mshr_hits 272 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu3.dcache.WriteReq_mshr_hits 19 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu3.dcache.demand_mshr_hits 291 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu3.dcache.overall_mshr_hits 291 # number of overall MSHR hits
|
|
|
|
|
system.cpu3.dcache.ReadReq_mshr_misses 174 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu3.dcache.WriteReq_mshr_misses 105 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu3.dcache.SwapReq_mshr_misses 58 # number of SwapReq MSHR misses
|
|
|
|
|
system.cpu3.dcache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu3.dcache.overall_mshr_misses 279 # number of overall MSHR misses
|
|
|
|
|
system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency 2494000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency 1504000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu3.dcache.SwapReq_mshr_miss_latency 1297000 # number of SwapReq MSHR miss cycles
|
|
|
|
|
system.cpu3.dcache.demand_mshr_miss_latency 3998000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu3.dcache.overall_mshr_miss_latency 3998000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate 0.004124 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate 0.003513 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu3.dcache.SwapReq_mshr_miss_rate 0.805556 # mshr miss rate for SwapReq accesses
|
|
|
|
|
system.cpu3.dcache.demand_mshr_miss_rate 0.003871 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu3.dcache.overall_mshr_miss_rate 0.003871 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 14333.333333 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 14323.809524 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 22362.068966 # average SwapReq mshr miss latency
|
|
|
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency 14329.749104 # average overall mshr miss latency
|
|
|
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency 14329.749104 # average overall mshr miss latency
|
|
|
|
|
system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.l2c.replacements 0 # number of replacements
|
|
|
|
|
system.l2c.tagsinuse 428.707153 # Cycle average of tags in use
|
|
|
|
|
system.l2c.total_refs 1488 # Total number of references to valid blocks.
|
|
|
|
|
system.l2c.sampled_refs 521 # Sample count of references to valid blocks.
|
|
|
|
|
system.l2c.avg_refs 2.856046 # Average number of references to valid blocks.
|
|
|
|
|
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.l2c.occ_blocks::0 348.158908 # Average occupied blocks per context
|
|
|
|
|
system.l2c.occ_blocks::1 9.356931 # Average occupied blocks per context
|
|
|
|
|
system.l2c.occ_blocks::2 63.539276 # Average occupied blocks per context
|
|
|
|
|
system.l2c.occ_blocks::3 2.442412 # Average occupied blocks per context
|
|
|
|
|
system.l2c.occ_blocks::4 5.209626 # Average occupied blocks per context
|
|
|
|
|
system.l2c.occ_percent::0 0.005312 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_percent::1 0.000143 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_percent::2 0.000970 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_percent::3 0.000037 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_percent::4 0.000079 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.ReadReq_hits::0 232 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::1 440 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::2 370 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::3 449 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::total 1491 # number of ReadReq hits
|
|
|
|
|
system.l2c.Writeback_hits::0 9 # number of Writeback hits
|
|
|
|
|
system.l2c.Writeback_hits::total 9 # number of Writeback hits
|
|
|
|
|
system.l2c.UpgradeReq_hits::0 3 # number of UpgradeReq hits
|
|
|
|
|
system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits
|
|
|
|
|
system.l2c.demand_hits::0 232 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::1 440 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::2 370 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::3 449 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::total 1491 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.overall_hits::0 232 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::1 440 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::2 370 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::3 449 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::total 1491 # number of overall hits
|
|
|
|
|
system.l2c.ReadReq_misses::0 425 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::1 15 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::2 82 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::3 4 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::total 526 # number of ReadReq misses
|
|
|
|
|
system.l2c.UpgradeReq_misses::0 26 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.UpgradeReq_misses::1 25 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.UpgradeReq_misses::2 23 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.UpgradeReq_misses::3 19 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.UpgradeReq_misses::total 93 # number of UpgradeReq misses
|
2010-08-17 14:14:03 +02:00
|
|
|
system.l2c.ReadExReq_misses::0 94 # number of ReadExReq misses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.ReadExReq_misses::1 12 # number of ReadExReq misses
|
2010-08-17 14:14:03 +02:00
|
|
|
system.l2c.ReadExReq_misses::2 13 # number of ReadExReq misses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.l2c.ReadExReq_misses::3 12 # number of ReadExReq misses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
|
2011-06-11 04:15:34 +02:00
|
|
|
system.l2c.demand_misses::0 519 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::1 27 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::2 95 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::3 16 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::total 657 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.overall_misses::0 519 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::1 27 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::2 95 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::3 16 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::total 657 # number of overall misses
|
|
|
|
|
system.l2c.ReadReq_miss_latency 27341000 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_miss_latency 156000 # number of UpgradeReq miss cycles
|
|
|
|
|
system.l2c.ReadExReq_miss_latency 6879000 # number of ReadExReq miss cycles
|
|
|
|
|
system.l2c.demand_miss_latency 34220000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.overall_miss_latency 34220000 # number of overall miss cycles
|
|
|
|
|
system.l2c.ReadReq_accesses::0 657 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::1 455 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::2 452 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::3 453 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::total 2017 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses)
|
2010-10-31 08:07:48 +01:00
|
|
|
system.l2c.UpgradeReq_accesses::0 29 # number of UpgradeReq accesses(hits+misses)
|
2011-06-11 04:15:34 +02:00
|
|
|
system.l2c.UpgradeReq_accesses::1 25 # number of UpgradeReq accesses(hits+misses)
|
2011-01-16 00:30:34 +01:00
|
|
|
system.l2c.UpgradeReq_accesses::2 23 # number of UpgradeReq accesses(hits+misses)
|
2011-06-11 04:15:34 +02:00
|
|
|
system.l2c.UpgradeReq_accesses::3 19 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.UpgradeReq_accesses::total 96 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::0 94 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::2 13 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.demand_accesses::0 751 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::1 467 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::2 465 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::3 465 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::total 2148 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::0 751 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::1 467 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::2 465 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::3 465 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::total 2148 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::0 0.646880 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::1 0.032967 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::2 0.181416 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::3 0.008830 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::total 0.870093 # miss rate for ReadReq accesses
|
2010-10-31 08:07:48 +01:00
|
|
|
system.l2c.UpgradeReq_miss_rate::0 0.896552 # miss rate for UpgradeReq accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses
|
2010-10-31 08:07:48 +01:00
|
|
|
system.l2c.UpgradeReq_miss_rate::total 3.896552 # miss rate for UpgradeReq accesses
|
2011-06-11 04:15:34 +02:00
|
|
|
system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.demand_miss_rate::0 0.691079 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::1 0.057816 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::2 0.204301 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::3 0.034409 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::total 0.987604 # miss rate for demand accesses
|
|
|
|
|
system.l2c.overall_miss_rate::0 0.691079 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::1 0.057816 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::2 0.204301 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::3 0.034409 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::total 0.987604 # miss rate for overall accesses
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::0 64331.764706 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::1 1822733.333333 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::2 333426.829268 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::3 6835250 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::total 9055741.927308 # average ReadReq miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::0 6000 # average UpgradeReq miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::1 6240 # average UpgradeReq miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::2 6782.608696 # average UpgradeReq miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::3 8210.526316 # average UpgradeReq miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 27233.135011 # average UpgradeReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::0 73180.851064 # average ReadExReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::1 573250 # average ReadExReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::2 529153.846154 # average ReadExReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::3 573250 # average ReadExReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::total 1748834.697218 # average ReadExReq miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::0 65934.489403 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::1 1267407.407407 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::2 360210.526316 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::3 2138750 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::total 3832302.423126 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::0 65934.489403 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::1 1267407.407407 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::2 360210.526316 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::3 2138750 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::total 3832302.423126 # average overall miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-06-11 04:15:34 +02:00
|
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
2009-04-21 17:37:50 +02:00
|
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
2011-06-11 04:15:34 +02:00
|
|
|
system.l2c.writebacks 0 # number of writebacks
|
|
|
|
|
system.l2c.ReadReq_mshr_hits 7 # number of ReadReq MSHR hits
|
2010-10-31 08:07:48 +01:00
|
|
|
system.l2c.demand_mshr_hits 7 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.l2c.overall_mshr_hits 7 # number of overall MSHR hits
|
2011-06-11 04:15:34 +02:00
|
|
|
system.l2c.ReadReq_mshr_misses 519 # number of ReadReq MSHR misses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_misses 93 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.l2c.ReadExReq_mshr_misses 131 # number of ReadExReq MSHR misses
|
|
|
|
|
system.l2c.demand_mshr_misses 650 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.l2c.overall_mshr_misses 650 # number of overall MSHR misses
|
2009-04-21 17:37:50 +02:00
|
|
|
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-06-11 04:15:34 +02:00
|
|
|
system.l2c.ReadReq_mshr_miss_latency 20754000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_latency 3720500 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_latency 5279000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_latency 26033000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_latency 26033000 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::0 0.789954 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::1 1.140659 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::2 1.148230 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::3 1.145695 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::total 4.224539 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::0 3.206897 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::1 3.720000 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::2 4.043478 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::3 4.894737 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 15.865112 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::0 1.393617 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::1 10.916667 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::2 10.076923 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::3 10.916667 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 33.303873 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::0 0.865513 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::1 1.391863 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::2 1.397849 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::3 1.397849 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::total 5.053075 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::0 0.865513 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::1 1.391863 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::2 1.397849 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::3 1.397849 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::total 5.053075 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency 39988.439306 # average ReadReq mshr miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.376344 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency 40297.709924 # average ReadExReq mshr miss latency
|
|
|
|
|
system.l2c.demand_avg_mshr_miss_latency 40050.769231 # average overall mshr miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_miss_latency 40050.769231 # average overall mshr miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
2009-04-21 17:37:50 +02:00
|
|
|
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-06-11 04:15:34 +02:00
|
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
2009-04-21 17:37:50 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
