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gem5/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt

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X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
---------- Begin Simulation Statistics ----------
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
sim_seconds 0.144463 # Number of seconds simulated
sim_ticks 144463317000 # Number of ticks simulated
final_tick 144463317000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
host_inst_rate 81167 # Simulator instruction rate (inst/s)
host_op_rate 136043 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 88782348 # Simulator tick rate (ticks/s)
host_mem_usage 282908 # Number of bytes of host memory used
host_seconds 1627.16 # Real time elapsed on the host
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
sim_insts 132071192 # Number of instructions simulated
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
sim_ops 221363384 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytes_read::cpu.inst 217088 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 125568 # Number of bytes read from this memory
system.physmem.bytes_read::total 342656 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 217088 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 217088 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3392 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1962 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5354 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1502721 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 869203 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2371924 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1502721 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1502721 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1502721 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 869203 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2371924 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 5354 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 5354 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 342656 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 342656 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 163 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 289 # Per bank write bursts
system.physmem.perBankRdBursts::1 357 # Per bank write bursts
system.physmem.perBankRdBursts::2 453 # Per bank write bursts
system.physmem.perBankRdBursts::3 356 # Per bank write bursts
system.physmem.perBankRdBursts::4 332 # Per bank write bursts
system.physmem.perBankRdBursts::5 326 # Per bank write bursts
system.physmem.perBankRdBursts::6 402 # Per bank write bursts
system.physmem.perBankRdBursts::7 377 # Per bank write bursts
system.physmem.perBankRdBursts::8 341 # Per bank write bursts
system.physmem.perBankRdBursts::9 276 # Per bank write bursts
system.physmem.perBankRdBursts::10 232 # Per bank write bursts
system.physmem.perBankRdBursts::11 277 # Per bank write bursts
system.physmem.perBankRdBursts::12 205 # Per bank write bursts
system.physmem.perBankRdBursts::13 465 # Per bank write bursts
system.physmem.perBankRdBursts::14 384 # Per bank write bursts
system.physmem.perBankRdBursts::15 282 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 144463266500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 5354 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 4302 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 874 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 155 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesPerActivate::samples 957 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 353.103448 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 172.307957 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 612.115437 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64 385 40.23% 40.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128 164 17.14% 57.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192 81 8.46% 65.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256 46 4.81% 70.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320 43 4.49% 75.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384 20 2.09% 77.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448 26 2.72% 79.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512 19 1.99% 81.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576 17 1.78% 83.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640 26 2.72% 86.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704 27 2.82% 89.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768 7 0.73% 89.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832 7 0.73% 90.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896 7 0.73% 91.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960 3 0.31% 91.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024 5 0.52% 92.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088 6 0.63% 92.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152 6 0.63% 93.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216 4 0.42% 93.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280 2 0.21% 94.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344 2 0.21% 94.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408 3 0.31% 94.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472 7 0.73% 95.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536 1 0.10% 95.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600 5 0.52% 96.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664 4 0.42% 96.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728 2 0.21% 96.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792 2 0.21% 96.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856 2 0.21% 97.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920 3 0.31% 97.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984 2 0.21% 97.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112 1 0.10% 97.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176 1 0.10% 97.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240 1 0.10% 97.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304 1 0.10% 98.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368 1 0.10% 98.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432 2 0.21% 98.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496 1 0.10% 98.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816 2 0.21% 98.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880 3 0.31% 98.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072 1 0.10% 99.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328 1 0.10% 99.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456 1 0.10% 99.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584 1 0.10% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160 1 0.10% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352 1 0.10% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736 1 0.10% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312 1 0.10% 99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696 1 0.10% 99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952 1 0.10% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 957 # Bytes accessed per row activation
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.totQLat 28783000 # Total ticks spent queuing
system.physmem.totMemAccLat 137846750 # Total ticks spent from burst creation until serviced by the DRAM
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.totBusLat 26770000 # Total ticks spent in databus transfers
system.physmem.totBankLat 82293750 # Total ticks spent accessing banks
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.avgQLat 5375.98 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBankLat 15370.52 # Average bank access latency per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.avgMemAccLat 25746.50 # Average memory access latency per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgRdBW 2.37 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
x86, regressions: updates stats This is due to op class, function call, walker patches.
2013-05-21 18:41:27 +02:00
system.physmem.busUtil 0.02 # Data bus utilization in percentage
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 4397 # Number of row buffer hits during reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readRowHitRate 82.13 # Row buffer hit rate for reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgGap 26982306.03 # Average gap between requests
system.physmem.pageHitRate 82.13 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput 2371924 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 3822 # Transaction distribution
system.membus.trans_dist::ReadResp 3822 # Transaction distribution
system.membus.trans_dist::UpgradeReq 163 # Transaction distribution
system.membus.trans_dist::UpgradeResp 163 # Transaction distribution
system.membus.trans_dist::ReadExReq 1532 # Transaction distribution
system.membus.trans_dist::ReadExResp 1532 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11034 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11034 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 11034 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342656 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342656 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 342656 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 342656 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.membus.reqLayer0.occupancy 6950000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.membus.respLayer1.occupancy 50662837 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.branchPred.lookups 18648233 # Number of BP lookups
system.cpu.branchPred.condPredicted 18648233 # Number of conditional branches predicted
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.branchPred.condIncorrect 1490176 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 11407549 # Number of BTB lookups
system.cpu.branchPred.BTBHits 10790529 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.branchPred.BTBHitPct 94.591126 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1320367 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 22841 # Number of incorrect RAS predictions.
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.workload.num_syscalls 400 # Number of system calls
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.numCycles 289221873 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.fetch.icacheStallCycles 23458043 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 206724218 # Number of instructions fetch has processed
system.cpu.fetch.Branches 18648233 # Number of branches that fetch encountered
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.fetch.predictedBranches 12110896 # Number of branches that fetch has predicted taken
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.fetch.Cycles 54209097 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 15518774 # Number of cycles fetch has spent squashing
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.fetch.BlockedCycles 178161359 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1571 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 9111 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.fetch.CacheLines 22353211 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 224061 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 269612469 # Number of instructions fetched each cycle (Total)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.fetch.rateDist::mean 1.268180 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.756310 # Number of instructions fetched each cycle (Total)
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.fetch.rateDist::0 216842563 80.43% 80.43% # Number of instructions fetched each cycle (Total)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.fetch.rateDist::1 2848142 1.06% 81.48% # Number of instructions fetched each cycle (Total)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.fetch.rateDist::2 2312055 0.86% 82.34% # Number of instructions fetched each cycle (Total)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.fetch.rateDist::3 2633842 0.98% 83.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 3218714 1.19% 84.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 3388946 1.26% 85.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 3831195 1.42% 87.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 2559437 0.95% 88.14% # Number of instructions fetched each cycle (Total)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.fetch.rateDist::8 31977575 11.86% 100.00% # Number of instructions fetched each cycle (Total)
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.fetch.rateDist::total 269612469 # Number of instructions fetched each cycle (Total)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.fetch.branchRate 0.064477 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.714760 # Number of inst fetches per cycle
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.decode.IdleCycles 36899359 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 167130004 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 41545229 # Number of cycles decode is running
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.decode.UnblockCycles 10264627 # Number of cycles decode is unblocking
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.decode.SquashCycles 13773250 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 336001462 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 13773250 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 44972487 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 116686698 # Number of cycles rename is blocking
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.rename.serializeStallCycles 32545 # count of cycles rename stalled for serializing inst
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.rename.RunCycles 42701689 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 51445800 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 329633775 # Number of instructions processed by rename
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.rename.ROBFullEvents 10827 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 26123597 # Number of times rename has blocked due to IQ full
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.rename.LSQFullEvents 22730549 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 382342090 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 917586713 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 605878272 # Number of integer rename lookups
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.rename.fp_rename_lookups 4127660 # Number of floating rename lookups
stats: Bump x86 stats This patch bumps the x86 stats to reflect the recent fixes.
2013-06-24 20:17:22 +02:00
system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.rename.UndoneMaps 122912640 # Number of HB maps that are undone due to squashing
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.rename.serializingInsts 2051 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2042 # count of temporary serializing insts renamed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.rename.skidInsts 105140052 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 84507276 # Number of loads inserted to the mem dependence unit.
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.memDep0.insertedStores 30107186 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 58355212 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 18979888 # Number of conflicting stores.
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iq.iqInstsAdded 322730905 # Number of instructions added to the IQ (excludes non-spec)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iq.iqNonSpecInstsAdded 4069 # Number of non-speculative instructions added to the IQ
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iq.iqInstsIssued 260501994 # Number of instructions issued
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iq.iqSquashedInstsIssued 116055 # Number of squashed instructions issued
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iq.iqSquashedInstsExamined 100987191 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 210203655 # Number of squashed operands that are examined and possibly removed from graph
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iq.iqSquashedNonSpecRemoved 2824 # Number of squashed non-spec instructions that were removed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iq.issued_per_cycle::samples 269612469 # Number of insts issued each cycle
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iq.issued_per_cycle::mean 0.966209 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.343680 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iq.issued_per_cycle::0 143429912 53.20% 53.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 55567346 20.61% 73.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 34108148 12.65% 86.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 19044980 7.06% 93.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 10887634 4.04% 97.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 4152283 1.54% 99.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1816697 0.67% 99.78% # Number of insts issued each cycle
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iq.issued_per_cycle::7 472473 0.18% 99.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 132996 0.05% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iq.issued_per_cycle::total 269612469 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iq.fu_full::IntAlu 130605 4.82% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.82% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2279077 84.03% 88.85% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 302412 11.15% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iq.FU_type_0::No_OpClass 1210810 0.46% 0.46% # Type of FU issued
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iq.FU_type_0::IntAlu 162055944 62.21% 62.67% # Type of FU issued
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iq.FU_type_0::IntMult 789191 0.30% 62.98% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 7035649 2.70% 65.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 1445882 0.56% 66.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.23% # Type of FU issued
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iq.FU_type_0::MemRead 65414513 25.11% 91.34% # Type of FU issued
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iq.FU_type_0::MemWrite 22550005 8.66% 100.00% # Type of FU issued
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iq.FU_type_0::total 260501994 # Type of FU issued
system.cpu.iq.rate 0.900699 # Inst issue rate
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iq.fu_busy_cnt 2712094 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.010411 # FU busy rate (busy events/executed inst)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iq.int_inst_queue_reads 788557578 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 420384868 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 255147075 # Number of integer instruction queue wakeup accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iq.fp_inst_queue_reads 4887028 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 3615221 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2349564 # Number of floating instruction queue wakeup accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iq.int_alu_accesses 259544026 # Number of integer alu accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iq.fp_alu_accesses 2459252 # Number of floating point alu accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iew.lsq.thread0.forwLoads 18903382 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 27857689 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 25992 # Number of memory responses ignored because the instruction is squashed
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iew.lsq.thread0.memOrderViolation 283319 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 9591469 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 49752 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iew.iewSquashCycles 13773250 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 85040639 # Number of cycles IEW is blocking
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iew.iewUnblockCycles 5471570 # Number of cycles IEW is unblocking
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iew.iewDispatchedInsts 322734974 # Number of instructions dispatched to IQ
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iew.iewDispSquashedInsts 133239 # Number of squashed instructions skipped by dispatch
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iew.iewDispLoadInsts 84507276 # Number of dispatched load instructions
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iew.iewDispStoreInsts 30107186 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1979 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2708196 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 13910 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 283319 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 639398 # Number of branches that were predicted taken incorrectly
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iew.predictedNotTakenIncorrect 901242 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1540640 # Number of branch mispredicts detected at execute
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iew.iewExecutedInsts 258732431 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 64645019 # Number of load instructions executed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iew.iewExecSquashedInsts 1769563 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iew.exec_refs 86992194 # number of memory reference insts executed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iew.exec_branches 14265859 # Number of branches executed
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iew.exec_stores 22347175 # Number of stores executed
system.cpu.iew.exec_rate 0.894581 # Inst execution rate
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iew.wb_sent 258096693 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 257496639 # cumulative count of insts written-back
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iew.wb_producers 205928299 # num instructions producing a value
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iew.wb_consumers 369130530 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iew.wb_rate 0.890308 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.557874 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.commit.commitSquashedInsts 101448840 # The number of squashed insts skipped by commit
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.commit.branchMispredicts 1491529 # The number of times a branch was mispredicted
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.commit.committed_per_cycle::samples 255839219 # Number of insts commited each cycle
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.commit.committed_per_cycle::mean 0.865244 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.654327 # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.commit.committed_per_cycle::0 156486617 61.17% 61.17% # Number of insts commited each cycle
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.commit.committed_per_cycle::1 57197635 22.36% 83.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 14067876 5.50% 89.02% # Number of insts commited each cycle
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.commit.committed_per_cycle::3 12054068 4.71% 93.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 4176261 1.63% 95.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 2944387 1.15% 96.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 904564 0.35% 96.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1049058 0.41% 97.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 6958753 2.72% 100.00% # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.commit.committed_per_cycle::total 255839219 # Number of insts commited each cycle
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.committedInsts 132071192 # Number of instructions committed
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.commit.refs 77165304 # Number of memory references committed
system.cpu.commit.loads 56649587 # Number of loads committed
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.membars 0 # Number of memory barriers committed
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.branches 12326938 # Number of branches committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
test: update stats Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses.
2013-10-16 16:44:12 +02:00
system.cpu.commit.int_insts 219019985 # Number of committed integer instructions.
x86, regressions: updates stats This is due to op class, function call, walker patches.
2013-05-21 18:41:27 +02:00
system.cpu.commit.function_calls 797818 # Number of function calls committed.
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.commit.bw_lim_events 6958753 # number cycles where commit BW limit reached
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.rob.rob_reads 571692690 # The number of ROB reads
system.cpu.rob.rob_writes 659422914 # The number of ROB writes
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.timesIdled 5933064 # Number of times that the entire CPU went into an idle state and unscheduled itself
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.idleCycles 19609404 # Total number of cycles that the CPU has spent unscheduled due to idling
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts 132071192 # Number of Instructions Simulated
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.cpi 2.189894 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.189894 # CPI: Total CPI of All Threads
system.cpu.ipc 0.456643 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.456643 # IPC: Total IPC of All Threads
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.int_regfile_reads 451224153 # number of integer regfile reads
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.int_regfile_writes 233957254 # number of integer regfile writes
system.cpu.fp_regfile_reads 3215586 # number of floating regfile reads
system.cpu.fp_regfile_writes 2009211 # number of floating regfile writes
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.cc_regfile_reads 102809513 # number of cc regfile reads
system.cpu.cc_regfile_writes 59799383 # number of cc regfile writes
system.cpu.misc_regfile_reads 133324417 # number of misc regfile reads
stats: Bump x86 stats This patch bumps the x86 stats to reflect the recent fixes.
2013-06-24 20:17:22 +02:00
system.cpu.misc_regfile_writes 1689 # number of misc regfile writes
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.toL2Bus.throughput 3898568 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 7250 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 7248 # Transaction distribution
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.toL2Bus.trans_dist::UpgradeReq 163 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 163 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1539 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1539 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13403 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4348 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 17751 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 423616 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129088 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 552704 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 552704 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 10496 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 4495500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 10760250 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 3467413 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.icache.tags.replacements 4653 # number of replacements
system.cpu.icache.tags.tagsinuse 1619.938452 # Cycle average of tags in use
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.icache.tags.total_refs 22344300 # Total number of references to valid blocks.
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.icache.tags.sampled_refs 6620 # Sample count of references to valid blocks.
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.icache.tags.avg_refs 3375.271903 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 1619.938452 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.790986 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.790986 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 1967 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 767 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 797 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.960449 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 44713203 # Number of tag accesses
system.cpu.icache.tags.data_accesses 44713203 # Number of data accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.icache.ReadReq_hits::cpu.inst 22344300 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 22344300 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 22344300 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 22344300 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 22344300 # number of overall hits
system.cpu.icache.overall_hits::total 22344300 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 8910 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 8910 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 8910 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 8910 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 8910 # number of overall misses
system.cpu.icache.overall_misses::total 8910 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 368144999 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 368144999 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 368144999 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 368144999 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 368144999 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 368144999 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 22353210 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 22353210 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 22353210 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 22353210 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 22353210 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 22353210 # number of overall (read+write) accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000399 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000399 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000399 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000399 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000399 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000399 # miss rate for overall accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41318.181706 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 41318.181706 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 41318.181706 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 41318.181706 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 41318.181706 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 41318.181706 # average overall miss latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 877 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 43.850000 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2126 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 2126 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 2126 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 2126 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 2126 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 2126 # number of overall MSHR hits
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6784 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 6784 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 6784 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 6784 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 6784 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 6784 # number of overall MSHR misses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 271638749 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 271638749 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 271638749 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 271638749 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 271638749 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 271638749 # number of overall MSHR miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000303 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000303 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000303 # mshr miss rate for overall accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40041.089180 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40041.089180 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40041.089180 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 40041.089180 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40041.089180 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 40041.089180 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.tags.tagsinuse 2543.926920 # Cycle average of tags in use
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.tags.total_refs 3266 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 3826 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.853633 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 1.725256 # Average occupied blocks per requestor
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2230.334814 # Average occupied blocks per requestor
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.tags.occ_blocks::cpu.data 311.866849 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000053 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068064 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.009517 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.077634 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3826 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 876 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 145 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2560 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.116760 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 75773 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 75773 # Number of data accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadReq_hits::cpu.inst 3227 # number of ReadReq hits
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.l2cache.ReadReq_hits::cpu.data 36 # number of ReadReq hits
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadReq_hits::total 3263 # number of ReadReq hits
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.demand_hits::cpu.inst 3227 # number of demand (read+write) hits
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.l2cache.demand_hits::cpu.data 43 # number of demand (read+write) hits
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.demand_hits::total 3270 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 3227 # number of overall hits
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.l2cache.overall_hits::cpu.data 43 # number of overall hits
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.overall_hits::total 3270 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3393 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 430 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 3823 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 163 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 163 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 1532 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1532 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3393 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1962 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 5355 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3393 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1962 # number of overall misses
system.cpu.l2cache.overall_misses::total 5355 # number of overall misses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 232417000 # number of ReadReq miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32755500 # number of ReadReq miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.ReadReq_miss_latency::total 265172500 # number of ReadReq miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104434000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 104434000 # number of ReadExReq miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.inst 232417000 # number of demand (read+write) miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.data 137189500 # number of demand (read+write) miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.demand_miss_latency::total 369606500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 232417000 # number of overall miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.overall_miss_latency::cpu.data 137189500 # number of overall miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.overall_miss_latency::total 369606500 # number of overall miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadReq_accesses::cpu.inst 6620 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 466 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7086 # number of ReadReq accesses(hits+misses)
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 163 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 163 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1539 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1539 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 6620 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2005 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 8625 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 6620 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2005 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 8625 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.512538 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.922747 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.539515 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995452 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.995452 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.512538 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.978554 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.620870 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.512538 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.978554 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.620870 # miss rate for overall accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68498.968464 # average ReadReq miss latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76175.581395 # average ReadReq miss latency
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69362.411719 # average ReadReq miss latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68168.407311 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68168.407311 # average ReadExReq miss latency
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68498.968464 # average overall miss latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69923.292559 # average overall miss latency
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.demand_avg_miss_latency::total 69020.821662 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68498.968464 # average overall miss latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69923.292559 # average overall miss latency
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.overall_avg_miss_latency::total 69020.821662 # average overall miss latency
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3393 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 430 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 3823 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 163 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 163 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1532 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1532 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3393 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1962 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 5355 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3393 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1962 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 5355 # number of overall MSHR misses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 189899500 # number of ReadReq MSHR miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27426500 # number of ReadReq MSHR miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 217326000 # number of ReadReq MSHR miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1630163 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1630163 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 84874000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 84874000 # number of ReadExReq MSHR miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 189899500 # number of demand (read+write) MSHR miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 112300500 # number of demand (read+write) MSHR miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::total 302200000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 189899500 # number of overall MSHR miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 112300500 # number of overall MSHR miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::total 302200000 # number of overall MSHR miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.922747 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.539515 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995452 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995452 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.978554 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.620870 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.978554 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.620870 # mshr miss rate for overall accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55968.022399 # average ReadReq mshr miss latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63782.558140 # average ReadReq mshr miss latency
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56846.978812 # average ReadReq mshr miss latency
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55400.783290 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55400.783290 # average ReadExReq mshr miss latency
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55968.022399 # average overall mshr miss latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56433.239963 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55968.022399 # average overall mshr miss latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56433.239963 # average overall mshr miss latency
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.tags.replacements 57 # number of replacements
system.cpu.dcache.tags.tagsinuse 1438.861304 # Cycle average of tags in use
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.dcache.tags.total_refs 66102356 # Total number of references to valid blocks.
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.tags.sampled_refs 2004 # Sample count of references to valid blocks.
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.dcache.tags.avg_refs 32985.207585 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 1438.861304 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.351284 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.351284 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 1947 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 432 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1395 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.475342 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 132211530 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 132211530 # Number of data accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.dcache.ReadReq_hits::cpu.data 45588097 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 45588097 # number of ReadReq hits
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.WriteReq_hits::cpu.data 20514029 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 20514029 # number of WriteReq hits
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.dcache.demand_hits::cpu.data 66102126 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 66102126 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 66102126 # number of overall hits
system.cpu.dcache.overall_hits::total 66102126 # number of overall hits
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.ReadReq_misses::cpu.data 935 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 935 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1702 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1702 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2637 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2637 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2637 # number of overall misses
system.cpu.dcache.overall_misses::total 2637 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 62763567 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 62763567 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 113907163 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 113907163 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 176670730 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 176670730 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 176670730 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 176670730 # number of overall miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.dcache.ReadReq_accesses::cpu.data 45589032 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 45589032 # number of ReadReq accesses(hits+misses)
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.dcache.demand_accesses::cpu.data 66104763 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 66104763 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 66104763 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 66104763 # number of overall (read+write) accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000083 # miss rate for WriteReq accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67126.809626 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 67126.809626 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66925.477673 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 66925.477673 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 66996.863860 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 66996.863860 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 66996.863860 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 66996.863860 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 77 # average number of cycles each access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.dcache.writebacks::writebacks 13 # number of writebacks
system.cpu.dcache.writebacks::total 13 # number of writebacks
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 468 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 468 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 469 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 469 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 469 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 469 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 467 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1701 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1701 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2168 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2168 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2168 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2168 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33590500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 33590500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109769587 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 109769587 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 143360087 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 143360087 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 143360087 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 143360087 # number of overall MSHR miss cycles
x86, regressions: updates stats This is due to op class, function call, walker patches.
2013-05-21 18:41:27 +02:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000083 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000083 # mshr miss rate for WriteReq accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71928.265525 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71928.265525 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64532.385068 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64532.385068 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66125.501384 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66125.501384 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66125.501384 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66125.501384 # average overall mshr miss latency
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
---------- End Simulation Statistics ----------
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