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gem5/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt

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add SMT hello world test - 2 threads --HG-- extra : convert_revision : 54cb19d1325295895b6f0b992499bbb0216b45df
2006-10-06 10:23:27 +02:00
---------- Begin Simulation Statistics ----------
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
sim_seconds 0.000024 # Number of seconds simulated
sim_ticks 23754500 # Number of ticks simulated
final_tick 23754500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
add SMT hello world test - 2 threads --HG-- extra : convert_revision : 54cb19d1325295895b6f0b992499bbb0216b45df
2006-10-06 10:23:27 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
host_inst_rate 70868 # Simulator instruction rate (inst/s)
host_op_rate 70863 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 132078042 # Simulator tick rate (ticks/s)
host_mem_usage 294344 # Number of bytes of host memory used
host_seconds 0.18 # Real time elapsed on the host
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
sim_insts 12744 # Number of instructions simulated
sim_ops 12744 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bytes_read::cpu.inst 40064 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 22336 # Number of bytes read from this memory
system.physmem.bytes_read::total 62400 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 40064 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 40064 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 626 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 349 # Number of read requests responded to by this memory
system.physmem.num_reads::total 975 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1686585700 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 940284999 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2626870698 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1686585700 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1686585700 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1686585700 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 940284999 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2626870698 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 975 # Number of read requests accepted
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writeReqs 0 # Number of write requests accepted
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.readBursts 975 # Number of DRAM read bursts, including those serviced by the write queue
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bytesReadDRAM 62400 # Total number of bytes read from DRAM
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bytesReadSys 62400 # Total read bytes from the system interface side
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::0 83 # Per bank write bursts
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::1 151 # Per bank write bursts
system.physmem.perBankRdBursts::2 78 # Per bank write bursts
system.physmem.perBankRdBursts::3 58 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::4 88 # Per bank write bursts
system.physmem.perBankRdBursts::5 49 # Per bank write bursts
system.physmem.perBankRdBursts::6 32 # Per bank write bursts
system.physmem.perBankRdBursts::7 49 # Per bank write bursts
system.physmem.perBankRdBursts::8 41 # Per bank write bursts
system.physmem.perBankRdBursts::9 38 # Per bank write bursts
system.physmem.perBankRdBursts::10 30 # Per bank write bursts
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::11 34 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::12 15 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::13 122 # Per bank write bursts
system.physmem.perBankRdBursts::14 70 # Per bank write bursts
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::15 37 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.totGap 23342000 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.readPktSize::6 975 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.rdQLenPdf::0 328 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 345 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 183 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 80 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 29 # What read queue length does an incoming req see
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.rdQLenPdf::5 10 # What read queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bytesPerActivate::samples 211 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 295.431280 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 188.087836 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 290.004628 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 69 32.70% 32.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 56 26.54% 59.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 25 11.85% 71.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 14 6.64% 77.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 15 7.11% 84.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 9 4.27% 89.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 4 1.90% 91.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 6 2.84% 93.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 13 6.16% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 211 # Bytes accessed per row activation
system.physmem.totQLat 12504500 # Total ticks spent queuing
system.physmem.totMemAccLat 30785750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 4875000 # Total ticks spent in databus transfers
system.physmem.avgQLat 12825.13 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.avgMemAccLat 31575.13 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2626.87 # Average DRAM read bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.avgRdBWSys 2626.87 # Average system read bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.busUtil 20.52 # Data bus utilization in percentage
system.physmem.busUtilRead 20.52 # Data bus utilization in percentage for reads
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.avgRdQLen 2.40 # Average read queue length when enqueuing
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.readRowHits 763 # Number of row buffer hits during reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.readRowHitRate 78.26 # Row buffer hit rate for reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.avgGap 23940.51 # Average gap between requests
system.physmem.pageHitRate 78.26 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 899640 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 490875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 4578600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 16058610 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 84750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 23638155 # Total energy per rank (pJ)
system.physmem_0.averagePower 1000.821593 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 44000 # Time in different power states
system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 22808500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 695520 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 379500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 3018600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 15908130 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 216750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 21744180 # Total energy per rank (pJ)
system.physmem_1.averagePower 920.632125 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 278750 # Time in different power states
system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 22573750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 7608 # Number of BP lookups
system.cpu.branchPred.condPredicted 4258 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1618 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 5646 # Number of BTB lookups
system.cpu.branchPred.BTBHits 865 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.branchPred.BTBHitPct 15.320581 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1051 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 77 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.read_hits 5192 # DTB read hits
system.cpu.dtb.read_misses 102 # DTB read misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dtb.read_acv 0 # DTB read access violations
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.read_accesses 5294 # DTB read accesses
system.cpu.dtb.write_hits 2108 # DTB write hits
system.cpu.dtb.write_misses 66 # DTB write misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dtb.write_acv 0 # DTB write access violations
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.write_accesses 2174 # DTB write accesses
system.cpu.dtb.data_hits 7300 # DTB hits
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dtb.data_misses 168 # DTB misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dtb.data_acv 0 # DTB access violations
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.data_accesses 7468 # DTB accesses
system.cpu.itb.fetch_hits 5663 # ITB hits
system.cpu.itb.fetch_misses 57 # ITB misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.itb.fetch_acv 0 # ITB acv
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.itb.fetch_accesses 5720 # ITB accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload0.num_syscalls 17 # Number of system calls
system.cpu.workload1.num_syscalls 17 # Number of system calls
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.numCycles 47510 # number of cpu cycles simulated
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.fetch.icacheStallCycles 1451 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 41889 # Number of instructions fetch has processed
system.cpu.fetch.Branches 7608 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 1916 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 11137 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1697 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 556 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 5663 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 846 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 28570 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.466188 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.843743 # Number of instructions fetched each cycle (Total)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.fetch.rateDist::0 21551 75.43% 75.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 541 1.89% 77.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 402 1.41% 78.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 607 2.12% 80.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 545 1.91% 82.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 439 1.54% 84.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 542 1.90% 86.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 448 1.57% 87.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 3495 12.23% 100.00% # Number of instructions fetched each cycle (Total)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.fetch.rateDist::total 28570 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.160135 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.881688 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 37575 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 12018 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 5449 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 625 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1245 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 719 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 495 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 33794 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 947 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1245 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 38261 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 5449 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 1170 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 5378 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 5409 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 31549 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 73 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 407 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 458 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 4425 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 23766 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 39316 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 39298 # Number of integer rename lookups
test: update stats Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses.
2013-10-16 16:44:12 +02:00
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.rename.UndoneMaps 14626 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 56 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 2199 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 3120 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1520 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 45 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores.
system.cpu.memDep1.insertedLoads 2933 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep1.insertedStores 1394 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep1.conflictingLoads 11 # Number of conflicting loads.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.iqInstsAdded 28021 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 23357 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 131 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 14239 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 8472 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 28570 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.817536 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.542788 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.issued_per_cycle::0 19963 69.87% 69.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 2657 9.30% 79.17% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 1959 6.86% 86.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 1384 4.84% 90.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 1325 4.64% 95.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 682 2.39% 97.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 348 1.22% 99.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 184 0.64% 99.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 68 0.24% 100.00% # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.issued_per_cycle::total 28570 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.fu_full::IntAlu 22 6.04% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.04% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 263 72.25% 78.30% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 79 21.70% 100.00% # attempts to use FU when none available
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.FU_type_0::IntAlu 7749 65.04% 65.05% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.06% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.08% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2973 24.95% 90.03% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1188 9.97% 100.00% # Type of FU issued
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.FU_type_0::total 11915 # Type of FU issued
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.FU_type_1::IntAlu 7559 66.06% 66.08% # Type of FU issued
system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.09% # Type of FU issued
system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued
system.cpu.iq.FU_type_1::MemRead 2735 23.90% 90.01% # Type of FU issued
system.cpu.iq.FU_type_1::MemWrite 1143 9.99% 100.00% # Type of FU issued
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.FU_type_1::total 11442 # Type of FU issued
system.cpu.iq.FU_type::total 23357 0.00% 0.00% # Type of FU issued
system.cpu.iq.rate 0.491623 # Inst issue rate
system.cpu.iq.fu_busy_cnt::0 183 # FU busy when requested
system.cpu.iq.fu_busy_cnt::1 181 # FU busy when requested
system.cpu.iq.fu_busy_cnt::total 364 # FU busy when requested
system.cpu.iq.fu_busy_rate::0 0.007835 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_busy_rate::1 0.007749 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_busy_rate::total 0.015584 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 75737 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 42325 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 20244 # Number of integer instruction queue wakeup accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.int_alu_accesses 23695 # Number of integer alu accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iew.lsq.thread0.forwLoads 87 # Number of loads that had data forwarded from stores
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 1937 # Number of loads squashed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iew.lsq.thread0.squashedStores 655 # Number of stores squashed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iew.lsq.thread0.cacheBlocked 426 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread1.forwLoads 65 # Number of loads that had data forwarded from stores
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iew.lsq.thread1.squashedLoads 1750 # Number of loads squashed
system.cpu.iew.lsq.thread1.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread1.memOrderViolation 18 # Number of memory ordering violations
system.cpu.iew.lsq.thread1.squashedStores 529 # Number of stores squashed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iew.lsq.thread1.cacheBlocked 346 # Number of times an access to memory failed due to the cache being blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iew.iewSquashCycles 1245 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 2860 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 601 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 28216 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 318 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 6053 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 2914 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 32 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 571 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 36 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 148 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 1270 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1418 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 21922 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts::0 2766 # Number of load instructions executed
system.cpu.iew.iewExecLoadInsts::1 2537 # Number of load instructions executed
system.cpu.iew.iewExecLoadInsts::total 5303 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1435 # Number of squashed instructions skipped in execute
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.exec_swp::0 0 # number of swp insts executed
system.cpu.iew.exec_swp::1 0 # number of swp insts executed
system.cpu.iew.exec_swp::total 0 # number of swp insts executed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iew.exec_nop::0 71 # number of nop insts executed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iew.exec_nop::1 73 # number of nop insts executed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iew.exec_nop::total 144 # number of nop insts executed
system.cpu.iew.exec_refs::0 3883 # number of memory reference insts executed
system.cpu.iew.exec_refs::1 3616 # number of memory reference insts executed
system.cpu.iew.exec_refs::total 7499 # number of memory reference insts executed
system.cpu.iew.exec_branches::0 1763 # Number of branches executed
system.cpu.iew.exec_branches::1 1733 # Number of branches executed
system.cpu.iew.exec_branches::total 3496 # Number of branches executed
system.cpu.iew.exec_stores::0 1117 # Number of stores executed
system.cpu.iew.exec_stores::1 1079 # Number of stores executed
system.cpu.iew.exec_stores::total 2196 # Number of stores executed
system.cpu.iew.exec_rate 0.461419 # Inst execution rate
system.cpu.iew.wb_sent::0 10477 # cumulative count of insts sent to commit
system.cpu.iew.wb_sent::1 10192 # cumulative count of insts sent to commit
system.cpu.iew.wb_sent::total 20669 # cumulative count of insts sent to commit
system.cpu.iew.wb_count::0 10260 # cumulative count of insts written-back
system.cpu.iew.wb_count::1 10004 # cumulative count of insts written-back
system.cpu.iew.wb_count::total 20264 # cumulative count of insts written-back
system.cpu.iew.wb_producers::0 5390 # num instructions producing a value
system.cpu.iew.wb_producers::1 5243 # num instructions producing a value
system.cpu.iew.wb_producers::total 10633 # num instructions producing a value
system.cpu.iew.wb_consumers::0 7128 # num instructions consuming a value
system.cpu.iew.wb_consumers::1 6992 # num instructions consuming a value
system.cpu.iew.wb_consumers::total 14120 # num instructions consuming a value
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iew.wb_rate::0 0.215955 # insts written-back per cycle
system.cpu.iew.wb_rate::1 0.210566 # insts written-back per cycle
system.cpu.iew.wb_rate::total 0.426521 # insts written-back per cycle
system.cpu.iew.wb_fanout::0 0.756173 # average fanout of values written-back
system.cpu.iew.wb_fanout::1 0.749857 # average fanout of values written-back
system.cpu.iew.wb_fanout::total 0.753045 # average fanout of values written-back
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.commit.commitSquashedInsts 15441 # The number of squashed insts skipped by commit
add SMT hello world test - 2 threads --HG-- extra : convert_revision : 54cb19d1325295895b6f0b992499bbb0216b45df
2006-10-06 10:23:27 +02:00
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.commit.branchMispredicts 1167 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 28457 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.449028 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.318063 # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.commit.committed_per_cycle::0 23389 82.19% 82.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 2450 8.61% 90.80% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 1057 3.71% 94.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 365 1.28% 95.80% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 316 1.11% 96.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 193 0.68% 97.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 226 0.79% 98.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 154 0.54% 98.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 307 1.08% 100.00% # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.commit.committed_per_cycle::total 28457 # Number of insts commited each cycle
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.committedInsts::0 6389 # Number of instructions committed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.committedInsts::1 6389 # Number of instructions committed
system.cpu.commit.committedInsts::total 12778 # Number of instructions committed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.committedOps::0 6389 # Number of ops (including micro ops) committed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.committedOps::1 6389 # Number of ops (including micro ops) committed
system.cpu.commit.committedOps::total 12778 # Number of ops (including micro ops) committed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed
system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed
system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.refs::0 2048 # Number of memory references committed
system.cpu.commit.refs::1 2048 # Number of memory references committed
system.cpu.commit.refs::total 4096 # Number of memory references committed
system.cpu.commit.loads::0 1183 # Number of loads committed
system.cpu.commit.loads::1 1183 # Number of loads committed
system.cpu.commit.loads::total 2366 # Number of loads committed
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.membars::0 0 # Number of memory barriers committed
system.cpu.commit.membars::1 0 # Number of memory barriers committed
system.cpu.commit.membars::total 0 # Number of memory barriers committed
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.branches::0 1050 # Number of branches committed
system.cpu.commit.branches::1 1050 # Number of branches committed
system.cpu.commit.branches::total 2100 # Number of branches committed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions.
system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions.
system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions.
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.int_insts::0 6307 # Number of committed integer instructions.
system.cpu.commit.int_insts::1 6307 # Number of committed integer instructions.
system.cpu.commit.int_insts::total 12614 # Number of committed integer instructions.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.function_calls::0 127 # Number of function calls committed.
system.cpu.commit.function_calls::1 127 # Number of function calls committed.
system.cpu.commit.function_calls::total 254 # Number of function calls committed.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 6389 # Class of committed instruction
system.cpu.commit.op_class_1::No_OpClass 19 0.30% 0.30% # Class of committed instruction
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_1::IntAlu 4319 67.60% 67.90% # Class of committed instruction
system.cpu.commit.op_class_1::IntMult 1 0.02% 67.91% # Class of committed instruction
system.cpu.commit.op_class_1::IntDiv 0 0.00% 67.91% # Class of committed instruction
system.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::FloatMult 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdAlu 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdCmp 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdCvt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdMisc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdMult 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdShift 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdSqrt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::MemRead 1183 18.52% 86.46% # Class of committed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_1::MemWrite 865 13.54% 100.00% # Class of committed instruction
system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_1::total 6389 # Class of committed instruction
system.cpu.commit.op_class::total 12778 0.00% 0.00% # Class of committed instruction
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.commit.bw_lim_events 307 # number cycles where commit BW limit reached
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits
system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits
system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.rob.rob_reads 133653 # The number of ROB reads
system.cpu.rob.rob_writes 59305 # The number of ROB writes
system.cpu.timesIdled 412 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 18940 # Total number of cycles that the CPU has spent unscheduled due to idling
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.committedInsts::0 6372 # Number of Instructions Simulated
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.committedInsts::1 6372 # Number of Instructions Simulated
system.cpu.committedInsts::total 12744 # Number of Instructions Simulated
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated
system.cpu.committedOps::total 12744 # Number of Ops (including micro ops) Simulated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.cpi::0 7.456058 # CPI: Cycles Per Instruction
system.cpu.cpi::1 7.456058 # CPI: Cycles Per Instruction
system.cpu.cpi_total 3.728029 # CPI: Total CPI of All Threads
system.cpu.ipc::0 0.134119 # IPC: Instructions Per Cycle
system.cpu.ipc::1 0.134119 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.268238 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 27427 # number of integer regfile reads
system.cpu.int_regfile_writes 15512 # number of integer regfile writes
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.fp_regfile_writes 4 # number of floating regfile writes
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.misc_regfile_reads 2 # number of misc regfile reads
system.cpu.misc_regfile_writes 2 # number of misc regfile writes
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.replacements::0 0 # number of replacements
system.cpu.dcache.tags.replacements::1 0 # number of replacements
system.cpu.dcache.tags.replacements::total 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 215.485703 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 5082 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 349 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 14.561605 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 215.485703 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.052609 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.052609 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.085205 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 12575 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 12575 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 4060 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 4060 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1022 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 1022 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 5082 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 5082 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 5082 # number of overall hits
system.cpu.dcache.overall_hits::total 5082 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 323 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 323 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 708 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 708 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1031 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1031 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1031 # number of overall misses
system.cpu.dcache.overall_misses::total 1031 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 22902750 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 22902750 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 50997162 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 50997162 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 73899912 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 73899912 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 73899912 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 73899912 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 4383 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 4383 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 6113 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 6113 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 6113 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 6113 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.073694 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.073694 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409249 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.409249 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.168657 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.168657 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.168657 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.168657 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70906.346749 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 70906.346749 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72029.889831 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 72029.889831 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 71677.897187 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 71677.897187 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 71677.897187 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 71677.897187 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 5816 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 146 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.835616 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 119 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 563 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 563 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 682 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 682 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 682 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 682 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 145 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 145 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 349 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 349 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 349 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 349 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16652250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 16652250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11883990 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11883990 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28536240 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 28536240 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28536240 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 28536240 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046543 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046543 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083815 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083815 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057091 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.057091 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057091 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.057091 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81628.676471 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81628.676471 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81958.551724 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81958.551724 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81765.730659 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 81765.730659 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81765.730659 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 81765.730659 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.replacements::0 7 # number of replacements
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.replacements::1 0 # number of replacements
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.replacements::total 7 # number of replacements
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.tagsinuse 320.653868 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 4726 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 628 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 7.525478 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 320.653868 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.156569 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.156569 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 621 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 261 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.303223 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 11936 # Number of tag accesses
system.cpu.icache.tags.data_accesses 11936 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 4726 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4726 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4726 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 4726 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 4726 # number of overall hits
system.cpu.icache.overall_hits::total 4726 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 928 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 928 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 928 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 928 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 928 # number of overall misses
system.cpu.icache.overall_misses::total 928 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 64563245 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 64563245 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 64563245 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 64563245 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 64563245 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 64563245 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 5654 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 5654 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 5654 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 5654 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 5654 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 5654 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.164132 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.164132 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.164132 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.164132 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.164132 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.164132 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69572.462284 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 69572.462284 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69572.462284 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 69572.462284 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69572.462284 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 69572.462284 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 4138 # number of cycles access was blocked
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.blocked::no_mshrs 83 # number of cycles access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 49.855422 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
Update refs. tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout: Update refs. (Korey's initial push didn't use the default O3-timing config?) --HG-- extra : convert_revision : d6bc241534483114def9cf88d7815ddfc9c88fd1
2006-10-07 17:32:10 +02:00
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 300 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 300 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 300 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 300 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 300 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 300 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 628 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 628 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 628 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 628 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 628 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 628 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46837996 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 46837996 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46837996 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 46837996 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46837996 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 46837996 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.111072 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.111072 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.111072 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.111072 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.111072 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.111072 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74582.796178 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74582.796178 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74582.796178 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 74582.796178 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74582.796178 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 74582.796178 # average overall mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements::0 0 # number of replacements
system.cpu.l2cache.tags.replacements::1 0 # number of replacements
system.cpu.l2cache.tags.replacements::total 0 # number of replacements
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.tagsinuse 443.003584 # Cycle average of tags in use
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.sampled_refs 830 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.002410 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.occ_blocks::cpu.inst 321.314753 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 121.688831 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009806 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.003714 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.013519 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 830 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 335 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 495 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025330 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 8791 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 8791 # Number of data accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 626 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 204 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 830 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 145 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 145 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 626 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 349 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 975 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 626 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 349 # number of overall misses
system.cpu.l2cache.overall_misses::total 975 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46183500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16439250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 62622750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11732750 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 11732750 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 46183500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 28172000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 74355500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 46183500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 28172000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 74355500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 628 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 204 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 832 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 145 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 145 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 628 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 349 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 977 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 628 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 349 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 977 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996815 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadReq_miss_rate::total 0.997596 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996815 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.demand_miss_rate::total 0.997953 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996815 # miss rate for overall accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.overall_miss_rate::total 0.997953 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73775.559105 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80584.558824 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75449.096386 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80915.517241 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80915.517241 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73775.559105 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80722.063037 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 76262.051282 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73775.559105 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80722.063037 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 76262.051282 # average overall miss latency
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
Update refs. tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout: Update refs. (Korey's initial push didn't use the default O3-timing config?) --HG-- extra : convert_revision : d6bc241534483114def9cf88d7815ddfc9c88fd1
2006-10-07 17:32:10 +02:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 626 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 830 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 145 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 145 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 626 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 349 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 975 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 626 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 349 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 975 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38371500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13925750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52297250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9959250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9959250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38371500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23885000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 62256500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38371500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23885000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 62256500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997953 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997953 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61296.325879 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68263.480392 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63008.734940 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68684.482759 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68684.482759 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61296.325879 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68438.395415 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63852.820513 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61296.325879 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68438.395415 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63852.820513 # average overall mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.trans_dist::ReadReq 832 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 832 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 145 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 145 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1256 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 698 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1954 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40192 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 62528 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 977 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 977 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 977 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 488500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1032000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 4.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 556000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
system.membus.trans_dist::ReadReq 830 # Transaction distribution
system.membus.trans_dist::ReadResp 830 # Transaction distribution
system.membus.trans_dist::ReadExReq 145 # Transaction distribution
system.membus.trans_dist::ReadExResp 145 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1950 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1950 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62400 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 62400 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 975 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 975 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 975 # Request fanout histogram
system.membus.reqLayer0.occupancy 1213500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 5.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 9051500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 38.1 # Layer utilization (%)
add SMT hello world test - 2 threads --HG-- extra : convert_revision : 54cb19d1325295895b6f0b992499bbb0216b45df
2006-10-06 10:23:27 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink