gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.829332                       # Number of seconds simulated
sim_ticks                                1829332003500                       # Number of ticks simulated
final_tick                               1829332003500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                2961606                       # Simulator instruction rate (inst/s)
host_op_rate                                  2961604                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            90238056091                       # Simulator tick rate (ticks/s)
host_mem_usage                                 333656                       # Number of bytes of host memory used
host_seconds                                    20.27                       # Real time elapsed on the host
sim_insts                                    60038469                       # Number of instructions simulated
sim_ops                                      60038469                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst            850496                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          66835072                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             67686528                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       850496                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          850496                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7415744                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7415744                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              13289                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1044298                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1057602                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          115871                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               115871                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               464922                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             36535234                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide               525                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                37000680                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          464922                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             464922                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4053799                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4053799                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4053799                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              464922                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            36535234                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide              525                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               41054479                       # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                      9710423                       # DTB read hits
system.cpu.dtb.read_misses                      10329                       # DTB read misses
system.cpu.dtb.read_acv                           210                       # DTB read access violations
system.cpu.dtb.read_accesses                   728856                       # DTB read accesses
system.cpu.dtb.write_hits                     6352496                       # DTB write hits
system.cpu.dtb.write_misses                      1142                       # DTB write misses
system.cpu.dtb.write_acv                          157                       # DTB write access violations
system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
system.cpu.dtb.data_hits                     16062919                       # DTB hits
system.cpu.dtb.data_misses                      11471                       # DTB misses
system.cpu.dtb.data_acv                           367                       # DTB access violations
system.cpu.dtb.data_accesses                  1020787                       # DTB accesses
system.cpu.itb.fetch_hits                     4974637                       # ITB hits
system.cpu.itb.fetch_misses                      5006                       # ITB misses
system.cpu.itb.fetch_acv                          184                       # ITB acv
system.cpu.itb.fetch_accesses                 4979643                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.numPwrStateTransitions               12714                       # Number of power state transitions
system.cpu.pwrStateClkGateDist::samples          6357                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::mean     283043477.146767                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::stdev    441371906.848107                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1000-5e+10         6357    100.00%    100.00% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::min_value       386000                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::max_value   2000000000                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::total            6357                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateResidencyTicks::ON     30024619278                       # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::CLK_GATED 1799307384222                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                       3658670365                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     6357                       # number of quiesce instructions executed
system.cpu.kern.inst.hwrei                     211318                       # number of hwrei instructions executed
system.cpu.kern.ipl_count::0                    74830     40.99%     40.99% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21                     243      0.13%     41.12% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22                    1866      1.02%     42.14% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31                  105622     57.86%    100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total               182561                       # number of times we switched to this ipl
system.cpu.kern.ipl_good::0                     73463     49.29%     49.29% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21                      243      0.16%     49.46% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22                     1866      1.25%     50.71% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31                    73463     49.29%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total                149035                       # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0             1811929137500     99.05%     99.05% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21                20110000      0.00%     99.05% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22                80238000      0.00%     99.05% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31             17302310500      0.95%    100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total         1829331796000                       # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0                  0.981732                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31                 0.695527                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total              0.816357                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx                  4177      2.17%      2.18% # number of callpals executed
system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
system.cpu.kern.callpal::swpipl                175248     91.19%     93.40% # number of callpals executed
system.cpu.kern.callpal::rdps                    6771      3.52%     96.92% # number of callpals executed
system.cpu.kern.callpal::wrkgp                      1      0.00%     96.92% # number of callpals executed
system.cpu.kern.callpal::wrusp                      7      0.00%     96.92% # number of callpals executed
system.cpu.kern.callpal::rdusp                      9      0.00%     96.93% # number of callpals executed
system.cpu.kern.callpal::whami                      2      0.00%     96.93% # number of callpals executed
system.cpu.kern.callpal::rti                     5203      2.71%     99.64% # number of callpals executed
system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
system.cpu.kern.callpal::total                 192179                       # number of callpals executed
system.cpu.kern.mode_switch::kernel              5949                       # number of protection mode switches
system.cpu.kern.mode_switch::user                1737                       # number of protection mode switches
system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
system.cpu.kern.mode_good::kernel                1908                      
system.cpu.kern.mode_good::user                  1737                      
system.cpu.kern.mode_good::idle                   171                      
system.cpu.kern.mode_switch_good::kernel     0.320726                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle       0.081545                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total      0.390064                       # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel        26833316500      1.47%      1.47% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user           1465069000      0.08%      1.55% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle         1801033409500     98.45%    100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
system.cpu.committedInsts                    60038469                       # Number of instructions committed
system.cpu.committedOps                      60038469                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses              55913692                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                 324460                       # Number of float alu accesses
system.cpu.num_func_calls                     1484182                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts      7110791                       # number of instructions that are conditional controls
system.cpu.num_int_insts                     55913692                       # number of integer instructions
system.cpu.num_fp_insts                        324460                       # number of float instructions
system.cpu.num_int_register_reads            76954245                       # number of times the integer registers were read
system.cpu.num_int_register_writes           41740352                       # number of times the integer registers were written
system.cpu.num_fp_register_reads               163642                       # number of times the floating registers were read
system.cpu.num_fp_register_writes              166520                       # number of times the floating registers were written
system.cpu.num_mem_refs                      16115703                       # number of memory refs
system.cpu.num_load_insts                     9747509                       # Number of load instructions
system.cpu.num_store_insts                    6368194                       # Number of store instructions
system.cpu.num_idle_cycles               3598621022.088898                       # Number of idle cycles
system.cpu.num_busy_cycles               60049342.911102                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.016413                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.983587                       # Percentage of idle cycles
system.cpu.Branches                           9064428                       # Number of branches fetched
system.cpu.op_class::No_OpClass               3199100      5.33%      5.33% # Class of executed instruction
system.cpu.op_class::IntAlu                  39448406     65.69%     71.02% # Class of executed instruction
system.cpu.op_class::IntMult                    60677      0.10%     71.12% # Class of executed instruction
system.cpu.op_class::IntDiv                         0      0.00%     71.12% # Class of executed instruction
system.cpu.op_class::FloatAdd                   38087      0.06%     71.18% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     71.18% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     71.18% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     71.18% # Class of executed instruction
system.cpu.op_class::FloatMultAcc                   0      0.00%     71.18% # Class of executed instruction
system.cpu.op_class::FloatDiv                    3636      0.01%     71.19% # Class of executed instruction
system.cpu.op_class::FloatMisc                      0      0.00%     71.19% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     71.19% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     71.19% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     71.19% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     71.19% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     71.19% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     71.19% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     71.19% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     71.19% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     71.19% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     71.19% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     71.19% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     71.19% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     71.19% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     71.19% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                   0      0.00%     71.19% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                   0      0.00%     71.19% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     71.19% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc                  0      0.00%     71.19% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     71.19% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     71.19% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     71.19% # Class of executed instruction
system.cpu.op_class::MemRead                  9830448     16.37%     87.56% # Class of executed instruction
system.cpu.op_class::MemWrite                 6236007     10.38%     97.95% # Class of executed instruction
system.cpu.op_class::FloatMemRead              144629      0.24%     98.19% # Class of executed instruction
system.cpu.op_class::FloatMemWrite             138108      0.23%     98.42% # Class of executed instruction
system.cpu.op_class::IprAccess                 951209      1.58%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                   60050307                       # Class of executed instruction
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements           2042707                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.997802                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            14038420                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           2043219                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs              6.870737                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          10840000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.997802                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999996                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999996                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          443                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          66369780                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         66369780                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data      7807772                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total         7807772                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      5848209                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        5848209                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       183141                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       183141                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       199282                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       199282                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      13655981                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         13655981                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     13655981                       # number of overall hits
system.cpu.dcache.overall_hits::total        13655981                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1721711                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1721711                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       304363                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       304363                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        17162                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        17162                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      2026074                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2026074                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2026074                       # number of overall misses
system.cpu.dcache.overall_misses::total       2026074                       # number of overall misses
system.cpu.dcache.ReadReq_accesses::cpu.data      9529483                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total      9529483                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6152572                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6152572                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200303                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       200303                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       199282                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       199282                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     15682055                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     15682055                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     15682055                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     15682055                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.180672                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.180672                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049469                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.049469                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085680                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085680                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.129197                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.129197                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.129197                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.129197                       # miss rate for overall accesses
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks       833476                       # number of writebacks
system.cpu.dcache.writebacks::total            833476                       # number of writebacks
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements            919606                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.215257                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            59130074                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            920118                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             64.263577                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle        9686452000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.215257                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.998467                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.998467                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          117                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          332                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          60970540                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         60970540                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst     59130074                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        59130074                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      59130074                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         59130074                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     59130074                       # number of overall hits
system.cpu.icache.overall_hits::total        59130074                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       920233                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        920233                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       920233                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         920233                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       920233                       # number of overall misses
system.cpu.icache.overall_misses::total        920233                       # number of overall misses
system.cpu.icache.ReadReq_accesses::cpu.inst     60050307                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     60050307                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     60050307                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     60050307                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     60050307                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     60050307                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.015324                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.015324                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.015324                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.015324                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.015324                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.015324                       # miss rate for overall accesses
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks       919606                       # number of writebacks
system.cpu.icache.writebacks::total            919606                       # number of writebacks
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements           992419                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65520.104765                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            4865571                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1057941                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             4.599095                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle        614754000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks   264.552906                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  4852.732213                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 60402.819646                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.004037                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.074047                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.921674                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.999757                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65522                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          606                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3042                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6629                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55077                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999786                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         48449706                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        48449706                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks       833476                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total       833476                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks       919354                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total       919354                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           12                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           12                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       187293                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       187293                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       906926                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total       906926                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       811229                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       811229                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst       906926                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       998522                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1905448                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       906926                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       998522                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1905448                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data            4                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            4                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       117054                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       117054                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        13289                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        13289                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       927644                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       927644                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst        13289                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      1044698                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       1057987                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        13289                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      1044698                       # number of overall misses
system.cpu.l2cache.overall_misses::total      1057987                       # number of overall misses
system.cpu.l2cache.WritebackDirty_accesses::writebacks       833476                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total       833476                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks       919354                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total       919354                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           16                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           16                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       304347                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       304347                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       920215                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total       920215                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1738873                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      1738873                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst       920215                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2043220                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2963435                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       920215                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2043220                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2963435                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.250000                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.250000                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.384607                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.384607                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.014441                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.014441                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.533474                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.533474                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014441                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.511300                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.357014                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014441                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.511300                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.357014                       # miss rate for overall accesses
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks        74359                       # number of writebacks
system.cpu.l2cache.writebacks::total            74359                       # number of writebacks
system.cpu.toL2Bus.snoop_filter.tot_requests      5925782                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      2962435                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1834                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         1449                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1449                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq           7184                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2666290                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq          9838                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp         9838                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty       833476                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean       919606                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      1209231                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           16                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           16                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       304347                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       304347                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq       920233                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      1738873                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2760072                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6163223                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8923295                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    117749696                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    184154670                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          301904366                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      993364                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic               4774656                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples      6936011                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.000753                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.027431                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            6930788     99.92%     99.92% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1               5223      0.08%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        6936011                       # Request fanout histogram
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.iobus.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                 7358                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7358                       # Transaction distribution
system.iobus.trans_dist::WriteReq               51390                       # Transaction distribution
system.iobus.trans_dist::WriteResp              51390                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5248                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1010                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio         1076                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18012                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        34044                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83452                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83452                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  117496                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20992                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2733                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio         1392                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9006                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total        46126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661616                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total      2661616                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2707742                       # Cumulative packet size per connected master and slave (bytes)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements                41686                       # number of replacements
system.iocache.tags.tagsinuse                1.225569                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41702                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1685780588017                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     1.225569                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.076598                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.076598                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375534                       # Number of tag accesses
system.iocache.tags.data_accesses              375534                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
system.iocache.demand_misses::tsunami.ide        41726                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41726                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41726                       # number of overall misses
system.iocache.overall_misses::total            41726                       # number of overall misses
system.iocache.ReadReq_accesses::tsunami.ide          174                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41726                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41726                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41726                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           41512                       # number of writebacks
system.iocache.writebacks::total                41512                       # number of writebacks
system.membus.snoop_filter.tot_requests       2132776                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests      1034179                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests          408                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq                7184                       # Transaction distribution
system.membus.trans_dist::ReadResp             948291                       # Transaction distribution
system.membus.trans_dist::WriteReq               9838                       # Transaction distribution
system.membus.trans_dist::WriteResp              9838                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       115871                       # Transaction distribution
system.membus.trans_dist::CleanEvict           917188                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              133                       # Transaction distribution
system.membus.trans_dist::UpgradeResp             133                       # Transaction distribution
system.membus.trans_dist::ReadExReq            116925                       # Transaction distribution
system.membus.trans_dist::ReadExResp           116925                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        941107                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        34044                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3107355                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3141399                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       125138                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       125138                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                3266537                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        46126                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     72461888                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     72508014                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2667904                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2667904                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                75175918                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples           2149798                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.000494                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.022210                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 2148737     99.95%     99.95% # Request fanout histogram
system.membus.snoop_fanout::1                    1061      0.05%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2149798                       # Request fanout histogram
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states

---------- End Simulation Statistics   ----------