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gem5/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt

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X86: Add x86 reference output for the timing CPU.
2008-11-10 06:57:15 +01:00
---------- Begin Simulation Statistics ----------
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
sim_seconds 1.650501 # Number of seconds simulated
sim_ticks 1650501252500 # Number of ticks simulated
final_tick 1650501252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats to reflect cache changes Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding.
2016-04-21 10:48:24 +02:00
host_inst_rate 691787 # Simulator instruction rate (inst/s)
host_op_rate 1280153 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1380901785 # Simulator tick rate (ticks/s)
host_mem_usage 282548 # Number of bytes of host memory used
host_seconds 1195.23 # Real time elapsed on the host
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
sim_insts 826847304 # Number of instructions simulated
sim_ops 1530082521 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory
system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 115776 # Number of instructions bytes read from this memory
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.physmem.bytes_written::writebacks 18765248 # Number of bytes written to this memory
system.physmem.bytes_written::total 18765248 # Number of bytes written to this memory
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.physmem.num_reads::cpu.inst 1809 # Number of read requests responded to by this memory
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.physmem.num_reads::cpu.data 379046 # Number of read requests responded to by this memory
system.physmem.num_reads::total 380855 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 293207 # Number of write requests responded to by this memory
system.physmem.num_writes::total 293207 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 70146 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 14697925 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14768071 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 70146 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 70146 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 11369424 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 11369424 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 11369424 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 70146 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 14697925 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 26137495 # Total bandwidth to/from this memory (bytes/s)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
system.cpu.workload.num_syscalls 551 # Number of system calls
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.numCycles 3301002505 # number of cpu cycles simulated
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.committedInsts 826847304 # Number of instructions committed
system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
x86, regressions: updates stats This is due to op class, function call, walker patches.
2013-05-21 18:41:27 +02:00
system.cpu.num_func_calls 35346287 # number of times a function call or return occured
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls
system.cpu.num_int_insts 1527470226 # number of integer instructions
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
system.cpu.num_fp_insts 0 # number of float instructions
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read
system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read
system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written
system.cpu.num_mem_refs 533241508 # number of memory refs
system.cpu.num_load_insts 384083313 # Number of load instructions
system.cpu.num_store_insts 149158195 # Number of store instructions
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.num_busy_cycles 3301002504.998000 # Number of busy cycles
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.Branches 149981740 # Number of branches fetched
system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction
system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction
system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction
system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction
system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.op_class::total 1530082521 # Class of executed instruction
system.cpu.dcache.tags.replacements 2517016 # number of replacements
system.cpu.dcache.tags.tagsinuse 4086.386474 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2521112 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 210.510458 # Average number of references to valid blocks.
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.warmup_cycle 8246025500 # Cycle when the warmup percentage was hit.
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 4086.386474 # Average occupied blocks per requestor
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.997653 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997653 # Average percentage of cache occupancy
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 148366841 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 530720441 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 530720441 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 530720441 # number of overall hits
system.cpu.dcache.overall_hits::total 530720441 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1729742 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1729742 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 791370 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 791370 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2521112 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2521112 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2521112 # number of overall misses
system.cpu.dcache.overall_misses::total 2521112 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 30948499500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 30948499500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 20399257500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 20399257500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 51347757000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 51347757000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 51347757000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 51347757000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 384083342 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 384083342 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 533241553 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 533241553 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 533241553 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 533241553 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004504 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004504 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.004728 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.004728 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.004728 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.004728 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17891.974352 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17891.974352 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25777.142803 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 25777.142803 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 20367.106658 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 20367.106658 # average overall miss latency
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.dcache.writebacks::writebacks 2325221 # number of writebacks
system.cpu.dcache.writebacks::total 2325221 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1729742 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1729742 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791370 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 791370 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2521112 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2521112 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2521112 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2521112 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29218757500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 29218757500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19607887500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 19607887500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48826645000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 48826645000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48826645000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 48826645000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004504 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004504 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005306 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005306 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.004728 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.004728 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16891.974352 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16891.974352 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24777.142803 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24777.142803 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.replacements 1253 # number of replacements
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.icache.tags.tagsinuse 881.361687 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks.
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.icache.tags.avg_refs 379640.306326 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 881.361687 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses
system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1068307822 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1068307822 # number of overall hits
system.cpu.icache.overall_hits::total 1068307822 # number of overall hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
system.cpu.icache.overall_misses::total 2814 # number of overall misses
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.icache.ReadReq_miss_latency::cpu.inst 125255000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 125255000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 125255000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 125255000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 125255000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 125255000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1068310636 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1068310636 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1068310636 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1068310636 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1068310636 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1068310636 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44511.371713 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 44511.371713 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 44511.371713 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 44511.371713 # average overall miss latency
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.icache.writebacks::writebacks 1253 # number of writebacks
system.cpu.icache.writebacks::total 1253 # number of writebacks
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122441000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 122441000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122441000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 122441000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122441000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 122441000 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43511.371713 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43511.371713 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 348438 # number of replacements
system.cpu.l2cache.tags.tagsinuse 29288.734166 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3851952 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 380798 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 10.115473 # Average number of references to valid blocks.
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.warmup_cycle 756996028500 # Cycle when the warmup percentage was hit.
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 20940.857984 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.259734 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.616448 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.639064 # Average percentage of cache occupancy
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004006 # Average percentage of cache occupancy
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.data 0.250751 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.893821 # Average percentage of cache occupancy
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 # Occupied blocks per task id
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.tags.tag_accesses 41509728 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 41509728 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 2325221 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 2325221 # number of WritebackDirty hits
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 585014 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 585014 # number of ReadExReq hits
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1005 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1005 # number of ReadCleanReq hits
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1557052 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 1557052 # number of ReadSharedReq hits
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_hits::cpu.inst 1005 # number of demand (read+write) hits
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.demand_hits::cpu.data 2142066 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2143071 # number of demand (read+write) hits
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_hits::cpu.inst 1005 # number of overall hits
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.overall_hits::cpu.data 2142066 # number of overall hits
system.cpu.l2cache.overall_hits::total 2143071 # number of overall hits
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 206356 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 206356 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1809 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 1809 # number of ReadCleanReq misses
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 172690 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 172690 # number of ReadSharedReq misses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_misses::cpu.inst 1809 # number of demand (read+write) misses
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.demand_misses::cpu.data 379046 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 380855 # number of demand (read+write) misses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_misses::cpu.inst 1809 # number of overall misses
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.overall_misses::cpu.data 379046 # number of overall misses
system.cpu.l2cache.overall_misses::total 380855 # number of overall misses
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12278185500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 12278185500 # number of ReadExReq miss cycles
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 107656000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 107656000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10275095500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 10275095500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 107656000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 22553281000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 22660937000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 107656000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 22553281000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 22660937000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 2325221 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 2325221 # number of WritebackDirty accesses(hits+misses)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.WritebackClean_accesses::writebacks 1253 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1253 # number of WritebackClean accesses(hits+misses)
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 791370 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 791370 # number of ReadExReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2814 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 2814 # number of ReadCleanReq accesses(hits+misses)
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1729742 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 1729742 # number of ReadSharedReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.demand_accesses::cpu.data 2521112 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2523926 # number of demand (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.overall_accesses::cpu.data 2521112 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2523926 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260758 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.260758 # miss rate for ReadExReq accesses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.642857 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.642857 # miss rate for ReadCleanReq accesses
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099836 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099836 # miss rate for ReadSharedReq accesses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.642857 # miss rate for demand accesses
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.data 0.150349 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.150898 # miss rate for demand accesses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.642857 # miss rate for overall accesses
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.data 0.150349 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.150898 # miss rate for overall accesses
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.016961 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.016961 # average ReadExReq miss latency
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.332228 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.332228 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.234524 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.234524 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.demand_avg_miss_latency::total 59500.169356 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.overall_avg_miss_latency::total 59500.169356 # average overall miss latency
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.writebacks::writebacks 293208 # number of writebacks
system.cpu.l2cache.writebacks::total 293208 # number of writebacks
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206356 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 206356 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1809 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1809 # number of ReadCleanReq MSHR misses
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172690 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172690 # number of ReadSharedReq MSHR misses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1809 # number of demand (read+write) MSHR misses
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.data 379046 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 380855 # number of demand (read+write) MSHR misses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1809 # number of overall MSHR misses
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.data 379046 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 380855 # number of overall MSHR misses
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10214625500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10214625500 # number of ReadExReq MSHR miss cycles
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 89566000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 89566000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8548195500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8548195500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 89566000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18762821000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 18852387000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89566000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762821000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 18852387000 # number of overall MSHR miss cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260758 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260758 # mshr miss rate for ReadExReq accesses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.642857 # mshr miss rate for ReadCleanReq accesses
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099836 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099836 # mshr miss rate for ReadSharedReq accesses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for demand accesses
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.150898 # mshr miss rate for demand accesses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for overall accesses
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.150898 # mshr miss rate for overall accesses
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.016961 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.016961 # average ReadExReq mshr miss latency
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.332228 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.332228 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234524 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234524 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data.
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 2618429 # Transaction distribution
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.toL2Bus.trans_dist::CleanEvict 247025 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 791370 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 791370 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1729742 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes)
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7559240 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7566121 # Packet count per connected master and slave (bytes)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes)
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310165312 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 310425600 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 348438 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 2872364 # Request fanout histogram
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::mean 0.000602 # Request fanout histogram
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.toL2Bus.snoop_fanout::stdev 0.024527 # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.toL2Bus.snoop_fanout::0 2870635 99.94% 99.94% # Request fanout histogram
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::1 1729 0.06% 100.00% # Request fanout histogram
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.toL2Bus.snoop_fanout::total 2872364 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4847571500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.membus.trans_dist::ReadResp 174499 # Transaction distribution
system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::CleanEvict 53507 # Transaction distribution
system.membus.trans_dist::ReadExReq 206356 # Transaction distribution
system.membus.trans_dist::ReadExResp 206356 # Transaction distribution
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.membus.trans_dist::ReadSharedReq 174499 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108424 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108424 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1108424 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139968 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139968 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 43139968 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.snoops 0 # Total snoops (count)
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.membus.snoop_fanout::samples 727569 # Request fanout histogram
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.membus.snoop_fanout::0 727569 100.00% 100.00% # Request fanout histogram
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.membus.snoop_fanout::total 727569 # Request fanout histogram
system.membus.reqLayer0.occupancy 1900428000 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17 18:32:53 +01:00
system.membus.respLayer1.occupancy 1904275000 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
X86: Add x86 reference output for the timing CPU.
2008-11-10 06:57:15 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink