2008-11-10 06:57:15 +01:00
---------- Begin Simulation Statistics ----------
2016-03-17 18:30:58 +01:00
sim_seconds 1.650601 # Number of seconds simulated
sim_ticks 1650600522500 # Number of ticks simulated
final_tick 1650600522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2012-01-10 16:59:01 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-03-17 18:30:58 +01:00
host_inst_rate 236277 # Simulator instruction rate (inst/s)
host_op_rate 436901 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 471636555 # Simulator tick rate (ticks/s)
host_mem_usage 314152 # Number of bytes of host memory used
host_seconds 3499.73 # Real time elapsed on the host
sim_insts 826906380 # Number of instructions simulated
sim_ops 1529035683 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2015-11-06 09:26:50 +01:00
system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory
2016-03-17 18:30:58 +01:00
system.physmem.bytes_read::cpu.data 24258880 # Number of bytes read from this memory
system.physmem.bytes_read::total 24374656 # Number of bytes read from this memory
2015-11-06 09:26:50 +01:00
system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 115776 # Number of instructions bytes read from this memory
2016-03-17 18:30:58 +01:00
system.physmem.bytes_written::writebacks 18765184 # Number of bytes written to this memory
system.physmem.bytes_written::total 18765184 # Number of bytes written to this memory
2015-11-06 09:26:50 +01:00
system.physmem.num_reads::cpu.inst 1809 # Number of read requests responded to by this memory
2016-03-17 18:30:58 +01:00
system.physmem.num_reads::cpu.data 379045 # Number of read requests responded to by this memory
system.physmem.num_reads::total 380854 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 293206 # Number of write requests responded to by this memory
system.physmem.num_writes::total 293206 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 70142 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 14697002 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14767144 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 70142 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 70142 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 11368701 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 11368701 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 11368701 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 70142 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 14697002 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 26135845 # Total bandwidth to/from this memory (bytes/s)
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
2012-01-10 16:59:01 +01:00
system.cpu.workload.num_syscalls 551 # Number of system calls
2016-03-17 18:30:58 +01:00
system.cpu.numCycles 3301201045 # number of cpu cycles simulated
2012-01-10 16:59:01 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-03-17 18:30:58 +01:00
system.cpu.committedInsts 826906380 # Number of instructions committed
system.cpu.committedOps 1529035683 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1526653037 # Number of integer alu accesses
2012-01-10 16:59:01 +01:00
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
2013-05-21 18:41:27 +02:00
system.cpu.num_func_calls 35346287 # number of times a function call or return occured
2016-03-17 18:30:58 +01:00
system.cpu.num_conditional_control_insts 92662756 # number of instructions that are conditional controls
system.cpu.num_int_insts 1526653037 # number of integer instructions
2012-01-10 16:59:01 +01:00
system.cpu.num_fp_insts 0 # number of float instructions
2016-03-17 18:30:58 +01:00
system.cpu.num_int_register_reads 3293861747 # number of times the integer registers were read
system.cpu.num_int_register_writes 1237389453 # number of times the integer registers were written
2012-01-10 16:59:01 +01:00
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
2016-03-17 18:30:58 +01:00
system.cpu.num_cc_register_reads 561356848 # number of times the CC registers were read
system.cpu.num_cc_register_writes 376698535 # number of times the CC registers were written
system.cpu.num_mem_refs 533282319 # number of memory refs
system.cpu.num_load_insts 384117825 # Number of load instructions
system.cpu.num_store_insts 149164494 # Number of store instructions
2014-10-20 23:48:19 +02:00
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
2016-03-17 18:30:58 +01:00
system.cpu.num_busy_cycles 3301201044.998000 # Number of busy cycles
2014-10-20 23:48:19 +02:00
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
2016-03-17 18:30:58 +01:00
system.cpu.Branches 149762544 # Number of branches fetched
system.cpu.op_class::No_OpClass 1818553 0.12% 0.12% # Class of executed instruction
system.cpu.op_class::IntAlu 989751625 64.73% 64.85% # Class of executed instruction
2014-05-10 00:58:50 +02:00
system.cpu.op_class::IntMult 306834 0.02% 64.87% # Class of executed instruction
2016-03-17 18:30:58 +01:00
system.cpu.op_class::IntDiv 3876352 0.25% 65.12% # Class of executed instruction
2014-05-10 00:58:50 +02:00
system.cpu.op_class::FloatAdd 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.12% # Class of executed instruction
2016-03-17 18:30:58 +01:00
system.cpu.op_class::MemRead 384117825 25.12% 90.24% # Class of executed instruction
system.cpu.op_class::MemWrite 149164494 9.76% 100.00% # Class of executed instruction
2014-05-10 00:58:50 +02:00
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
2016-03-17 18:30:58 +01:00
system.cpu.op_class::total 1529035683 # Class of executed instruction
system.cpu.dcache.tags.replacements 2515885 # number of replacements
system.cpu.dcache.tags.tagsinuse 4086.387052 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 530762383 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2519981 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 210.621581 # Average number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.warmup_cycle 8246025500 # Cycle when the warmup percentage was hit.
2016-03-17 18:30:58 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 4086.387052 # Average occupied blocks per requestor
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.997653 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997653 # Average percentage of cache occupancy
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-03-17 18:30:58 +01:00
system.cpu.dcache.tags.tag_accesses 1069084709 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1069084709 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 382389020 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 382389020 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148373363 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 148373363 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 530762383 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 530762383 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 530762383 # number of overall hits
system.cpu.dcache.overall_hits::total 530762383 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1728834 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1728834 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 791147 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 791147 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2519981 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2519981 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2519981 # number of overall misses
system.cpu.dcache.overall_misses::total 2519981 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 30936646500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 30936646500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 20396358500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 20396358500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 51333005000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 51333005000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 51333005000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 51333005000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 384117854 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 384117854 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 149164510 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 149164510 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 533282364 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 533282364 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 533282364 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 533282364 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004501 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004501 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005304 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.005304 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.004725 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.004725 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.004725 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.004725 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17894.515321 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17894.515321 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25780.744286 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 25780.744286 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20370.393666 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 20370.393666 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20370.393666 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 20370.393666 # average overall miss latency
2015-03-02 11:04:20 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2016-03-17 18:30:58 +01:00
system.cpu.dcache.writebacks::writebacks 2324237 # number of writebacks
system.cpu.dcache.writebacks::total 2324237 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1728834 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1728834 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791147 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 791147 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2519981 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2519981 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2519981 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2519981 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29207812500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 29207812500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19605211500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 19605211500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48813024000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 48813024000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48813024000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 48813024000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004501 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004501 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005304 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005304 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004725 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.004725 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004725 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.004725 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16894.515321 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16894.515321 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24780.744286 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24780.744286 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19370.393666 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19370.393666 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19370.393666 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19370.393666 # average overall mshr miss latency
2015-03-02 11:04:20 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.replacements 1253 # number of replacements
2016-03-17 18:30:58 +01:00
system.cpu.icache.tags.tagsinuse 881.377882 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1068379901 # Total number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks.
2016-03-17 18:30:58 +01:00
system.cpu.icache.tags.avg_refs 379665.920753 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-03-17 18:30:58 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 881.377882 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.430360 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.430360 # Average percentage of cache occupancy
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id
2016-03-17 18:30:58 +01:00
system.cpu.icache.tags.tag_accesses 2136768244 # Number of tag accesses
system.cpu.icache.tags.data_accesses 2136768244 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1068379901 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1068379901 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1068379901 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1068379901 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1068379901 # number of overall hits
system.cpu.icache.overall_hits::total 1068379901 # number of overall hits
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
system.cpu.icache.overall_misses::total 2814 # number of overall misses
2016-03-17 18:30:58 +01:00
system.cpu.icache.ReadReq_miss_latency::cpu.inst 125256000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 125256000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 125256000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 125256000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 125256000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 125256000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1068382715 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1068382715 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1068382715 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1068382715 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1068382715 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1068382715 # number of overall (read+write) accesses
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses
2012-02-12 23:07:43 +01:00
system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses
2016-03-17 18:30:58 +01:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44511.727079 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 44511.727079 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 44511.727079 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 44511.727079 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.727079 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 44511.727079 # average overall miss latency
2012-01-10 16:59:01 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2012-01-10 16:59:01 +01:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.icache.writebacks::writebacks 1253 # number of writebacks
system.cpu.icache.writebacks::total 1253 # number of writebacks
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses
2016-03-17 18:30:58 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122442000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 122442000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122442000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 122442000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122442000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 122442000 # number of overall MSHR miss cycles
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
2012-02-12 23:07:43 +01:00
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
2016-03-17 18:30:58 +01:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43511.727079 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43511.727079 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.727079 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.727079 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.727079 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.727079 # average overall mshr miss latency
2012-01-10 16:59:01 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.tags.replacements 348437 # number of replacements
system.cpu.l2cache.tags.tagsinuse 29288.556947 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3849932 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 380797 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 10.110195 # Average number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.warmup_cycle 756996028500 # Cycle when the warmup percentage was hit.
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 20940.547795 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.260188 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.748964 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.639055 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004006 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.250755 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.893816 # Average percentage of cache occupancy
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
2014-01-24 22:29:33 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8218 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24062 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.tags.tag_accesses 41491408 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 41491408 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 2324237 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 2324237 # number of WritebackDirty hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 584791 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 584791 # number of ReadExReq hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1005 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1005 # number of ReadCleanReq hits
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1556145 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 1556145 # number of ReadSharedReq hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_hits::cpu.inst 1005 # number of demand (read+write) hits
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_hits::cpu.data 2140936 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2141941 # number of demand (read+write) hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_hits::cpu.inst 1005 # number of overall hits
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.overall_hits::cpu.data 2140936 # number of overall hits
system.cpu.l2cache.overall_hits::total 2141941 # number of overall hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 206356 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 206356 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1809 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 1809 # number of ReadCleanReq misses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 172689 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 172689 # number of ReadSharedReq misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_misses::cpu.inst 1809 # number of demand (read+write) misses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_misses::cpu.data 379045 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 380854 # number of demand (read+write) misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_misses::cpu.inst 1809 # number of overall misses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.overall_misses::cpu.data 379045 # number of overall misses
system.cpu.l2cache.overall_misses::total 380854 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12278185500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 12278185500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 107657000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 107657000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10275036000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 10275036000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 107657000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 22553221500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 22660878500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 107657000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 22553221500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 22660878500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 2324237 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 2324237 # number of WritebackDirty accesses(hits+misses)
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.WritebackClean_accesses::writebacks 1253 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1253 # number of WritebackClean accesses(hits+misses)
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 791147 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 791147 # number of ReadExReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2814 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 2814 # number of ReadCleanReq accesses(hits+misses)
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1728834 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 1728834 # number of ReadSharedReq accesses(hits+misses)
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_accesses::cpu.data 2519981 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2522795 # number of demand (read+write) accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.overall_accesses::cpu.data 2519981 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2522795 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260831 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.260831 # miss rate for ReadExReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.642857 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.642857 # miss rate for ReadCleanReq accesses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099888 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099888 # miss rate for ReadSharedReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.642857 # miss rate for demand accesses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.data 0.150416 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.150965 # miss rate for demand accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.642857 # miss rate for overall accesses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.data 0.150416 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.150965 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.016961 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.016961 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.885019 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.885019 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.234526 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.234526 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.885019 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59500.171982 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.885019 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59500.171982 # average overall miss latency
2009-04-22 19:25:17 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2012-01-10 16:59:01 +01:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2012-01-10 16:59:01 +01:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
2008-11-10 06:57:15 +01:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.writebacks::writebacks 293207 # number of writebacks
system.cpu.l2cache.writebacks::total 293207 # number of writebacks
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206356 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 206356 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1809 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1809 # number of ReadCleanReq MSHR misses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172689 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172689 # number of ReadSharedReq MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1809 # number of demand (read+write) MSHR misses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.data 379045 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 380854 # number of demand (read+write) MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1809 # number of overall MSHR misses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.data 379045 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 380854 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10214625500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10214625500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 89567000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 89567000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8548146000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8548146000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 89567000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18762771500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 18852338500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89567000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762771500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 18852338500 # number of overall MSHR miss cycles
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260831 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260831 # mshr miss rate for ReadExReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.642857 # mshr miss rate for ReadCleanReq accesses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099888 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099888 # mshr miss rate for ReadSharedReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for demand accesses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150416 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.150965 # mshr miss rate for demand accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for overall accesses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150416 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.150965 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.016961 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.016961 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.885019 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.885019 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234526 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234526 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.885019 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.171982 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.885019 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.171982 # average overall mshr miss latency
2012-01-10 16:59:01 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.snoop_filter.tot_requests 5039933 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2517138 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.trans_dist::ReadResp 1731648 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 2617444 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.trans_dist::CleanEvict 246878 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 791147 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 791147 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1728834 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes)
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7555847 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7562728 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes)
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310029952 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 310290240 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 348437 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 2871232 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::mean 0.000602 # Request fanout histogram
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.snoop_fanout::stdev 0.024532 # Request fanout histogram
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.snoop_fanout::0 2869503 99.94% 99.94% # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::1 1729 0.06% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.snoop_fanout::total 2871232 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4845456500 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 3779971500 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
2016-03-17 18:30:58 +01:00
system.membus.trans_dist::ReadResp 174498 # Transaction distribution
system.membus.trans_dist::WritebackDirty 293206 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::CleanEvict 53507 # Transaction distribution
system.membus.trans_dist::ReadExReq 206356 # Transaction distribution
system.membus.trans_dist::ReadExResp 206356 # Transaction distribution
2016-03-17 18:30:58 +01:00
system.membus.trans_dist::ReadSharedReq 174498 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108421 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108421 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1108421 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139840 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139840 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 43139840 # Cumulative packet size per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.membus.snoops 0 # Total snoops (count)
2016-03-17 18:30:58 +01:00
system.membus.snoop_fanout::samples 727567 # Request fanout histogram
2015-03-02 11:04:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-03-17 18:30:58 +01:00
system.membus.snoop_fanout::0 727567 100.00% 100.00% # Request fanout histogram
2015-03-02 11:04:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2016-03-17 18:30:58 +01:00
system.membus.snoop_fanout::total 727567 # Request fanout histogram
system.membus.reqLayer0.occupancy 1900421500 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
2016-03-17 18:30:58 +01:00
system.membus.respLayer1.occupancy 1904270000 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
2008-11-10 06:57:15 +01:00
---------- End Simulation Statistics ----------
