2007-04-09 09:59:56 +02:00
---------- Begin Simulation Statistics ----------
2015-03-02 11:04:20 +01:00
sim_seconds 0.000027 # Number of seconds simulated
2015-09-25 13:27:03 +02:00
sim_ticks 26944000 # Number of ticks simulated
final_tick 26944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2007-04-09 09:59:56 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-03-17 18:25:11 +01:00
host_inst_rate 12271 # Simulator instruction rate (inst/s)
host_op_rate 12271 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 22902062 # Simulator tick rate (ticks/s)
host_mem_usage 227268 # Number of bytes of host memory used
host_seconds 1.18 # Real time elapsed on the host
2012-08-15 16:38:05 +02:00
sim_insts 14436 # Number of instructions simulated
sim_ops 14436 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2015-09-15 15:14:09 +02:00
system.physmem.bytes_read::cpu.inst 21888 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory
system.physmem.bytes_read::total 31296 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 21888 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 21888 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 342 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory
system.physmem.num_reads::total 489 # Number of read requests responded to by this memory
2015-09-25 13:27:03 +02:00
system.physmem.bw_read::cpu.inst 812351544 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 349168646 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1161520190 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 812351544 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 812351544 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 812351544 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 349168646 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1161520190 # Total bandwidth to/from this memory (bytes/s)
2015-09-15 15:14:09 +02:00
system.physmem.readReqs 489 # Number of read requests accepted
2013-11-01 16:56:34 +01:00
system.physmem.writeReqs 0 # Number of write requests accepted
2015-09-15 15:14:09 +02:00
system.physmem.readBursts 489 # Number of DRAM read bursts, including those serviced by the write queue
2013-11-01 16:56:34 +01:00
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
2015-09-15 15:14:09 +02:00
system.physmem.bytesReadDRAM 31296 # Total number of bytes read from DRAM
2013-11-01 16:56:34 +01:00
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
2015-09-15 15:14:09 +02:00
system.physmem.bytesReadSys 31296 # Total read bytes from the system interface side
2013-11-01 16:56:34 +01:00
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::0 107 # Per bank write bursts
2015-09-15 15:14:09 +02:00
system.physmem.perBankRdBursts::1 27 # Per bank write bursts
system.physmem.perBankRdBursts::2 49 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::3 24 # Per bank write bursts
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::4 20 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::5 0 # Per bank write bursts
system.physmem.perBankRdBursts::6 32 # Per bank write bursts
2015-09-15 15:14:09 +02:00
system.physmem.perBankRdBursts::7 36 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::8 4 # Per bank write bursts
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::9 2 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::10 1 # Per bank write bursts
system.physmem.perBankRdBursts::11 0 # Per bank write bursts
2015-09-15 15:14:09 +02:00
system.physmem.perBankRdBursts::12 56 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::13 31 # Per bank write bursts
system.physmem.perBankRdBursts::14 61 # Per bank write bursts
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::15 39 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
2015-09-25 13:27:03 +02:00
system.physmem.totGap 26891000 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2015-09-15 15:14:09 +02:00
system.physmem.readPktSize::6 489 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
2015-09-15 15:14:09 +02:00
system.physmem.rdQLenPdf::0 297 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
2013-05-30 18:54:18 +02:00
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
2015-09-15 15:14:09 +02:00
system.physmem.bytesPerActivate::samples 73 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 396.273973 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 268.840282 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 332.152795 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 12 16.44% 16.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 20 27.40% 43.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 11 15.07% 58.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 7 9.59% 68.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 6 8.22% 76.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1 1.37% 78.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 5 6.85% 84.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1 1.37% 86.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 10 13.70% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 73 # Bytes accessed per row activation
system.physmem.totQLat 3681750 # Total ticks spent queuing
system.physmem.totMemAccLat 12850500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2445000 # Total ticks spent in databus transfers
system.physmem.avgQLat 7529.14 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2015-09-15 15:14:09 +02:00
system.physmem.avgMemAccLat 26279.14 # Average memory access latency per DRAM burst
2015-09-25 13:27:03 +02:00
system.physmem.avgRdBW 1161.52 # Average DRAM read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
2015-09-25 13:27:03 +02:00
system.physmem.avgRdBWSys 1161.52 # Average system read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-09-15 15:14:09 +02:00
system.physmem.busUtil 9.07 # Data bus utilization in percentage
system.physmem.busUtilRead 9.07 # Data bus utilization in percentage for reads
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
2015-09-15 15:14:09 +02:00
system.physmem.avgRdQLen 1.53 # Average read queue length when enqueuing
2013-11-01 16:56:34 +01:00
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
2015-09-15 15:14:09 +02:00
system.physmem.readRowHits 409 # Number of row buffer hits during reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
2015-09-15 15:14:09 +02:00
system.physmem.readRowHitRate 83.64 # Row buffer hit rate for reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
2015-09-25 13:27:03 +02:00
system.physmem.avgGap 54991.82 # Average gap between requests
2015-09-15 15:14:09 +02:00
system.physmem.pageHitRate 83.64 # Row buffer hit rate, read and write combined
2015-03-02 11:04:20 +01:00
system.physmem_0.actEnergy 302400 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 165000 # Energy for precharge commands per rank (pJ)
2015-09-15 15:14:09 +02:00
system.physmem_0.readEnergy 2082600 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
2015-09-15 15:14:09 +02:00
system.physmem_0.actBackEnergy 15849990 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 267750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 20193420 # Total energy per rank (pJ)
system.physmem_0.averagePower 854.974120 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 363750 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-09-15 15:14:09 +02:00
system.physmem_0.memoryStateTime::ACT 22488750 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-09-15 15:14:09 +02:00
system.physmem_1.actEnergy 241920 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 132000 # Energy for precharge commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_1.readEnergy 1318200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
2015-09-15 15:14:09 +02:00
system.physmem_1.actBackEnergy 15637950 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 453750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 19309500 # Total energy per rank (pJ)
system.physmem_1.averagePower 817.549616 # Core power per rank (mW)
2015-09-25 13:27:03 +02:00
system.physmem_1.memoryStateTime::IDLE 2040000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-09-15 15:14:09 +02:00
system.physmem_1.memoryStateTime::ACT 22166500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-09-15 15:14:09 +02:00
system.cpu.branchPred.lookups 8026 # Number of BP lookups
system.cpu.branchPred.condPredicted 5198 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 978 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 5876 # Number of BTB lookups
system.cpu.branchPred.BTBHits 3165 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2015-09-15 15:14:09 +02:00
system.cpu.branchPred.BTBHitPct 53.863172 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 554 # Number of times the RAS was used to get a target.
2014-09-03 13:42:59 +02:00
system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2011-06-11 04:15:34 +02:00
system.cpu.workload.num_syscalls 18 # Number of system calls
2015-09-25 13:27:03 +02:00
system.cpu.numCycles 53889 # number of cpu cycles simulated
2011-06-11 04:15:34 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-09-25 13:27:03 +02:00
system.cpu.fetch.icacheStallCycles 13792 # Number of cycles fetch is stalled on an Icache miss
2015-09-15 15:14:09 +02:00
system.cpu.fetch.Insts 37180 # Number of instructions fetch has processed
system.cpu.fetch.Branches 8026 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 3719 # Number of branches that fetch has predicted taken
2015-09-25 13:27:03 +02:00
system.cpu.fetch.Cycles 15452 # Number of cycles fetch has run and was not squashing or blocked
2015-09-15 15:14:09 +02:00
system.cpu.fetch.SquashCycles 2149 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1088 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 6095 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 549 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 31410 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.183699 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.297330 # Number of instructions fetched each cycle (Total)
2011-06-11 04:15:34 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2015-09-15 15:14:09 +02:00
system.cpu.fetch.rateDist::0 20227 64.40% 64.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 5497 17.50% 81.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 701 2.23% 84.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 561 1.79% 85.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 758 2.41% 88.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 907 2.89% 91.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 332 1.06% 92.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 377 1.20% 93.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 2050 6.53% 100.00% # Number of instructions fetched each cycle (Total)
2011-06-11 04:15:34 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2015-09-15 15:14:09 +02:00
system.cpu.fetch.rateDist::total 31410 # Number of instructions fetched each cycle (Total)
2015-09-25 13:27:03 +02:00
system.cpu.fetch.branchRate 0.148936 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.689937 # Number of inst fetches per cycle
2015-09-15 15:14:09 +02:00
system.cpu.decode.IdleCycles 10981 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 12209 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 6549 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 597 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1074 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 28093 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1074 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 11557 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 929 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 9876 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 6585 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 1389 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 25671 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full
system.cpu.rename.SQFullEvents 994 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 23124 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 48097 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 39637 # Number of integer rename lookups
2012-08-15 16:38:05 +02:00
system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed
2015-09-15 15:14:09 +02:00
system.cpu.rename.UndoneMaps 9305 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 731 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 747 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 3478 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 3489 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 2288 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
2011-06-11 04:15:34 +02:00
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
2015-09-15 15:14:09 +02:00
system.cpu.iq.iqInstsAdded 22031 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 704 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 20835 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 8 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 8299 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 5262 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 229 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 31410 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.663324 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.403192 # Number of insts issued each cycle
2011-06-11 04:15:34 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2015-09-15 15:14:09 +02:00
system.cpu.iq.issued_per_cycle::0 23338 74.30% 74.30% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 2945 9.38% 83.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 1556 4.95% 88.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 1448 4.61% 93.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 938 2.99% 96.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 645 2.05% 98.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 357 1.14% 99.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 149 0.47% 99.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 34 0.11% 100.00% # Number of insts issued each cycle
2011-06-11 04:15:34 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2015-09-15 15:14:09 +02:00
system.cpu.iq.issued_per_cycle::total 31410 # Number of insts issued each cycle
2011-06-11 04:15:34 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2015-09-15 15:14:09 +02:00
system.cpu.iq.fu_full::IntAlu 59 33.33% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 51 28.81% 62.15% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 67 37.85% 100.00% # attempts to use FU when none available
2011-06-11 04:15:34 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
2015-09-15 15:14:09 +02:00
system.cpu.iq.FU_type_0::IntAlu 15392 73.88% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 3355 16.10% 89.98% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 2088 10.02% 100.00% # Type of FU issued
2011-06-11 04:15:34 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2015-09-15 15:14:09 +02:00
system.cpu.iq.FU_type_0::total 20835 # Type of FU issued
2015-09-25 13:27:03 +02:00
system.cpu.iq.rate 0.386628 # Inst issue rate
2015-09-15 15:14:09 +02:00
system.cpu.iq.fu_busy_cnt 177 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.008495 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 73265 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 31060 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 19408 # Number of integer instruction queue wakeup accesses
2011-06-11 04:15:34 +02:00
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
2015-09-15 15:14:09 +02:00
system.cpu.iq.int_alu_accesses 21012 # Number of integer alu accesses
2011-06-11 04:15:34 +02:00
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
2015-09-15 15:14:09 +02:00
system.cpu.iew.lsq.thread0.forwLoads 30 # Number of loads that had data forwarded from stores
2011-06-11 04:15:34 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2015-09-15 15:14:09 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 1264 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
2015-07-03 16:15:03 +02:00
system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations
2015-09-15 15:14:09 +02:00
system.cpu.iew.lsq.thread0.squashedStores 840 # Number of stores squashed
2011-06-11 04:15:34 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2015-07-03 16:15:03 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
2015-09-15 15:14:09 +02:00
system.cpu.iew.lsq.thread0.cacheBlocked 30 # Number of times an access to memory failed due to the cache being blocked
2011-06-11 04:15:34 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2015-09-15 15:14:09 +02:00
system.cpu.iew.iewSquashCycles 1074 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 918 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 23852 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 173 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 3489 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 2288 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 704 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall
2015-07-03 16:15:03 +02:00
system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations
2015-09-15 15:14:09 +02:00
system.cpu.iew.predictedTakenIncorrect 261 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 835 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1096 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 20012 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 3241 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 823 # Number of squashed instructions skipped in execute
2011-06-11 04:15:34 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
2015-09-15 15:14:09 +02:00
system.cpu.iew.exec_nop 1117 # number of nop insts executed
system.cpu.iew.exec_refs 5240 # number of memory reference insts executed
system.cpu.iew.exec_branches 4296 # Number of branches executed
system.cpu.iew.exec_stores 1999 # Number of stores executed
2015-09-25 13:27:03 +02:00
system.cpu.iew.exec_rate 0.371356 # Inst execution rate
2015-09-15 15:14:09 +02:00
system.cpu.iew.wb_sent 19648 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 19408 # cumulative count of insts written-back
system.cpu.iew.wb_producers 9326 # num instructions producing a value
system.cpu.iew.wb_consumers 12017 # num instructions consuming a value
2015-09-25 13:27:03 +02:00
system.cpu.iew.wb_rate 0.360148 # insts written-back per cycle
2015-09-15 15:14:09 +02:00
system.cpu.iew.wb_fanout 0.776067 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 8625 # The number of squashed insts skipped by commit
2008-07-25 01:31:54 +02:00
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
2015-09-15 15:14:09 +02:00
system.cpu.commit.branchMispredicts 978 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 29597 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.512282 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.339725 # Number of insts commited each cycle
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2015-09-15 15:14:09 +02:00
system.cpu.commit.committed_per_cycle::0 23176 78.31% 78.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 3360 11.35% 89.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 1108 3.74% 93.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 619 2.09% 95.49% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 326 1.10% 96.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 270 0.91% 97.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 381 1.29% 98.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 67 0.23% 99.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 290 0.98% 100.00% # Number of insts commited each cycle
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2015-09-15 15:14:09 +02:00
system.cpu.commit.committed_per_cycle::total 29597 # Number of insts commited each cycle
2012-08-15 16:38:05 +02:00
system.cpu.commit.committedInsts 15162 # Number of instructions committed
system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
2011-06-11 04:15:34 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2012-08-15 16:38:05 +02:00
system.cpu.commit.refs 3673 # Number of memory references committed
system.cpu.commit.loads 2225 # Number of loads committed
2011-04-20 03:45:23 +02:00
system.cpu.commit.membars 0 # Number of memory barriers committed
2012-08-15 16:38:05 +02:00
system.cpu.commit.branches 3358 # Number of branches committed
2011-06-11 04:15:34 +02:00
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
2012-08-15 16:38:05 +02:00
system.cpu.commit.int_insts 12174 # Number of committed integer instructions.
2011-06-11 04:15:34 +02:00
system.cpu.commit.function_calls 187 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 726 4.79% 4.79% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 10763 70.99% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 15162 # Class of committed instruction
2015-09-15 15:14:09 +02:00
system.cpu.commit.bw_lim_events 290 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 52271 # The number of ROB reads
system.cpu.rob.rob_writes 49405 # The number of ROB writes
system.cpu.timesIdled 197 # Number of times that the entire CPU went into an idle state and unscheduled itself
2015-09-25 13:27:03 +02:00
system.cpu.idleCycles 22479 # Total number of cycles that the CPU has spent unscheduled due to idling
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts 14436 # Number of Instructions Simulated
system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
2015-09-25 13:27:03 +02:00
system.cpu.cpi 3.732959 # CPI: Cycles Per Instruction
system.cpu.cpi_total 3.732959 # CPI: Total CPI of All Threads
system.cpu.ipc 0.267884 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.267884 # IPC: Total IPC of All Threads
2016-03-17 18:25:11 +01:00
system.cpu.int_regfile_reads 32030 # number of integer regfile reads
2015-09-15 15:14:09 +02:00
system.cpu.int_regfile_writes 17799 # number of integer regfile writes
system.cpu.misc_regfile_reads 6992 # number of misc regfile reads
2011-06-11 04:15:34 +02:00
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.replacements 0 # number of replacements
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.tagsinuse 98.069813 # Cycle average of tags in use
2015-09-15 15:14:09 +02:00
system.cpu.dcache.tags.total_refs 4030 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 27.602740 # Average number of references to valid blocks.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.occ_blocks::cpu.data 98.069813 # Average occupied blocks per requestor
2015-09-15 15:14:09 +02:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.023943 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.023943 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id
2015-09-15 15:14:09 +02:00
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 9286 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 9286 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 2991 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 2991 # number of ReadReq hits
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
2015-09-15 15:14:09 +02:00
system.cpu.dcache.demand_hits::cpu.data 4024 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 4024 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 4024 # number of overall hits
system.cpu.dcache.overall_hits::total 4024 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 131 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 131 # number of ReadReq misses
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses
2015-09-15 15:14:09 +02:00
system.cpu.dcache.demand_misses::cpu.data 540 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 540 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 540 # number of overall misses
system.cpu.dcache.overall_misses::total 540 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9101000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 9101000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 26970477 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 26970477 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 36071477 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 36071477 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 36071477 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 36071477 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 3122 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 3122 # number of ReadReq accesses(hits+misses)
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
2015-09-15 15:14:09 +02:00
system.cpu.dcache.demand_accesses::cpu.data 4564 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 4564 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 4564 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 4564 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.041960 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.041960 # miss rate for ReadReq accesses
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.118317 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.118317 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.118317 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.118317 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69473.282443 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 69473.282443 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65942.486553 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 65942.486553 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 66799.031481 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 66799.031481 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 66799.031481 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 66799.031481 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 1282 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-09-15 15:14:09 +02:00
system.cpu.dcache.blocked::no_mshrs 27 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
2015-09-15 15:14:09 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.481481 # average number of cycles each access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2015-09-15 15:14:09 +02:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits
2015-09-15 15:14:09 +02:00
system.cpu.dcache.demand_mshr_hits::cpu.data 393 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 393 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 393 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 393 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses
2015-09-15 15:14:09 +02:00
system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5139000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5139000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6383500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6383500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11522500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11522500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11522500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11522500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020500 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020500 # mshr miss rate for ReadReq accesses
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032209 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.032209 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032209 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.032209 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80296.875000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80296.875000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76909.638554 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76909.638554 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78384.353741 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 78384.353741 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78384.353741 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78384.353741 # average overall mshr miss latency
2014-12-23 15:31:20 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.replacements 0 # number of replacements
2015-09-25 13:27:03 +02:00
system.cpu.icache.tags.tagsinuse 190.290590 # Cycle average of tags in use
2015-09-15 15:14:09 +02:00
system.cpu.icache.tags.total_refs 5576 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 344 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 16.209302 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-09-25 13:27:03 +02:00
system.cpu.icache.tags.occ_blocks::cpu.inst 190.290590 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.092915 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.092915 # Average percentage of cache occupancy
2015-09-15 15:14:09 +02:00
system.cpu.icache.tags.occ_task_id_blocks::1024 344 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 12534 # Number of tag accesses
system.cpu.icache.tags.data_accesses 12534 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 5576 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 5576 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 5576 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 5576 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 5576 # number of overall hits
system.cpu.icache.overall_hits::total 5576 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 519 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 519 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 519 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 519 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 519 # number of overall misses
system.cpu.icache.overall_misses::total 519 # number of overall misses
2015-09-25 13:27:03 +02:00
system.cpu.icache.ReadReq_miss_latency::cpu.inst 36200500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 36200500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 36200500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 36200500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 36200500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 36200500 # number of overall miss cycles
2015-09-15 15:14:09 +02:00
system.cpu.icache.ReadReq_accesses::cpu.inst 6095 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 6095 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 6095 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 6095 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 6095 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 6095 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085152 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.085152 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.085152 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.085152 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.085152 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.085152 # miss rate for overall accesses
2015-09-25 13:27:03 +02:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69750.481696 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 69750.481696 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69750.481696 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 69750.481696 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69750.481696 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 69750.481696 # average overall miss latency
2015-09-15 15:14:09 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2011-06-11 04:15:34 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-09-15 15:14:09 +02:00
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
2011-06-11 04:15:34 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2015-09-15 15:14:09 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2011-06-11 04:15:34 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
2015-09-15 15:14:09 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 175 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 175 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 175 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 175 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 175 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 175 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 344 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 344 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 344 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26532000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 26532000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26532000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 26532000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26532000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 26532000 # number of overall MSHR miss cycles
2015-09-15 15:14:09 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.056440 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.056440 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.056440 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.056440 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.056440 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.056440 # mshr miss rate for overall accesses
2015-09-25 13:27:03 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77127.906977 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77127.906977 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77127.906977 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 77127.906977 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77127.906977 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 77127.906977 # average overall mshr miss latency
2011-06-11 04:15:34 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.tags.tagsinuse 224.000415 # Cycle average of tags in use
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.tags.sampled_refs 405 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.004938 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.tags.occ_blocks::cpu.inst 189.663901 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 34.336514 # Average occupied blocks per requestor
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005788 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001048 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.006836 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 405 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012360 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4416 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4416 # Number of data accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 342 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 342 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 64 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 64 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 342 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 147 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 489 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 342 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses
system.cpu.l2cache.overall_misses::total 489 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6258000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6258000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25992500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 25992500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5044000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 5044000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 25992500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 11302000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 37294500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 25992500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 11302000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 37294500 # number of overall miss cycles
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses)
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 344 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 344 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 64 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 344 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 491 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 344 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 491 # number of overall (read+write) accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994186 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994186 # miss rate for ReadCleanReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994186 # miss rate for demand accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_miss_rate::total 0.995927 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994186 # miss rate for overall accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.overall_miss_rate::total 0.995927 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75397.590361 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75397.590361 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76001.461988 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76001.461988 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78812.500000 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78812.500000 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76001.461988 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76884.353741 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 76266.871166 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76001.461988 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76884.353741 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 76266.871166 # average overall miss latency
2009-04-22 19:25:17 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2011-06-11 04:15:34 +02:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2011-06-11 04:15:34 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
2007-04-09 09:59:56 +02:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 342 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 342 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 64 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 64 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 342 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 489 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 342 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 489 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5428000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5428000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22572500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22572500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4414000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4414000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22572500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9842000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 32414500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22572500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9842000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 32414500 # number of overall MSHR miss cycles
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994186 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994186 # mshr miss rate for ReadCleanReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994186 # mshr miss rate for demand accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::total 0.995927 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994186 # mshr miss rate for overall accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995927 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65397.590361 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65397.590361 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66001.461988 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66001.461988 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68968.750000 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68968.750000 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66001.461988 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66952.380952 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66287.321063 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66001.461988 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66952.380952 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66287.321063 # average overall mshr miss latency
2011-06-11 04:15:34 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.tot_requests 491 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.trans_dist::ReadResp 407 # Transaction distribution
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.trans_dist::ReadCleanReq 344 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 64 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 688 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 981 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22016 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 31360 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.snoop_fanout::samples 491 # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::mean 0.004073 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.063757 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::0 489 99.59% 99.59% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 2 0.41% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.snoop_fanout::total 491 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 245500 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 516000 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%)
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
2015-09-15 15:14:09 +02:00
system.membus.trans_dist::ReadResp 405 # Transaction distribution
2014-12-23 15:31:20 +01:00
system.membus.trans_dist::ReadExReq 83 # Transaction distribution
system.membus.trans_dist::ReadExResp 83 # Transaction distribution
2015-09-15 15:14:09 +02:00
system.membus.trans_dist::ReadSharedReq 406 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 977 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 977 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31232 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
2015-09-15 15:14:09 +02:00
system.membus.snoop_fanout::samples 489 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-09-15 15:14:09 +02:00
system.membus.snoop_fanout::0 489 100.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2015-09-15 15:14:09 +02:00
system.membus.snoop_fanout::total 489 # Request fanout histogram
2015-07-03 16:15:03 +02:00
system.membus.reqLayer0.occupancy 593500 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
2015-09-15 15:14:09 +02:00
system.membus.respLayer1.occupancy 2584750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 9.6 # Layer utilization (%)
2007-04-09 09:59:56 +02:00
---------- End Simulation Statistics ----------
