2006-07-27 23:47:43 +02:00
---------- Begin Simulation Statistics ----------
2016-12-05 22:48:34 +01:00
sim_seconds 1.926422 # Number of seconds simulated
sim_ticks 1926421638000 # Number of ticks simulated
final_tick 1926421638000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2012-01-25 18:19:50 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-12-05 22:48:34 +01:00
host_inst_rate 1739419 # Simulator instruction rate (inst/s)
host_op_rate 1739418 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 59628989604 # Simulator tick rate (ticks/s)
host_mem_usage 334072 # Number of bytes of host memory used
host_seconds 32.31 # Real time elapsed on the host
2016-10-14 00:21:40 +02:00
sim_insts 56195014 # Number of instructions simulated
sim_ops 56195014 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-12-05 22:48:34 +01:00
system.physmem.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
2016-10-14 00:21:40 +02:00
system.physmem.bytes_read::cpu.inst 844672 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24856896 # Number of bytes read from this memory
2014-09-03 13:42:59 +02:00
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
2016-10-14 00:21:40 +02:00
system.physmem.bytes_read::total 25702528 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 844672 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 844672 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7408960 # Number of bytes written to this memory
system.physmem.bytes_written::total 7408960 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 13198 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 388389 # Number of read requests responded to by this memory
2014-09-03 13:42:59 +02:00
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
2016-10-14 00:21:40 +02:00
system.physmem.num_reads::total 401602 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 115765 # Number of write requests responded to by this memory
system.physmem.num_writes::total 115765 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 438467 # Total read bandwidth from this memory (bytes/s)
2016-12-05 22:48:34 +01:00
system.physmem.bw_read::cpu.data 12903144 # Total read bandwidth from this memory (bytes/s)
2016-10-14 00:21:40 +02:00
system.physmem.bw_read::tsunami.ide 498 # Total read bandwidth from this memory (bytes/s)
2016-12-05 22:48:34 +01:00
system.physmem.bw_read::total 13342109 # Total read bandwidth from this memory (bytes/s)
2016-10-14 00:21:40 +02:00
system.physmem.bw_inst_read::cpu.inst 438467 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 438467 # Instruction read bandwidth from this memory (bytes/s)
2016-12-05 22:48:34 +01:00
system.physmem.bw_write::writebacks 3845970 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3845970 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3845970 # Total bandwidth to/from this memory (bytes/s)
2016-10-14 00:21:40 +02:00
system.physmem.bw_total::cpu.inst 438467 # Total bandwidth to/from this memory (bytes/s)
2016-12-05 22:48:34 +01:00
system.physmem.bw_total::cpu.data 12903144 # Total bandwidth to/from this memory (bytes/s)
2016-10-14 00:21:40 +02:00
system.physmem.bw_total::tsunami.ide 498 # Total bandwidth to/from this memory (bytes/s)
2016-12-05 22:48:34 +01:00
system.physmem.bw_total::total 17188079 # Total bandwidth to/from this memory (bytes/s)
2016-10-14 00:21:40 +02:00
system.physmem.readReqs 401602 # Number of read requests accepted
system.physmem.writeReqs 115765 # Number of write requests accepted
system.physmem.readBursts 401602 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 115765 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 25695552 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue
system.physmem.bytesWritten 7408000 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 25702528 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7408960 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue
2015-07-03 16:15:03 +02:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-10-14 00:21:40 +02:00
system.physmem.perBankRdBursts::0 25229 # Per bank write bursts
system.physmem.perBankRdBursts::1 25631 # Per bank write bursts
system.physmem.perBankRdBursts::2 25563 # Per bank write bursts
system.physmem.perBankRdBursts::3 25503 # Per bank write bursts
system.physmem.perBankRdBursts::4 24978 # Per bank write bursts
system.physmem.perBankRdBursts::5 24964 # Per bank write bursts
system.physmem.perBankRdBursts::6 24209 # Per bank write bursts
2016-08-12 15:12:59 +02:00
system.physmem.perBankRdBursts::7 24494 # Per bank write bursts
2016-10-14 00:21:40 +02:00
system.physmem.perBankRdBursts::8 25180 # Per bank write bursts
system.physmem.perBankRdBursts::9 24757 # Per bank write bursts
system.physmem.perBankRdBursts::10 25269 # Per bank write bursts
system.physmem.perBankRdBursts::11 24873 # Per bank write bursts
system.physmem.perBankRdBursts::12 24512 # Per bank write bursts
system.physmem.perBankRdBursts::13 25367 # Per bank write bursts
2016-08-12 15:12:59 +02:00
system.physmem.perBankRdBursts::14 25615 # Per bank write bursts
2016-10-14 00:21:40 +02:00
system.physmem.perBankRdBursts::15 25349 # Per bank write bursts
system.physmem.perBankWrBursts::0 7626 # Per bank write bursts
system.physmem.perBankWrBursts::1 7640 # Per bank write bursts
system.physmem.perBankWrBursts::2 7866 # Per bank write bursts
system.physmem.perBankWrBursts::3 7539 # Per bank write bursts
system.physmem.perBankWrBursts::4 7128 # Per bank write bursts
system.physmem.perBankWrBursts::5 6982 # Per bank write bursts
system.physmem.perBankWrBursts::6 6324 # Per bank write bursts
system.physmem.perBankWrBursts::7 6321 # Per bank write bursts
system.physmem.perBankWrBursts::8 7317 # Per bank write bursts
system.physmem.perBankWrBursts::9 6511 # Per bank write bursts
system.physmem.perBankWrBursts::10 7117 # Per bank write bursts
system.physmem.perBankWrBursts::11 6900 # Per bank write bursts
system.physmem.perBankWrBursts::12 7101 # Per bank write bursts
2016-08-12 15:12:59 +02:00
system.physmem.perBankWrBursts::13 7827 # Per bank write bursts
system.physmem.perBankWrBursts::14 7864 # Per bank write bursts
2016-10-14 00:21:40 +02:00
system.physmem.perBankWrBursts::15 7687 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2016-10-14 00:21:40 +02:00
system.physmem.numWrRetry 65 # Number of times write queue was full causing retry
2016-12-05 22:48:34 +01:00
system.physmem.totGap 1926409764500 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-10-14 00:21:40 +02:00
system.physmem.readPktSize::6 401602 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2016-10-14 00:21:40 +02:00
system.physmem.writePktSize::6 115765 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 401479 # What read queue length does an incoming req see
2014-09-03 13:42:59 +02:00
system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2016-10-14 00:21:40 +02:00
system.physmem.wrQLenPdf::15 1555 # What write queue length does an incoming req see
2016-12-05 22:48:34 +01:00
system.physmem.wrQLenPdf::16 2767 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5442 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5449 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5980 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6090 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6888 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 7955 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 6560 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 6959 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7525 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 7149 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 6506 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 6626 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 5946 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 5824 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 5647 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 5581 # What write queue length does an incoming req see
2016-10-14 00:21:40 +02:00
system.physmem.wrQLenPdf::33 497 # What write queue length does an incoming req see
2016-12-05 22:48:34 +01:00
system.physmem.wrQLenPdf::34 478 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 398 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 372 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 319 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 334 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 296 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 302 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 330 # What write queue length does an incoming req see
2016-10-14 00:21:40 +02:00
system.physmem.wrQLenPdf::42 351 # What write queue length does an incoming req see
2016-12-05 22:48:34 +01:00
system.physmem.wrQLenPdf::43 379 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 365 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 335 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 288 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 356 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 311 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 303 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 303 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 280 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 264 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 209 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 199 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 205 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 339 # What write queue length does an incoming req see
2016-10-14 00:21:40 +02:00
system.physmem.wrQLenPdf::57 238 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 176 # What write queue length does an incoming req see
2016-12-05 22:48:34 +01:00
system.physmem.wrQLenPdf::59 333 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 299 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 189 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see
2016-10-14 00:21:40 +02:00
system.physmem.wrQLenPdf::63 159 # What write queue length does an incoming req see
2016-12-05 22:48:34 +01:00
system.physmem.bytesPerActivate::samples 63476 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 521.512887 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 315.060266 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 415.295929 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 14957 23.56% 23.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 11430 18.01% 41.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 4320 6.81% 48.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3081 4.85% 53.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 3222 5.08% 58.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1508 2.38% 60.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1584 2.50% 63.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 999 1.57% 64.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 22375 35.25% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 63476 # Bytes accessed per row activation
2016-10-14 00:21:40 +02:00
system.physmem.rdPerTurnAround::samples 5049 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 79.519311 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 2969.676150 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191 5046 99.94% 99.94% # Reads before turning the bus around for writes
2014-09-03 13:42:59 +02:00
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
2016-10-14 00:21:40 +02:00
system.physmem.rdPerTurnAround::total 5049 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5049 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 22.925332 # Writes before turning the bus around for reads
2016-12-05 22:48:34 +01:00
system.physmem.wrPerTurnAround::gmean 18.953728 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 24.991500 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23 4538 89.88% 89.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31 34 0.67% 90.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39 165 3.27% 93.82% # Writes before turning the bus around for reads
2016-10-14 00:21:40 +02:00
system.physmem.wrPerTurnAround::40-47 7 0.14% 93.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55 1 0.02% 93.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63 14 0.28% 94.26% # Writes before turning the bus around for reads
2016-12-05 22:48:34 +01:00
system.physmem.wrPerTurnAround::64-71 8 0.16% 94.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79 5 0.10% 94.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87 34 0.67% 95.19% # Writes before turning the bus around for reads
2016-10-14 00:21:40 +02:00
system.physmem.wrPerTurnAround::88-95 2 0.04% 95.23% # Writes before turning the bus around for reads
2016-12-05 22:48:34 +01:00
system.physmem.wrPerTurnAround::96-103 141 2.79% 98.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111 16 0.32% 98.34% # Writes before turning the bus around for reads
2016-10-14 00:21:40 +02:00
system.physmem.wrPerTurnAround::112-119 13 0.26% 98.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127 3 0.06% 98.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135 6 0.12% 98.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143 6 0.12% 98.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159 3 0.06% 98.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167 2 0.04% 98.99% # Writes before turning the bus around for reads
2016-12-05 22:48:34 +01:00
system.physmem.wrPerTurnAround::168-175 12 0.24% 99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183 4 0.08% 99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191 13 0.26% 99.56% # Writes before turning the bus around for reads
2016-10-14 00:21:40 +02:00
system.physmem.wrPerTurnAround::192-199 10 0.20% 99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207 1 0.02% 99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215 1 0.02% 99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-223 6 0.12% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231 2 0.04% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5049 # Writes before turning the bus around for reads
2016-12-05 22:48:34 +01:00
system.physmem.totQLat 6110922250 # Total ticks spent queuing
system.physmem.totMemAccLat 13638916000 # Total ticks spent from burst creation until serviced by the DRAM
2016-10-14 00:21:40 +02:00
system.physmem.totBusLat 2007465000 # Total ticks spent in databus transfers
2016-12-05 22:48:34 +01:00
system.physmem.avgQLat 15220.50 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-12-05 22:48:34 +01:00
system.physmem.avgMemAccLat 33970.50 # Average memory access latency per DRAM burst
2016-10-14 00:21:40 +02:00
system.physmem.avgRdBW 13.34 # Average DRAM read bandwidth in MiByte/s
2016-08-12 15:12:59 +02:00
system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s
2016-10-14 00:21:40 +02:00
system.physmem.avgRdBWSys 13.34 # Average system read bandwidth in MiByte/s
2016-08-12 15:12:59 +02:00
system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-07-03 16:15:03 +02:00
system.physmem.busUtil 0.13 # Data bus utilization in percentage
2014-09-03 13:42:59 +02:00
system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
2015-03-02 11:04:20 +01:00
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
2014-09-03 13:42:59 +02:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
2016-10-14 00:21:40 +02:00
system.physmem.avgWrQLen 24.93 # Average write queue length when enqueuing
2016-12-05 22:48:34 +01:00
system.physmem.readRowHits 360225 # Number of row buffer hits during reads
2016-10-14 00:21:40 +02:00
system.physmem.writeRowHits 93542 # Number of row buffer hits during writes
system.physmem.readRowHitRate 89.72 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes
2016-12-05 22:48:34 +01:00
system.physmem.avgGap 3723487.90 # Average gap between requests
2016-10-14 00:21:40 +02:00
system.physmem.pageHitRate 87.73 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 220840200 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 117379350 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1432076940 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 299763720 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 5519467200.000001 # Energy for refresh commands per rank (pJ)
2016-12-05 22:48:34 +01:00
system.physmem_0.actBackEnergy 5038088640 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 365587680 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 13029981120 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 6359365440 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 449603503800 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 481990544460 # Total energy per rank (pJ)
system.physmem_0.averagePower 250.199922 # Core power per rank (mW)
system.physmem_0.totalIdleTime 1914259413500 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 611958500 # Time in different power states
2016-10-14 00:21:40 +02:00
system.physmem_0.memoryStateTime::REF 2347892000 # Time in different power states
2016-12-05 22:48:34 +01:00
system.physmem_0.memoryStateTime::SREF 1869275787500 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 16560859500 # Time in different power states
system.physmem_0.memoryStateTime::ACT 9050522500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 28574618000 # Time in different power states
system.physmem_1.actEnergy 232378440 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 123512070 # Energy for precharge commands per rank (pJ)
2016-10-14 00:21:40 +02:00
system.physmem_1.readEnergy 1434583080 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 304451280 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 5706932400.000001 # Energy for refresh commands per rank (pJ)
2016-12-05 22:48:34 +01:00
system.physmem_1.actBackEnergy 5156813940 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 361085280 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 13650484260 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 6593796000 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 449082763260 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 482651694330 # Total energy per rank (pJ)
system.physmem_1.averagePower 250.543123 # Core power per rank (mW)
system.physmem_1.totalIdleTime 1914156494000 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 598122250 # Time in different power states
2016-10-14 00:21:40 +02:00
system.physmem_1.memoryStateTime::REF 2427510000 # Time in different power states
2016-12-05 22:48:34 +01:00
system.physmem_1.memoryStateTime::SREF 1867055047500 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 17171481750 # Time in different power states
system.physmem_1.memoryStateTime::ACT 9234080250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 29935396250 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2012-01-25 18:19:50 +01:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
2016-10-14 00:21:40 +02:00
system.cpu.dtb.read_hits 9066536 # DTB read hits
system.cpu.dtb.read_misses 10331 # DTB read misses
2012-01-25 18:19:50 +01:00
system.cpu.dtb.read_acv 210 # DTB read access violations
2016-10-14 00:21:40 +02:00
system.cpu.dtb.read_accesses 728865 # DTB read accesses
system.cpu.dtb.write_hits 6357492 # DTB write hits
system.cpu.dtb.write_misses 1143 # DTB write misses
2012-01-25 18:19:50 +01:00
system.cpu.dtb.write_acv 157 # DTB write access violations
2016-10-14 00:21:40 +02:00
system.cpu.dtb.write_accesses 291932 # DTB write accesses
system.cpu.dtb.data_hits 15424028 # DTB hits
system.cpu.dtb.data_misses 11474 # DTB misses
2012-01-25 18:19:50 +01:00
system.cpu.dtb.data_acv 367 # DTB access violations
2016-10-14 00:21:40 +02:00
system.cpu.dtb.data_accesses 1020797 # DTB accesses
system.cpu.itb.fetch_hits 4975201 # ITB hits
system.cpu.itb.fetch_misses 5010 # ITB misses
2012-01-25 18:19:50 +01:00
system.cpu.itb.fetch_acv 184 # ITB acv
2016-10-14 00:21:40 +02:00
system.cpu.itb.fetch_accesses 4980211 # ITB accesses
2012-01-25 18:19:50 +01:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
2016-10-14 00:21:40 +02:00
system.cpu.numPwrStateTransitions 12758 # Number of power state transitions
system.cpu.pwrStateClkGateDist::samples 6379 # Distribution of time spent in the clock gated state
2016-12-05 22:48:34 +01:00
system.cpu.pwrStateClkGateDist::mean 281128919.971939 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::stdev 439406494.656653 # Distribution of time spent in the clock gated state
2016-06-06 18:16:44 +02:00
system.cpu.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state
2016-10-14 00:21:40 +02:00
system.cpu.pwrStateClkGateDist::1000-5e+10 6378 99.98% 100.00% # Distribution of time spent in the clock gated state
2016-07-21 18:19:18 +02:00
system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
2016-06-06 18:16:44 +02:00
system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state
2016-10-14 00:21:40 +02:00
system.cpu.pwrStateClkGateDist::total 6379 # Distribution of time spent in the clock gated state
2016-12-05 22:48:34 +01:00
system.cpu.pwrStateResidencyTicks::ON 133100257499 # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::CLK_GATED 1793321380501 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 3852843276 # number of cpu cycles simulated
2012-01-25 18:19:50 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.kern.inst.arm 0 # number of arm instructions executed
2016-10-14 00:21:40 +02:00
system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed
system.cpu.kern.inst.hwrei 212049 # number of hwrei instructions executed
system.cpu.kern.ipl_count::0 74911 40.89% 40.89% # number of times we switched to this ipl
2015-11-06 09:26:50 +01:00
system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
2016-10-14 00:21:40 +02:00
system.cpu.kern.ipl_count::22 1934 1.06% 42.01% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31 106246 57.99% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total 183222 # number of times we switched to this ipl
system.cpu.kern.ipl_good::0 73544 49.31% 49.31% # number of times we switched to this ipl from a different ipl
2012-10-25 19:14:42 +02:00
system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
2016-10-14 00:21:40 +02:00
system.cpu.kern.ipl_good::22 1934 1.30% 50.69% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73544 49.31% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 149153 # number of times we switched to this ipl from a different ipl
2016-12-05 22:48:34 +01:00
system.cpu.kern.ipl_ticks::0 1859428733000 96.52% 96.52% # number of cycles we spent at this ipl
2016-10-14 00:21:40 +02:00
system.cpu.kern.ipl_ticks::21 94503000 0.00% 96.53% # number of cycles we spent at this ipl
2016-12-05 22:48:34 +01:00
system.cpu.kern.ipl_ticks::22 772464500 0.04% 96.57% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 66125203500 3.43% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1926420904000 # number of cycles we spent at this ipl
2016-10-14 00:21:40 +02:00
system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl
2012-01-25 18:19:50 +01:00
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
2016-10-14 00:21:40 +02:00
system.cpu.kern.ipl_used::31 0.692205 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total 0.814056 # fraction of swpipl calls that actually changed the ipl
2012-01-25 18:19:50 +01:00
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
2016-10-14 00:21:40 +02:00
system.cpu.kern.callpal::swpctx 4177 2.16% 2.17% # number of callpals executed
2015-07-03 16:15:03 +02:00
system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
2012-01-25 18:19:50 +01:00
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
2016-10-14 00:21:40 +02:00
system.cpu.kern.callpal::swpipl 175997 91.22% 93.41% # number of callpals executed
system.cpu.kern.callpal::rdps 6834 3.54% 96.96% # number of callpals executed
2012-01-25 18:19:50 +01:00
system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
2014-12-02 12:08:25 +01:00
system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed
2015-11-06 09:26:50 +01:00
system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
2016-10-14 00:21:40 +02:00
system.cpu.kern.callpal::rti 5159 2.67% 99.64% # number of callpals executed
2012-01-25 18:19:50 +01:00
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
2016-10-14 00:21:40 +02:00
system.cpu.kern.callpal::total 192947 # number of callpals executed
system.cpu.kern.mode_switch::kernel 5906 # number of protection mode switches
system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
2016-08-12 15:12:59 +02:00
system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches
2016-10-14 00:21:40 +02:00
system.cpu.kern.mode_good::kernel 1908
system.cpu.kern.mode_good::user 1738
system.cpu.kern.mode_good::idle 170
system.cpu.kern.mode_switch_good::kernel 0.323061 # fraction of useful protection mode switches
2012-01-25 18:19:50 +01:00
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
2016-10-14 00:21:40 +02:00
system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.391786 # fraction of useful protection mode switches
2016-12-05 22:48:34 +01:00
system.cpu.kern.mode_ticks::kernel 47043334000 2.44% 2.44% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 5370278500 0.28% 2.72% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1874007289500 97.28% 100.00% # number of ticks spent at the given mode
2016-10-14 00:21:40 +02:00
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
system.cpu.committedInsts 56195014 # Number of instructions committed
system.cpu.committedOps 56195014 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 52066552 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
system.cpu.num_func_calls 1483758 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 6469897 # number of instructions that are conditional controls
system.cpu.num_int_insts 52066552 # number of integer instructions
system.cpu.num_fp_insts 324460 # number of float instructions
system.cpu.num_int_register_reads 71340789 # number of times the integer registers were read
system.cpu.num_int_register_writes 38530081 # number of times the integer registers were written
system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
system.cpu.num_mem_refs 15476659 # number of memory refs
system.cpu.num_load_insts 9103400 # Number of load instructions
system.cpu.num_store_insts 6373259 # Number of store instructions
2016-12-05 22:48:34 +01:00
system.cpu.num_idle_cycles 3586642761.000138 # Number of idle cycles
system.cpu.num_busy_cycles 266200514.999862 # Number of busy cycles
2016-10-14 00:21:40 +02:00
system.cpu.not_idle_fraction 0.069092 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.930908 # Percentage of idle cycles
system.cpu.Branches 8424278 # Number of branches fetched
system.cpu.op_class::No_OpClass 3201027 5.70% 5.70% # Class of executed instruction
system.cpu.op_class::IntAlu 36239709 64.48% 70.17% # Class of executed instruction
system.cpu.op_class::IntMult 61024 0.11% 70.28% # Class of executed instruction
2015-11-06 09:26:50 +01:00
system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction
2016-10-14 00:21:40 +02:00
system.cpu.op_class::FloatAdd 38087 0.07% 70.35% # Class of executed instruction
2015-11-06 09:26:50 +01:00
system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction
2016-10-19 12:20:04 +02:00
system.cpu.op_class::FloatMultAcc 0 0.00% 70.35% # Class of executed instruction
2015-11-06 09:26:50 +01:00
system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction
2016-10-19 12:20:04 +02:00
system.cpu.op_class::FloatMisc 0 0.00% 70.35% # Class of executed instruction
2015-11-06 09:26:50 +01:00
system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 70.35% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 70.35% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 70.35% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 70.35% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 70.35% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 70.35% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 70.35% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 70.35% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 70.35% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction
2016-10-19 12:20:04 +02:00
system.cpu.op_class::MemRead 9185894 16.34% 86.70% # Class of executed instruction
system.cpu.op_class::MemWrite 6241230 11.10% 97.80% # Class of executed instruction
system.cpu.op_class::FloatMemRead 144629 0.26% 98.06% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 138108 0.25% 98.30% # Class of executed instruction
2016-10-14 00:21:40 +02:00
system.cpu.op_class::IprAccess 953511 1.70% 100.00% # Class of executed instruction
2015-11-06 09:26:50 +01:00
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
2016-10-14 00:21:40 +02:00
system.cpu.op_class::total 56206855 # Class of executed instruction
2016-12-05 22:48:34 +01:00
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 1390804 # number of replacements
2016-10-14 00:21:40 +02:00
system.cpu.dcache.tags.tagsinuse 511.976541 # Cycle average of tags in use
2016-12-05 22:48:34 +01:00
system.cpu.dcache.tags.total_refs 14051759 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1391316 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 10.099617 # Average number of references to valid blocks.
2016-10-14 00:21:40 +02:00
system.cpu.dcache.tags.warmup_cycle 121311500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.976541 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999954 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999954 # Average percentage of cache occupancy
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-12-05 22:48:34 +01:00
system.cpu.dcache.tags.tag_accesses 63163621 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 63163621 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 7815914 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7815914 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 5853567 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 5853567 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183003 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 183003 # number of LoadLockedReq hits
2016-10-14 00:21:40 +02:00
system.cpu.dcache.StoreCondReq_hits::cpu.data 199258 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 199258 # number of StoreCondReq hits
2016-12-05 22:48:34 +01:00
system.cpu.dcache.demand_hits::cpu.data 13669481 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 13669481 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 13669481 # number of overall hits
system.cpu.dcache.overall_hits::total 13669481 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1069734 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1069734 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 304322 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 304322 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17278 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 17278 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 1374056 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1374056 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1374056 # number of overall misses
system.cpu.dcache.overall_misses::total 1374056 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 33050329500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 33050329500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 13442227500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 13442227500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232507000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 232507000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 46492557000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 46492557000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 46492557000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 46492557000 # number of overall miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.dcache.ReadReq_accesses::cpu.data 8885648 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 8885648 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6157889 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6157889 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200281 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 200281 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 199258 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 199258 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 15043537 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 15043537 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 15043537 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 15043537 # number of overall (read+write) accesses
2016-12-05 22:48:34 +01:00
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120389 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.120389 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049420 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.049420 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086269 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086269 # miss rate for LoadLockedReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.091339 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.091339 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.091339 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.091339 # miss rate for overall accesses
2016-12-05 22:48:34 +01:00
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30895.839059 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 30895.839059 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44171.067159 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 44171.067159 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13456.823706 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13456.823706 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 33835.998678 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 33835.998678 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 33835.998678 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 33835.998678 # average overall miss latency
2014-12-02 12:08:25 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-12-05 22:48:34 +01:00
system.cpu.dcache.writebacks::writebacks 835203 # number of writebacks
system.cpu.dcache.writebacks::total 835203 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069734 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1069734 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304322 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 304322 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17278 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17278 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1374056 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1374056 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1374056 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1374056 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
2016-10-14 00:21:40 +02:00
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9652 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 9652 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16582 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 16582 # number of overall MSHR uncacheable misses
2016-12-05 22:48:34 +01:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31980595500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 31980595500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13137905500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 13137905500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215229000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215229000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45118501000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 45118501000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45118501000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 45118501000 # number of overall MSHR miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1533908500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1533908500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1533908500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 1533908500 # number of overall MSHR uncacheable cycles
2016-12-05 22:48:34 +01:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120389 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120389 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049420 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049420 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086269 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086269 # mshr miss rate for LoadLockedReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091339 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.091339 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091339 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.091339 # mshr miss rate for overall accesses
2016-12-05 22:48:34 +01:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29895.839059 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29895.839059 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43171.067159 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43171.067159 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12456.823706 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12456.823706 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32835.998678 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 32835.998678 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32835.998678 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 32835.998678 # average overall mshr miss latency
2016-10-14 00:21:40 +02:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221343.217893 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221343.217893 # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92504.432517 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92504.432517 # average overall mshr uncacheable latency
2016-12-05 22:48:34 +01:00
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 928685 # number of replacements
system.cpu.icache.tags.tagsinuse 507.830405 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 55277500 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 929196 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 59.489602 # Average number of references to valid blocks.
2016-10-14 00:21:40 +02:00
system.cpu.icache.tags.warmup_cycle 44439092500 # Cycle when the warmup percentage was hit.
2016-12-05 22:48:34 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 507.830405 # Average occupied blocks per requestor
2016-10-14 00:21:40 +02:00
system.cpu.icache.tags.occ_percent::cpu.inst 0.991856 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.991856 # Average percentage of cache occupancy
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
2014-05-10 00:58:50 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
2016-12-05 22:48:34 +01:00
system.cpu.icache.tags.tag_accesses 57136212 # Number of tag accesses
system.cpu.icache.tags.data_accesses 57136212 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 55277500 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 55277500 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 55277500 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 55277500 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 55277500 # number of overall hits
system.cpu.icache.overall_hits::total 55277500 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 929356 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 929356 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 929356 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 929356 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 929356 # number of overall misses
system.cpu.icache.overall_misses::total 929356 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 13310087000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 13310087000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 13310087000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 13310087000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 13310087000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 13310087000 # number of overall miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.icache.ReadReq_accesses::cpu.inst 56206856 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 56206856 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 56206856 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 56206856 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 56206856 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 56206856 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016535 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.016535 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.016535 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.016535 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.016535 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.016535 # miss rate for overall accesses
2016-12-05 22:48:34 +01:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14321.838994 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14321.838994 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14321.838994 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14321.838994 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14321.838994 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14321.838994 # average overall miss latency
2012-01-25 18:19:50 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-12-05 22:48:34 +01:00
system.cpu.icache.writebacks::writebacks 928685 # number of writebacks
system.cpu.icache.writebacks::total 928685 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929356 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 929356 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 929356 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 929356 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 929356 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 929356 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12380731000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 12380731000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12380731000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 12380731000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12380731000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 12380731000 # number of overall MSHR miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016535 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016535 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016535 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.016535 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016535 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.016535 # mshr miss rate for overall accesses
2016-12-05 22:48:34 +01:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13321.838994 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13321.838994 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13321.838994 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13321.838994 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13321.838994 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13321.838994 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.tags.replacements 336397 # number of replacements
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.tags.tagsinuse 65387.710870 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4236311 # Total number of references to valid blocks.
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.tags.sampled_refs 401919 # Sample count of references to valid blocks.
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.tags.avg_refs 10.540211 # Average number of references to valid blocks.
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.tags.warmup_cycle 7724199000 # Cycle when the warmup percentage was hit.
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 234.658565 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4730.574877 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 60422.477428 # Average occupied blocks per requestor
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.tags.occ_percent::writebacks 0.003581 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072183 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.921974 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.997737 # Average percentage of cache occupancy
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 518 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 384 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4685 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59935 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.tags.tag_accesses 37511410 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 37511410 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 835203 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 835203 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 928452 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 928452 # number of WritebackClean hits
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.UpgradeReq_hits::cpu.data 12 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 12 # number of UpgradeReq hits
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 187488 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 187488 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 916138 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 916138 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 815038 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 815038 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 916138 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1002526 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1918664 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 916138 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1002526 # number of overall hits
system.cpu.l2cache.overall_hits::total 1918664 # number of overall hits
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 116817 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 116817 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13198 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 13198 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 271974 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 271974 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 13198 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 388791 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 401989 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 13198 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 388791 # number of overall misses
system.cpu.l2cache.overall_misses::total 401989 # number of overall misses
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 246500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 246500 # number of UpgradeReq miss cycles
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10708900500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 10708900500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1353922000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 1353922000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21993208500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 21993208500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 1353922000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 32702109000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 34056031000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 1353922000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 32702109000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 34056031000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 835203 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 835203 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 928452 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 928452 # number of WritebackClean accesses(hits+misses)
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses)
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304305 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 304305 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 929336 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 929336 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1087012 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 1087012 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 929336 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1391317 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2320653 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 929336 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1391317 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2320653 # number of overall (read+write) accesses
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.294118 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.294118 # miss rate for UpgradeReq accesses
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383881 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.383881 # miss rate for ReadExReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014202 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014202 # miss rate for ReadCleanReq accesses
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250203 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250203 # miss rate for ReadSharedReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014202 # miss rate for demand accesses
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.data 0.279441 # miss rate for demand accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.demand_miss_rate::total 0.173222 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014202 # miss rate for overall accesses
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.data 0.279441 # miss rate for overall accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.overall_miss_rate::total 0.173222 # miss rate for overall accesses
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 49300 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 49300 # average UpgradeReq miss latency
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91672.449215 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91672.449215 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 102585.391726 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 102585.391726 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80865.113945 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80865.113945 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 102585.391726 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84112.309699 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 84718.813201 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 102585.391726 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84112.309699 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 84718.813201 # average overall miss latency
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.writebacks::writebacks 74253 # number of writebacks
system.cpu.l2cache.writebacks::total 74253 # number of writebacks
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116817 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 116817 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 13198 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13198 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 271974 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 271974 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 13198 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 388791 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 401989 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 13198 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 388791 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 401989 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9652 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9652 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16582 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16582 # number of overall MSHR uncacheable misses
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 196500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 196500 # number of UpgradeReq MSHR miss cycles
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9540730500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9540730500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1221942000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1221942000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19273468500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19273468500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1221942000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28814199000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 30036141000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1221942000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28814199000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 30036141000 # number of overall MSHR miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447252500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447252500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447252500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447252500 # number of overall MSHR uncacheable cycles
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.294118 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.294118 # mshr miss rate for UpgradeReq accesses
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383881 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383881 # mshr miss rate for ReadExReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014202 # mshr miss rate for ReadCleanReq accesses
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250203 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250203 # mshr miss rate for ReadSharedReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for demand accesses
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279441 # mshr miss rate for demand accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::total 0.173222 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for overall accesses
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279441 # mshr miss rate for overall accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.173222 # mshr miss rate for overall accesses
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 39300 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 39300 # average UpgradeReq mshr miss latency
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81672.449215 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81672.449215 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 92585.391726 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 92585.391726 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70865.113945 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70865.113945 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 92585.391726 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74112.309699 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74718.813201 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 92585.391726 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74112.309699 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74718.813201 # average overall mshr miss latency
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208838.744589 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208838.744589 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87278.524907 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87278.524907 # average overall mshr uncacheable latency
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.snoop_filter.tot_requests 4640179 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319543 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1996 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.snoop_filter.tot_snoops 884 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 884 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.trans_dist::ReadResp 2023455 # Transaction distribution
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.trans_dist::WriteReq 9652 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 9652 # Transaction distribution
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.trans_dist::WritebackDirty 909456 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 928685 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 817745 # Transaction distribution
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.trans_dist::ReadExReq 304305 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 304305 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 929356 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1087173 # Transaction distribution
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.trans_dist::InvalidateReq 219 # Transaction distribution
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.trans_dist::InvalidateResp 1 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787377 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4206794 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 6994171 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118913344 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142551908 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 261465252 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 336955 # Total snoops (count)
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.snoopTraffic 4763520 # Total snoop traffic (bytes)
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.snoop_fanout::samples 2674049 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.001078 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.032812 # Request fanout histogram
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.snoop_fanout::0 2671167 99.89% 99.89% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 2882 0.11% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.snoop_fanout::total 2674049 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4097094500 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.snoopLayer0.occupancy 293883 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 1394034000 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 2098740000 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
2014-12-02 12:08:25 +01:00
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
2016-12-05 22:48:34 +01:00
system.iobus.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
2014-12-02 12:08:25 +01:00
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
2016-10-14 00:21:40 +02:00
system.iobus.trans_dist::WriteReq 51204 # Transaction distribution
system.iobus.trans_dist::WriteResp 51204 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5160 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.iobus.pkt_count_system.bridge.master::total 33164 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.iobus.pkt_count::total 116614 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20640 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.iobus.pkt_size_system.bridge.master::total 44580 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.iobus.pkt_size::total 2706188 # Cumulative packet size per connected master and slave (bytes)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer0.occupancy 5344000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer1.occupancy 757500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer23.occupancy 15813000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer24.occupancy 1891500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer25.occupancy 6041500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer27.occupancy 216206774 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.respLayer0.occupancy 23512000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2015-07-03 16:15:03 +02:00
system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
2014-12-02 12:08:25 +01:00
system.iocache.tags.replacements 41685 # number of replacements
2016-12-05 22:48:34 +01:00
system.iocache.tags.tagsinuse 1.342515 # Cycle average of tags in use
2014-12-02 12:08:25 +01:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2016-10-14 00:21:40 +02:00
system.iocache.tags.warmup_cycle 1760392723000 # Cycle when the warmup percentage was hit.
2016-12-05 22:48:34 +01:00
system.iocache.tags.occ_blocks::tsunami.ide 1.342515 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide 0.083907 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.083907 # Average percentage of cache occupancy
2014-12-02 12:08:25 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
system.iocache.tags.data_accesses 375525 # Number of data accesses
2016-12-05 22:48:34 +01:00
system.iocache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
2016-04-21 10:48:24 +02:00
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
system.iocache.overall_misses::total 41725 # number of overall misses
2016-10-14 00:21:40 +02:00
system.iocache.ReadReq_miss_latency::tsunami.ide 21848883 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21848883 # number of ReadReq miss cycles
2016-12-05 22:48:34 +01:00
system.iocache.WriteLineReq_miss_latency::tsunami.ide 4937049891 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4937049891 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 4958898774 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 4958898774 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 4958898774 # number of overall miss cycles
system.iocache.overall_miss_latency::total 4958898774 # number of overall miss cycles
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
2016-04-21 10:48:24 +02:00
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-12-02 12:08:25 +01:00
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2016-10-14 00:21:40 +02:00
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126294.121387 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 126294.121387 # average ReadReq miss latency
2016-12-05 22:48:34 +01:00
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118816.179510 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118816.179510 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 118847.184518 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 118847.184518 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 118847.184518 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 118847.184518 # average overall miss latency
2016-10-14 00:21:40 +02:00
system.iocache.blocked_cycles::no_mshrs 700 # number of cycles access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-10-14 00:21:40 +02:00
system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2016-10-14 00:21:40 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 175 # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.writebacks::writebacks 41512 # number of writebacks
system.iocache.writebacks::total 41512 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
2016-04-21 10:48:24 +02:00
system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
2016-10-14 00:21:40 +02:00
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13198883 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 13198883 # number of ReadReq MSHR miss cycles
2016-12-05 22:48:34 +01:00
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2857005811 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2857005811 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 2870204694 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 2870204694 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 2870204694 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 2870204694 # number of overall MSHR miss cycles
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-12-02 12:08:25 +01:00
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2016-10-14 00:21:40 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76294.121387 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 76294.121387 # average ReadReq mshr miss latency
2016-12-05 22:48:34 +01:00
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68757.359718 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68757.359718 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68788.608604 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 68788.608604 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68788.608604 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 68788.608604 # average overall mshr miss latency
2016-10-14 00:21:40 +02:00
system.membus.snoop_filter.tot_requests 821141 # Total number of requests made to the snoop filter.
2016-12-05 22:48:34 +01:00
system.membus.snoop_filter.hit_single_requests 378172 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 503 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-08-12 15:12:59 +02:00
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-12-05 22:48:34 +01:00
system.membus.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::ReadReq 6930 # Transaction distribution
2016-08-12 15:12:59 +02:00
system.membus.trans_dist::ReadResp 292275 # Transaction distribution
2016-10-14 00:21:40 +02:00
system.membus.trans_dist::WriteReq 9652 # Transaction distribution
system.membus.trans_dist::WriteResp 9652 # Transaction distribution
system.membus.trans_dist::WritebackDirty 115765 # Transaction distribution
system.membus.trans_dist::CleanEvict 261592 # Transaction distribution
2016-08-12 15:12:59 +02:00
system.membus.trans_dist::UpgradeReq 136 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
2016-10-14 00:21:40 +02:00
system.membus.trans_dist::ReadExReq 116686 # Transaction distribution
system.membus.trans_dist::ReadExResp 116686 # Transaction distribution
2016-08-12 15:12:59 +02:00
system.membus.trans_dist::ReadSharedReq 285345 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
2016-12-05 22:48:34 +01:00
system.membus.trans_dist::InvalidateResp 124 # Transaction distribution
2016-10-14 00:21:40 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33164 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139253 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172417 # Packet count per connected master and slave (bytes)
2016-02-10 10:08:27 +01:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.membus.pkt_count::total 1255842 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44580 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30453760 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30498340 # Cumulative packet size per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.membus.pkt_size::total 33156068 # Cumulative packet size per connected master and slave (bytes)
2016-12-05 22:48:34 +01:00
system.membus.snoops 555 # Total snoops (count)
2016-07-21 18:19:18 +02:00
system.membus.snoopTraffic 27456 # Total snoop traffic (bytes)
2016-10-14 00:21:40 +02:00
system.membus.snoop_fanout::samples 460301 # Request fanout histogram
2016-12-05 22:48:34 +01:00
system.membus.snoop_fanout::mean 0.001419 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.037638 # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-12-05 22:48:34 +01:00
system.membus.snoop_fanout::0 459648 99.86% 99.86% # Request fanout histogram
system.membus.snoop_fanout::1 653 0.14% 100.00% # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.membus.snoop_fanout::total 460301 # Request fanout histogram
2016-12-05 22:48:34 +01:00
system.membus.reqLayer0.occupancy 30123500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.membus.reqLayer1.occupancy 1287046834 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.membus.respLayer1.occupancy 2142988500 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.membus.respLayer2.occupancy 1022522 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
2014-12-02 12:08:25 +01:00
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
2016-12-05 22:48:34 +01:00
system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
2006-07-27 23:47:43 +02:00
---------- End Simulation Statistics ----------
