2011-04-25 23:18:08 +02:00
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---------- Begin Simulation Statistics ----------
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2015-07-03 16:15:03 +02:00
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sim_seconds 0.417249 # Number of seconds simulated
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sim_ticks 417248608500 # Number of ticks simulated
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final_tick 417248608500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2011-04-25 23:18:08 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2015-07-03 16:15:03 +02:00
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host_inst_rate 95567 # Simulator instruction rate (inst/s)
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host_op_rate 176715 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 48224052 # Simulator tick rate (ticks/s)
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host_mem_usage 428536 # Number of bytes of host memory used
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host_seconds 8652.29 # Real time elapsed on the host
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2012-08-15 16:38:05 +02:00
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sim_insts 826877109 # Number of instructions simulated
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2013-03-11 23:45:09 +01:00
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sim_ops 1528988701 # Number of ops (including micro ops) simulated
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2014-01-24 22:29:33 +01:00
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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2015-07-03 16:15:03 +02:00
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system.physmem.bytes_read::cpu.inst 222784 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 24527040 # Number of bytes read from this memory
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system.physmem.bytes_read::total 24749824 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 222784 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 222784 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 18883520 # Number of bytes written to this memory
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system.physmem.bytes_written::total 18883520 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 3481 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 383235 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 386716 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 295055 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 295055 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 533936 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 58782796 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 59316732 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 533936 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 533936 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 45257239 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 45257239 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 45257239 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 533936 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 58782796 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 104573971 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 386716 # Number of read requests accepted
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system.physmem.writeReqs 295055 # Number of write requests accepted
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system.physmem.readBursts 386716 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 295055 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 24729280 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 20544 # Total number of bytes read from write queue
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system.physmem.bytesWritten 18881664 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 24749824 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 18883520 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 321 # Number of DRAM read bursts serviced by the write queue
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2013-11-01 16:56:34 +01:00
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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2015-07-03 16:15:03 +02:00
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system.physmem.neitherReadNorWriteReqs 188421 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 24059 # Per bank write bursts
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system.physmem.perBankRdBursts::1 26427 # Per bank write bursts
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system.physmem.perBankRdBursts::2 24735 # Per bank write bursts
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system.physmem.perBankRdBursts::3 24592 # Per bank write bursts
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system.physmem.perBankRdBursts::4 23512 # Per bank write bursts
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system.physmem.perBankRdBursts::5 23783 # Per bank write bursts
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system.physmem.perBankRdBursts::6 24571 # Per bank write bursts
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system.physmem.perBankRdBursts::7 24367 # Per bank write bursts
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system.physmem.perBankRdBursts::8 23708 # Per bank write bursts
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system.physmem.perBankRdBursts::9 23929 # Per bank write bursts
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system.physmem.perBankRdBursts::10 24776 # Per bank write bursts
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system.physmem.perBankRdBursts::11 24016 # Per bank write bursts
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system.physmem.perBankRdBursts::12 23246 # Per bank write bursts
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system.physmem.perBankRdBursts::13 22935 # Per bank write bursts
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system.physmem.perBankRdBursts::14 23871 # Per bank write bursts
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system.physmem.perBankRdBursts::15 23868 # Per bank write bursts
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system.physmem.perBankWrBursts::0 18618 # Per bank write bursts
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system.physmem.perBankWrBursts::1 19926 # Per bank write bursts
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system.physmem.perBankWrBursts::2 18978 # Per bank write bursts
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system.physmem.perBankWrBursts::3 19008 # Per bank write bursts
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system.physmem.perBankWrBursts::4 18159 # Per bank write bursts
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system.physmem.perBankWrBursts::5 18511 # Per bank write bursts
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system.physmem.perBankWrBursts::6 19142 # Per bank write bursts
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system.physmem.perBankWrBursts::7 19088 # Per bank write bursts
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system.physmem.perBankWrBursts::8 18666 # Per bank write bursts
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system.physmem.perBankWrBursts::9 18203 # Per bank write bursts
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system.physmem.perBankWrBursts::10 18897 # Per bank write bursts
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system.physmem.perBankWrBursts::11 17760 # Per bank write bursts
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system.physmem.perBankWrBursts::12 17400 # Per bank write bursts
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system.physmem.perBankWrBursts::13 16992 # Per bank write bursts
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system.physmem.perBankWrBursts::14 17815 # Per bank write bursts
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system.physmem.perBankWrBursts::15 17863 # Per bank write bursts
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2013-11-01 16:56:34 +01:00
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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2013-11-27 00:05:25 +01:00
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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2015-07-03 16:15:03 +02:00
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system.physmem.totGap 417248585500 # Total gap between requests
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2013-11-01 16:56:34 +01:00
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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2015-07-03 16:15:03 +02:00
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system.physmem.readPktSize::6 386716 # Read request sizes (log2)
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2013-11-01 16:56:34 +01:00
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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2015-07-03 16:15:03 +02:00
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system.physmem.writePktSize::6 295055 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 381306 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 4710 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 331 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 39 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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2013-03-28 00:36:21 +01:00
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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2012-10-30 14:35:32 +01:00
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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2012-10-25 19:14:42 +02:00
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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2014-03-23 16:12:19 +01:00
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
2015-07-03 16:15:03 +02:00
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system.physmem.wrQLenPdf::15 6180 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 6571 # What write queue length does an incoming req see
|
2015-05-05 09:22:39 +02:00
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system.physmem.wrQLenPdf::17 16924 # What write queue length does an incoming req see
|
2015-07-03 16:15:03 +02:00
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system.physmem.wrQLenPdf::18 17529 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 17600 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 17650 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 17661 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 17665 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 17728 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 17675 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 17719 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 17679 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 17738 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 17732 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 17730 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 17919 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 17604 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 17538 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 41 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 23 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 16 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 9 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 8 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 9 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 10 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 11 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 8 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 8 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 6 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 6 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 5 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 3 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
2015-03-02 11:04:20 +01:00
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
2014-05-10 00:58:50 +02:00
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|
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
|
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
2014-03-23 16:12:19 +01:00
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|
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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|
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
2015-07-03 16:15:03 +02:00
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system.physmem.bytesPerActivate::samples 147457 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 295.740616 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 174.463963 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 323.226581 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 54784 37.15% 37.15% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::128-255 40098 27.19% 64.35% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::256-383 13706 9.29% 73.64% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::384-511 7465 5.06% 78.70% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::512-639 5444 3.69% 82.39% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::640-767 3767 2.55% 84.95% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::768-895 3056 2.07% 87.02% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::896-1023 2830 1.92% 88.94% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::1024-1151 16307 11.06% 100.00% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::total 147457 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.rdPerTurnAround::samples 17513 # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.rdPerTurnAround::mean 22.062525 # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.rdPerTurnAround::stdev 217.476315 # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.rdPerTurnAround::0-1023 17502 99.94% 99.94% # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.rdPerTurnAround::1024-2047 6 0.03% 99.97% # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes
|
2015-07-03 16:15:03 +02:00
|
|
|
system.physmem.rdPerTurnAround::total 17513 # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.wrPerTurnAround::samples 17513 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::mean 16.846114 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::gmean 16.774956 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::stdev 2.557273 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::16-19 17320 98.90% 98.90% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::20-23 139 0.79% 99.69% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::24-27 31 0.18% 99.87% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::28-31 5 0.03% 99.90% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::32-35 2 0.01% 99.91% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::36-39 2 0.01% 99.92% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::44-47 1 0.01% 99.93% # Writes before turning the bus around for reads
|
2015-04-30 05:35:23 +02:00
|
|
|
system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads
|
2015-07-03 16:15:03 +02:00
|
|
|
system.physmem.wrPerTurnAround::56-59 1 0.01% 99.94% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads
|
2015-03-02 11:04:20 +01:00
|
|
|
system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads
|
2015-07-03 16:15:03 +02:00
|
|
|
system.physmem.wrPerTurnAround::76-79 3 0.02% 99.97% # Writes before turning the bus around for reads
|
2015-04-30 05:35:23 +02:00
|
|
|
system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Writes before turning the bus around for reads
|
2015-07-03 16:15:03 +02:00
|
|
|
system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Writes before turning the bus around for reads
|
2015-04-30 05:35:23 +02:00
|
|
|
system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads
|
2015-07-03 16:15:03 +02:00
|
|
|
system.physmem.wrPerTurnAround::212-215 1 0.01% 100.00% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::total 17513 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.totQLat 4300099500 # Total ticks spent queuing
|
|
|
|
|
system.physmem.totMemAccLat 11545005750 # Total ticks spent from burst creation until serviced by the DRAM
|
|
|
|
|
system.physmem.totBusLat 1931975000 # Total ticks spent in databus transfers
|
|
|
|
|
system.physmem.avgQLat 11128.77 # Average queueing delay per DRAM burst
|
2015-04-30 05:35:23 +02:00
|
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
2015-07-03 16:15:03 +02:00
|
|
|
system.physmem.avgMemAccLat 29878.77 # Average memory access latency per DRAM burst
|
|
|
|
|
system.physmem.avgRdBW 59.27 # Average DRAM read bandwidth in MiByte/s
|
|
|
|
|
system.physmem.avgWrBW 45.25 # Average achieved write bandwidth in MiByte/s
|
|
|
|
|
system.physmem.avgRdBWSys 59.32 # Average system read bandwidth in MiByte/s
|
|
|
|
|
system.physmem.avgWrBWSys 45.26 # Average system write bandwidth in MiByte/s
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
2015-07-03 16:15:03 +02:00
|
|
|
system.physmem.busUtil 0.82 # Data bus utilization in percentage
|
2015-04-30 05:35:23 +02:00
|
|
|
system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads
|
|
|
|
|
system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes
|
2015-07-03 16:15:03 +02:00
|
|
|
system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
|
|
|
|
|
system.physmem.avgWrQLen 21.79 # Average write queue length when enqueuing
|
|
|
|
|
system.physmem.readRowHits 318002 # Number of row buffer hits during reads
|
|
|
|
|
system.physmem.writeRowHits 215948 # Number of row buffer hits during writes
|
|
|
|
|
system.physmem.readRowHitRate 82.30 # Row buffer hit rate for reads
|
|
|
|
|
system.physmem.writeRowHitRate 73.19 # Row buffer hit rate for writes
|
|
|
|
|
system.physmem.avgGap 612006.94 # Average gap between requests
|
|
|
|
|
system.physmem.pageHitRate 78.35 # Row buffer hit rate, read and write combined
|
|
|
|
|
system.physmem_0.actEnergy 569698920 # Energy for activate commands per rank (pJ)
|
|
|
|
|
system.physmem_0.preEnergy 310847625 # Energy for precharge commands per rank (pJ)
|
|
|
|
|
system.physmem_0.readEnergy 1529026200 # Energy for read commands per rank (pJ)
|
|
|
|
|
system.physmem_0.writeEnergy 981072000 # Energy for write commands per rank (pJ)
|
|
|
|
|
system.physmem_0.refreshEnergy 27252204720 # Energy for refresh commands per rank (pJ)
|
|
|
|
|
system.physmem_0.actBackEnergy 63410789430 # Energy for active background per rank (pJ)
|
|
|
|
|
system.physmem_0.preBackEnergy 194721715500 # Energy for precharge background per rank (pJ)
|
|
|
|
|
system.physmem_0.totalEnergy 288775354395 # Total energy per rank (pJ)
|
|
|
|
|
system.physmem_0.averagePower 692.105150 # Core power per rank (mW)
|
|
|
|
|
system.physmem_0.memoryStateTime::IDLE 323379971500 # Time in different power states
|
|
|
|
|
system.physmem_0.memoryStateTime::REF 13932620000 # Time in different power states
|
2014-12-23 15:31:20 +01:00
|
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
2015-07-03 16:15:03 +02:00
|
|
|
system.physmem_0.memoryStateTime::ACT 79931501500 # Time in different power states
|
2014-12-23 15:31:20 +01:00
|
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
2015-07-03 16:15:03 +02:00
|
|
|
system.physmem_1.actEnergy 544690440 # Energy for activate commands per rank (pJ)
|
|
|
|
|
system.physmem_1.preEnergy 297202125 # Energy for precharge commands per rank (pJ)
|
|
|
|
|
system.physmem_1.readEnergy 1484246400 # Energy for read commands per rank (pJ)
|
|
|
|
|
system.physmem_1.writeEnergy 930262320 # Energy for write commands per rank (pJ)
|
|
|
|
|
system.physmem_1.refreshEnergy 27252204720 # Energy for refresh commands per rank (pJ)
|
|
|
|
|
system.physmem_1.actBackEnergy 61581182625 # Energy for active background per rank (pJ)
|
|
|
|
|
system.physmem_1.preBackEnergy 196326633750 # Energy for precharge background per rank (pJ)
|
|
|
|
|
system.physmem_1.totalEnergy 288416422380 # Total energy per rank (pJ)
|
|
|
|
|
system.physmem_1.averagePower 691.244901 # Core power per rank (mW)
|
|
|
|
|
system.physmem_1.memoryStateTime::IDLE 326066613500 # Time in different power states
|
|
|
|
|
system.physmem_1.memoryStateTime::REF 13932620000 # Time in different power states
|
2014-12-23 15:31:20 +01:00
|
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
2015-07-03 16:15:03 +02:00
|
|
|
system.physmem_1.memoryStateTime::ACT 77244604500 # Time in different power states
|
2014-12-23 15:31:20 +01:00
|
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.branchPred.lookups 230038764 # Number of BP lookups
|
|
|
|
|
system.cpu.branchPred.condPredicted 230038764 # Number of conditional branches predicted
|
|
|
|
|
system.cpu.branchPred.condIncorrect 9737010 # Number of conditional branches incorrect
|
|
|
|
|
system.cpu.branchPred.BTBLookups 131438605 # Number of BTB lookups
|
|
|
|
|
system.cpu.branchPred.BTBHits 128726788 # Number of BTB hits
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.branchPred.BTBHitPct 97.936818 # BTB Hit Percentage
|
|
|
|
|
system.cpu.branchPred.usedRAS 27748214 # Number of times the RAS was used to get a target.
|
|
|
|
|
system.cpu.branchPred.RASInCorrect 1467706 # Number of incorrect RAS predictions.
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.workload.num_syscalls 551 # Number of system calls
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.numCycles 834497218 # number of cpu cycles simulated
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.fetch.icacheStallCycles 185109509 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.Insts 1269285801 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.Branches 230038764 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.predictedBranches 156475002 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.Cycles 638168020 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.SquashCycles 20207441 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.TlbCycles 514 # Number of cycles fetch has spent waiting for tlb
|
|
|
|
|
system.cpu.fetch.MiscStallCycles 99542 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
|
|
|
system.cpu.fetch.PendingTrapStallCycles 817516 # Number of stall cycles due to pending traps
|
|
|
|
|
system.cpu.fetch.PendingQuiesceStallCycles 1330 # Number of stall cycles due to pending quiesce instructions
|
|
|
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 56 # Number of stall cycles due to full MSHR
|
|
|
|
|
system.cpu.fetch.CacheLines 179424674 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 2717056 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed
|
|
|
|
|
system.cpu.fetch.rateDist::samples 834300207 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::mean 2.829871 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::stdev 3.382747 # Number of instructions fetched each cycle (Total)
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.fetch.rateDist::0 426804407 51.16% 51.16% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::1 33711236 4.04% 55.20% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::2 32817404 3.93% 59.13% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::3 33341418 4.00% 63.13% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::4 27188546 3.26% 66.39% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::5 27662073 3.32% 69.70% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::6 36987842 4.43% 74.14% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::7 33698291 4.04% 78.17% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::8 182088990 21.83% 100.00% # Number of instructions fetched each cycle (Total)
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.fetch.rateDist::total 834300207 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.branchRate 0.275662 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.rate 1.521019 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu.decode.IdleCycles 127532754 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.BlockedCycles 374895763 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.RunCycles 240450543 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.UnblockCycles 81317427 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.decode.SquashCycles 10103720 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.DecodedInsts 2225154931 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.rename.SquashCycles 10103720 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.IdleCycles 159590885 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.BlockCycles 159861387 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.serializeStallCycles 39705 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RunCycles 285625371 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.UnblockCycles 219079139 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RenamedInsts 2175033402 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.ROBFullEvents 169320 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu.rename.IQFullEvents 136042771 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.LQFullEvents 24241877 # Number of times rename has blocked due to LQ full
|
|
|
|
|
system.cpu.rename.SQFullEvents 48673196 # Number of times rename has blocked due to SQ full
|
|
|
|
|
system.cpu.rename.RenamedOperands 2279253847 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RenameLookups 5500789642 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.int_rename_lookups 3498971898 # Number of integer rename lookups
|
|
|
|
|
system.cpu.rename.fp_rename_lookups 55892 # Number of floating rename lookups
|
2013-03-11 23:45:09 +01:00
|
|
|
system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.rename.UndoneMaps 665212993 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.serializingInsts 3161 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.tempSerializingInsts 2925 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.rename.skidInsts 415266866 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.memDep0.insertedLoads 528334914 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 209874644 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.conflictingLoads 239338770 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 72144908 # Number of conflicting stores.
|
|
|
|
|
system.cpu.iq.iqInstsAdded 2101019043 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 25133 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqInstsIssued 1826920514 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 398452 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 572055475 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 973771254 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 24581 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.issued_per_cycle::samples 834300207 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::mean 2.189764 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::stdev 2.073153 # Number of insts issued each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::0 254789239 30.54% 30.54% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::1 125577373 15.05% 45.59% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::2 119153367 14.28% 59.87% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::3 111141032 13.32% 73.19% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::4 92244378 11.06% 84.25% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::5 61717114 7.40% 91.65% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::6 43107761 5.17% 96.82% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::7 19155881 2.30% 99.11% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::8 7414062 0.89% 100.00% # Number of insts issued each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::total 834300207 # Number of insts issued each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.iq.fu_full::IntAlu 11334405 42.48% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.48% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemRead 12275528 46.01% 88.49% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemWrite 3069676 11.51% 100.00% # attempts to use FU when none available
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 2718617 0.15% 0.15% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntAlu 1211210104 66.30% 66.45% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntMult 389740 0.02% 66.47% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntDiv 3881078 0.21% 66.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 127 0.00% 66.68% # Type of FU issued
|
2015-04-30 05:35:23 +02:00
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 2 0.00% 66.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 27 0.00% 66.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 416 0.00% 66.68% # Type of FU issued
|
2015-04-30 05:35:23 +02:00
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.iq.FU_type_0::MemRead 435004125 23.81% 90.49% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 173716278 9.51% 100.00% # Type of FU issued
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 1826920514 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 2.189247 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 26679609 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.014604 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 4515187521 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 2673359658 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1796857140 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 31775 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 70770 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 6885 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 1850866868 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 14638 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 185770181 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 144235066 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 213448 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 384677 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 60714458 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 19450 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 994 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 10103720 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 107027275 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 6171947 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 2101044176 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 397040 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 528337223 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 209874644 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 7154 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 1885059 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 3390398 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 384677 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 5738634 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 4563911 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 10302545 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 1805509782 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 428792858 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 21410732 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
|
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.iew.exec_refs 598991015 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 171766085 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 170198157 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 2.163590 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 1802110409 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 1796864025 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 1368049337 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 2090115063 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.iew.wb_rate 2.153229 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.654533 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 572135204 # The number of squashed insts skipped by commit
|
2012-12-30 19:45:52 +01:00
|
|
|
system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.commit.branchMispredicts 9825001 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 756651956 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 2.020729 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.548081 # Number of insts commited each cycle
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 287953386 38.06% 38.06% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 175292333 23.17% 61.22% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 57344837 7.58% 68.80% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 86221937 11.40% 80.20% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 27113369 3.58% 83.78% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 27107052 3.58% 87.36% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 9811804 1.30% 88.66% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 8976581 1.19% 89.85% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 76830657 10.15% 100.00% # Number of insts commited each cycle
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 756651956 # Number of insts commited each cycle
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.commit.committedInsts 826877109 # Number of instructions committed
|
2013-03-11 23:45:09 +01:00
|
|
|
system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2013-03-11 23:45:09 +01:00
|
|
|
system.cpu.commit.refs 533262343 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 384102157 # Number of loads committed
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.commit.branches 149758583 # Number of branches committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
2013-10-16 16:44:12 +02:00
|
|
|
system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions.
|
2013-05-21 18:41:27 +02:00
|
|
|
system.cpu.commit.function_calls 17673145 # Number of function calls committed.
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.commit.op_class_0::No_OpClass 1819099 0.12% 0.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::IntAlu 989721889 64.73% 64.85% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.87% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::IntDiv 3878536 0.25% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.commit.bw_lim_events 76830657 # number cycles where commit BW limit reached
|
|
|
|
|
system.cpu.rob.rob_reads 2780945204 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 4280083493 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 2292 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 197011 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.committedInsts 826877109 # Number of Instructions Simulated
|
2013-03-11 23:45:09 +01:00
|
|
|
system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.cpi 1.009216 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 1.009216 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 0.990869 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.990869 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 2762017076 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 1465005269 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 7183 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 481 # number of floating regfile writes
|
|
|
|
|
system.cpu.cc_regfile_reads 600929280 # number of cc regfile reads
|
|
|
|
|
system.cpu.cc_regfile_writes 409654003 # number of cc regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 990121594 # number of misc regfile reads
|
2013-03-11 23:45:09 +01:00
|
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.dcache.tags.replacements 2534273 # number of replacements
|
|
|
|
|
system.cpu.dcache.tags.tagsinuse 4088.021333 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.tags.total_refs 387553004 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.sampled_refs 2538369 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.avg_refs 152.677961 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.warmup_cycle 1679458500 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4088.021333 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.998052 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.tags.occ_percent::total 0.998052 # Average percentage of cache occupancy
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
|
2015-05-05 09:22:39 +02:00
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 873 # Occupied blocks per task id
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3168 # Occupied blocks per task id
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.dcache.tags.tag_accesses 784232137 # Number of tag accesses
|
|
|
|
|
system.cpu.dcache.tags.data_accesses 784232137 # Number of data accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 238902536 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 238902536 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 148180257 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 148180257 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::cpu.data 387082793 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 387082793 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 387082793 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 387082793 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 2784146 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 2784146 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 979945 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 979945 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses::cpu.data 3764091 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 3764091 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 3764091 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 3764091 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 59451413500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 59451413500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 30841040499 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 30841040499 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 90292453999 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 90292453999 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 90292453999 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 90292453999 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 241686682 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 241686682 # number of ReadReq accesses(hits+misses)
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 390846884 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 390846884 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 390846884 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 390846884 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011520 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.011520 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006570 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.006570 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.009631 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.009631 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.009631 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.009631 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21353.554555 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 21353.554555 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31472.215787 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 31472.215787 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23987.850984 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::total 23987.850984 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23987.850984 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::total 23987.850984 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 10871 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 28 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 1128 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.637411 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.dcache.writebacks::writebacks 2332718 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 2332718 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1016180 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 1016180 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19269 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 19269 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 1035449 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 1035449 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 1035449 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 1035449 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767966 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1767966 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 960676 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 960676 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 2728642 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 2728642 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 2728642 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 2728642 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33608501500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 33608501500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29628930000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 29628930000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63237431500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 63237431500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63237431500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 63237431500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007315 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007315 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006441 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006441 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006981 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.006981 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006981 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.006981 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19009.698999 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19009.698999 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30841.751017 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30841.751017 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23175.422609 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23175.422609 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23175.422609 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23175.422609 # average overall mshr miss latency
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.icache.tags.replacements 6996 # number of replacements
|
|
|
|
|
system.cpu.icache.tags.tagsinuse 1051.094157 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.tags.total_refs 179219973 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.sampled_refs 8606 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.avg_refs 20825.002673 # Average number of references to valid blocks.
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1051.094157 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.513230 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.tags.occ_percent::total 0.513230 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1610 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
|
2015-05-05 09:22:39 +02:00
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 319 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1167 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.786133 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.icache.tags.tag_accesses 359048380 # Number of tag accesses
|
|
|
|
|
system.cpu.icache.tags.data_accesses 359048380 # Number of data accesses
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 179223042 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 179223042 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 179223042 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 179223042 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 179223042 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 179223042 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 201632 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 201632 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 201632 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 201632 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 201632 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 201632 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1282836497 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 1282836497 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 1282836497 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::total 1282836497 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 1282836497 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::total 1282836497 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 179424674 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 179424674 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 179424674 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 179424674 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 179424674 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 179424674 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001124 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.001124 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.001124 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total 0.001124 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.001124 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total 0.001124 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6362.266391 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 6362.266391 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 6362.266391 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total 6362.266391 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 6362.266391 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total 6362.266391 # average overall miss latency
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 972 # number of cycles access was blocked
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 60.750000 # average number of cycles each access was blocked
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2599 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits::total 2599 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 2599 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::total 2599 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 2599 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::total 2599 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 199033 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 199033 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 199033 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 199033 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 199033 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 199033 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 971187998 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 971187998 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 971187998 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 971187998 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 971187998 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 971187998 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001109 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001109 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001109 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.001109 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001109 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.001109 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4879.532530 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4879.532530 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4879.532530 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 4879.532530 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4879.532530 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 4879.532530 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.l2cache.tags.replacements 354039 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tags.tagsinuse 29616.478826 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.tags.total_refs 3899597 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.sampled_refs 386397 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.avg_refs 10.092203 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.warmup_cycle 197715227000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 20954.813586 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 251.117391 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 8410.547849 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.639490 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007663 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.256670 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::total 0.903823 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32358 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 247 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13367 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18661 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987488 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.l2cache.tags.tag_accesses 43296958 # Number of tag accesses
|
|
|
|
|
system.cpu.l2cache.tags.data_accesses 43296958 # Number of data accesses
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 2332718 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 2332718 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1894 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits::total 1894 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 564156 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 564156 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5160 # number of ReadCleanReq hits
|
|
|
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 5160 # number of ReadCleanReq hits
|
|
|
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1590936 # number of ReadSharedReq hits
|
|
|
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 1590936 # number of ReadSharedReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 5160 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 2155092 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 2160252 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 5160 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 2155092 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 2160252 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 188379 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses::total 188379 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 206660 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 206660 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3483 # number of ReadCleanReq misses
|
|
|
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 3483 # number of ReadCleanReq misses
|
|
|
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176617 # number of ReadSharedReq misses
|
|
|
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 176617 # number of ReadSharedReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3483 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 383277 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 386760 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3483 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 383277 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 386760 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13128500 # number of UpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 13128500 # number of UpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16382009500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 16382009500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 282985000 # number of ReadCleanReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 282985000 # number of ReadCleanReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14212128500 # number of ReadSharedReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 14212128500 # number of ReadSharedReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 282985000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 30594138000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 30877123000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 282985000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 30594138000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 30877123000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 2332718 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 2332718 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 190273 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 190273 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 770816 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 770816 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8643 # number of ReadCleanReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 8643 # number of ReadCleanReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1767553 # number of ReadSharedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 1767553 # number of ReadSharedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 8643 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 2538369 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 2547012 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 8643 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 2538369 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 2547012 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990046 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990046 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268105 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.268105 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.402985 # miss rate for ReadCleanReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.402985 # miss rate for ReadCleanReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099922 # miss rate for ReadSharedReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099922 # miss rate for ReadSharedReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.402985 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.150993 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::total 0.151849 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.402985 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.150993 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::total 0.151849 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 69.691951 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 69.691951 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79270.345011 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79270.345011 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81247.487798 # average ReadCleanReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81247.487798 # average ReadCleanReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80468.632691 # average ReadSharedReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80468.632691 # average ReadSharedReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81247.487798 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79822.525223 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 79835.357845 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81247.487798 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79822.525223 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 79835.357845 # average overall miss latency
|
2012-12-30 19:45:52 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.l2cache.writebacks::writebacks 295055 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.writebacks::total 295055 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
|
2015-03-02 11:04:20 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1999 # number of CleanEvict MSHR misses
|
|
|
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::total 1999 # number of CleanEvict MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 188379 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 188379 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206660 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 206660 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3482 # number of ReadCleanReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3482 # number of ReadCleanReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176617 # number of ReadSharedReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176617 # number of ReadSharedReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3482 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 383277 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 386759 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3482 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 383277 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 386759 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3964257964 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3964257964 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14315409500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14315409500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 248098000 # number of ReadCleanReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 248098000 # number of ReadCleanReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12445958500 # number of ReadSharedReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12445958500 # number of ReadSharedReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 248098000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26761368000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 27009466000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 248098000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26761368000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 27009466000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
|
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990046 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990046 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268105 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268105 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.402869 # mshr miss rate for ReadCleanReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.402869 # mshr miss rate for ReadCleanReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099922 # mshr miss rate for ReadSharedReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099922 # mshr miss rate for ReadSharedReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.402869 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150993 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.151848 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.402869 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150993 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.151848 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21044.054613 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21044.054613 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69270.345011 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69270.345011 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71251.579552 # average ReadCleanReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71251.579552 # average ReadCleanReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70468.632691 # average ReadSharedReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70468.632691 # average ReadSharedReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71251.579552 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69822.525223 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69835.391032 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71251.579552 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69822.525223 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69835.391032 # average overall mshr miss latency
|
2012-12-30 19:45:52 +01:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 1966585 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::Writeback 2627773 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 256159 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 190273 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 190273 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 770816 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 770816 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 199033 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1767553 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 214213 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7980639 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count::total 8194852 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 553088 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311749568 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size::total 312302656 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.snoops 544429 # Total snoops (count)
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::samples 5822983 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::mean 1.060800 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.238964 # Request fanout histogram
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.toL2Bus.snoop_fanout::1 5468944 93.92% 93.92% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::2 354039 6.08% 100.00% # Request fanout histogram
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
2015-05-05 09:22:39 +02:00
|
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::total 5822983 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 5095186894 # Layer occupancy (ticks)
|
2015-04-30 05:35:23 +02:00
|
|
|
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.toL2Bus.respLayer0.occupancy 298551493 # Layer occupancy (ticks)
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
2015-07-03 16:15:03 +02:00
|
|
|
system.cpu.toL2Bus.respLayer1.occupancy 3902690569 # Layer occupancy (ticks)
|
|
|
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
|
|
|
|
|
system.membus.trans_dist::ReadResp 180098 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::Writeback 295055 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::CleanEvict 57423 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::UpgradeReq 188421 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::UpgradeResp 188421 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadExReq 206618 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadExResp 206618 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadSharedReq 180098 # Transaction distribution
|
|
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1502752 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1502752 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count::total 1502752 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43633344 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43633344 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size::total 43633344 # Cumulative packet size per connected master and slave (bytes)
|
2014-12-23 15:31:20 +01:00
|
|
|
system.membus.snoops 0 # Total snoops (count)
|
2015-07-03 16:15:03 +02:00
|
|
|
system.membus.snoop_fanout::samples 927615 # Request fanout histogram
|
2014-12-23 15:31:20 +01:00
|
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
2015-07-03 16:15:03 +02:00
|
|
|
system.membus.snoop_fanout::0 927615 100.00% 100.00% # Request fanout histogram
|
2014-12-23 15:31:20 +01:00
|
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
2015-07-03 16:15:03 +02:00
|
|
|
system.membus.snoop_fanout::total 927615 # Request fanout histogram
|
|
|
|
|
system.membus.reqLayer0.occupancy 2233739536 # Layer occupancy (ticks)
|
2015-03-02 11:04:20 +01:00
|
|
|
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
2015-07-03 16:15:03 +02:00
|
|
|
system.membus.respLayer1.occupancy 2422494891 # Layer occupancy (ticks)
|
2015-04-30 05:35:23 +02:00
|
|
|
system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
|
2011-04-25 23:18:08 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
