sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity
gem5/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt

1044 lines
119 KiB
Plaintext
Raw Normal View History

stats: update 20.parser o3 now that it works. realview-o3 works too.
2011-04-25 23:18:08 +02:00
---------- Begin Simulation Statistics ----------
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
sim_seconds 0.417785 # Number of seconds simulated
sim_ticks 417784645500 # Number of ticks simulated
final_tick 417784645500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
stats: update 20.parser o3 now that it works. realview-o3 works too.
2011-04-25 23:18:08 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
host_inst_rate 77548 # Simulator instruction rate (inst/s)
host_op_rate 143396 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 39181823 # Simulator tick rate (ticks/s)
host_mem_usage 423644 # Number of bytes of host memory used
host_seconds 10662.72 # Real time elapsed on the host
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
sim_insts 826877109 # Number of instructions simulated
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
sim_ops 1528988701 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.bytes_read::cpu.inst 225536 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24536320 # Number of bytes read from this memory
system.physmem.bytes_read::total 24761856 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 225536 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 225536 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 18818176 # Number of bytes written to this memory
system.physmem.bytes_written::total 18818176 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 3524 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 383380 # Number of read requests responded to by this memory
system.physmem.num_reads::total 386904 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 294034 # Number of write requests responded to by this memory
system.physmem.num_writes::total 294034 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 539838 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 58729588 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 59269426 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 539838 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 539838 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 45042766 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 45042766 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 45042766 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 539838 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 58729588 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 104312192 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 386904 # Number of read requests accepted
system.physmem.writeReqs 294034 # Number of write requests accepted
system.physmem.readBursts 386904 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 294034 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 24739840 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 22016 # Total number of bytes read from write queue
system.physmem.bytesWritten 18816320 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 24761856 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 18818176 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 344 # Number of DRAM read bursts serviced by the write queue
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.neitherReadNorWriteReqs 194832 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 24113 # Per bank write bursts
system.physmem.perBankRdBursts::1 26506 # Per bank write bursts
system.physmem.perBankRdBursts::2 24704 # Per bank write bursts
system.physmem.perBankRdBursts::3 24585 # Per bank write bursts
system.physmem.perBankRdBursts::4 23284 # Per bank write bursts
system.physmem.perBankRdBursts::5 23758 # Per bank write bursts
system.physmem.perBankRdBursts::6 24455 # Per bank write bursts
system.physmem.perBankRdBursts::7 24304 # Per bank write bursts
system.physmem.perBankRdBursts::8 23622 # Per bank write bursts
system.physmem.perBankRdBursts::9 23951 # Per bank write bursts
system.physmem.perBankRdBursts::10 24786 # Per bank write bursts
stats: x86: changes due to recent patches The change in 20.parser is from new x87 instructions. The change to pc-o3-timing is not clear to me. It seems that this test might be invoking some undefined behavior.
2015-04-14 18:01:11 +02:00
system.physmem.perBankRdBursts::11 24077 # Per bank write bursts
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.perBankRdBursts::12 23364 # Per bank write bursts
system.physmem.perBankRdBursts::13 22990 # Per bank write bursts
system.physmem.perBankRdBursts::14 24090 # Per bank write bursts
system.physmem.perBankRdBursts::15 23971 # Per bank write bursts
system.physmem.perBankWrBursts::0 18545 # Per bank write bursts
system.physmem.perBankWrBursts::1 19845 # Per bank write bursts
system.physmem.perBankWrBursts::2 18943 # Per bank write bursts
system.physmem.perBankWrBursts::3 18938 # Per bank write bursts
system.physmem.perBankWrBursts::4 18040 # Per bank write bursts
system.physmem.perBankWrBursts::5 18456 # Per bank write bursts
system.physmem.perBankWrBursts::6 18996 # Per bank write bursts
system.physmem.perBankWrBursts::7 18987 # Per bank write bursts
system.physmem.perBankWrBursts::8 18549 # Per bank write bursts
system.physmem.perBankWrBursts::9 18172 # Per bank write bursts
system.physmem.perBankWrBursts::10 18834 # Per bank write bursts
system.physmem.perBankWrBursts::11 17732 # Per bank write bursts
system.physmem.perBankWrBursts::12 17374 # Per bank write bursts
system.physmem.perBankWrBursts::13 16972 # Per bank write bursts
system.physmem.perBankWrBursts::14 17820 # Per bank write bursts
system.physmem.perBankWrBursts::15 17802 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.totGap 417784619000 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.readPktSize::6 386904 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.writePktSize::6 294034 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 381510 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 4656 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 343 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 42 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.wrQLenPdf::15 6151 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 6574 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 16911 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 17474 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 17558 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 17562 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 17584 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 17583 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 17630 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 17652 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 17624 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 17632 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 17742 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 17647 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 17645 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 17830 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 17528 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 17474 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 27 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 20 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 21 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.bytesPerActivate::samples 147384 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 295.518428 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 174.412890 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 322.590500 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 54886 37.24% 37.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 39792 27.00% 64.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 13719 9.31% 73.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 7560 5.13% 78.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 5573 3.78% 82.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 3862 2.62% 85.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 3103 2.11% 87.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 2674 1.81% 89.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 16215 11.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 147384 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 17444 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 22.159252 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 209.918601 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 17431 99.93% 99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.97% # Reads before turning the bus around for writes
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.rdPerTurnAround::total 17444 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 17444 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.854219 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.780353 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 2.660093 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 17244 98.85% 98.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 141 0.81% 99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 26 0.15% 99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 11 0.06% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 5 0.03% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 3 0.02% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 3 0.02% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 1 0.01% 99.96% # Writes before turning the bus around for reads
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.wrPerTurnAround::76-79 1 0.01% 99.97% # Writes before turning the bus around for reads
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.wrPerTurnAround::80-83 2 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 17444 # Writes before turning the bus around for reads
system.physmem.totQLat 4274781750 # Total ticks spent queuing
system.physmem.totMemAccLat 11522781750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1932800000 # Total ticks spent in databus transfers
system.physmem.avgQLat 11058.52 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 29808.52 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 59.22 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 45.04 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 59.27 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 45.04 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.busUtil 0.81 # Data bus utilization in percentage
system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 21.29 # Average write queue length when enqueuing
system.physmem.readRowHits 318043 # Number of row buffer hits during reads
system.physmem.writeRowHits 215127 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.28 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 73.16 # Row buffer hit rate for writes
system.physmem.avgGap 613542.82 # Average gap between requests
system.physmem.pageHitRate 78.34 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 567476280 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 309634875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1526389800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 976691520 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 27287295360 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 63728995635 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 194764938000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 289161421470 # Total energy per rank (pJ)
system.physmem_0.averagePower 692.139218 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 323446024000 # Time in different power states
system.physmem_0.memoryStateTime::REF 13950560000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem_0.memoryStateTime::ACT 80384174500 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem_1.actEnergy 546399000 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 298134375 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1488177600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 928104480 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 27287295360 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 61807042845 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 196450861500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 288806015160 # Total energy per rank (pJ)
system.physmem_1.averagePower 691.288514 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 326265955250 # Time in different power states
system.physmem_1.memoryStateTime::REF 13950560000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem_1.memoryStateTime::ACT 77563900250 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.branchPred.lookups 230228501 # Number of BP lookups
system.cpu.branchPred.condPredicted 230228501 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 9739021 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 131459692 # Number of BTB lookups
system.cpu.branchPred.BTBHits 128773186 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.branchPred.BTBHitPct 97.956403 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 27739164 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 1472550 # Number of incorrect RAS predictions.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.workload.num_syscalls 551 # Number of system calls
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.numCycles 835569292 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.fetch.icacheStallCycles 185184379 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1269166320 # Number of instructions fetch has processed
system.cpu.fetch.Branches 230228501 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 156512350 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 639147953 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 20213743 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 511 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 99253 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 822297 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 1772 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 179484418 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 2740851 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 7 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 835363066 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.826562 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.382493 # Number of instructions fetched each cycle (Total)
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.fetch.rateDist::0 427868247 51.22% 51.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 33702021 4.03% 55.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 32929710 3.94% 59.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 33265996 3.98% 63.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 27012416 3.23% 66.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 27748723 3.32% 69.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 36992796 4.43% 74.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 33648824 4.03% 78.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 182194333 21.81% 100.00% # Number of instructions fetched each cycle (Total)
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.fetch.rateDist::total 835363066 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.275535 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.518924 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 127510375 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 375947418 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 240571925 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 81226477 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 10106871 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 2225382694 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 10106871 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 159640008 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 160513488 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 42854 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 285557624 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 219502221 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2175351414 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 185986 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 136028392 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 24255750 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 49096014 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 2279465980 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 5501874168 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3499442561 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 66867 # Number of floating rename lookups
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.rename.UndoneMaps 665425126 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 3167 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2999 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 415602419 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 528341229 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 209838821 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 239501304 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 72157646 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2101036293 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 25395 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1826926557 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 429463 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 572072987 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 974001425 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 24843 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 835363066 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.186985 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.073368 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.iq.issued_per_cycle::0 255962202 30.64% 30.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 125607638 15.04% 45.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 118770145 14.22% 59.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 111086257 13.30% 73.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 92824001 11.11% 84.30% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 61460839 7.36% 91.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 43056890 5.15% 96.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 19182433 2.30% 99.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 7412661 0.89% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.iq.issued_per_cycle::total 835363066 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.iq.fu_full::IntAlu 11317596 42.46% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 12272214 46.05% 88.51% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 3062486 11.49% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.iq.FU_type_0::No_OpClass 2719434 0.15% 0.15% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1211207278 66.30% 66.45% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 389699 0.02% 66.47% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 3880989 0.21% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 135 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 39 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 410 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 435021653 23.81% 90.49% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 173706920 9.51% 100.00% # Type of FU issued
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.iq.FU_type_0::total 1826926557 # Type of FU issued
system.cpu.iq.rate 2.186445 # Inst issue rate
system.cpu.iq.fu_busy_cnt 26652296 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.014589 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4516265766 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2673396604 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1796798251 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 32173 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 70520 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 7153 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1850844448 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 14971 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 185549711 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 144242393 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 210251 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 386532 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 60678635 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 19153 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 1029 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.iew.iewSquashCycles 10106871 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 107291908 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 6438859 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2101061688 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 392799 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 528344550 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 209838821 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 7385 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1906737 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 3653179 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 386532 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 5738958 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 4581595 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 10320553 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1805492449 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 428838978 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 21434108 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.iew.exec_refs 598981338 # number of memory reference insts executed
system.cpu.iew.exec_branches 171787473 # Number of branches executed
system.cpu.iew.exec_stores 170142360 # Number of stores executed
system.cpu.iew.exec_rate 2.160793 # Inst execution rate
system.cpu.iew.wb_sent 1802094257 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1796805404 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1368063103 # num instructions producing a value
system.cpu.iew.wb_consumers 2090238527 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.iew.wb_rate 2.150397 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.654501 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.commit.commitSquashedInsts 572152437 # The number of squashed insts skipped by commit
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.commit.branchMispredicts 9826757 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 757699482 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.017936 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.547497 # Number of insts commited each cycle
stats: update 20.parser o3 now that it works. realview-o3 works too.
2011-04-25 23:18:08 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.commit.committed_per_cycle::0 289066041 38.15% 38.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 175144894 23.12% 61.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 57411271 7.58% 68.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 86235215 11.38% 80.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 27150149 3.58% 83.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 27136057 3.58% 87.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 9784065 1.29% 88.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 8843971 1.17% 89.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 76927819 10.15% 100.00% # Number of insts commited each cycle
stats: update 20.parser o3 now that it works. realview-o3 works too.
2011-04-25 23:18:08 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.commit.committed_per_cycle::total 757699482 # Number of insts commited each cycle
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.committedInsts 826877109 # Number of instructions committed
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.commit.refs 533262343 # Number of memory references committed
system.cpu.commit.loads 384102157 # Number of loads committed
stats: update 20.parser o3 now that it works. realview-o3 works too.
2011-04-25 23:18:08 +02:00
system.cpu.commit.membars 0 # Number of memory barriers committed
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.branches 149758583 # Number of branches committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
test: update stats Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses.
2013-10-16 16:44:12 +02:00
system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions.
x86, regressions: updates stats This is due to op class, function call, walker patches.
2013-05-21 18:41:27 +02:00
system.cpu.commit.function_calls 17673145 # Number of function calls committed.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 1819099 0.12% 0.12% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 989721889 64.73% 64.85% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.87% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 3878536 0.25% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.commit.bw_lim_events 76927819 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 2781912801 # The number of ROB reads
system.cpu.rob.rob_writes 4280130406 # The number of ROB writes
system.cpu.timesIdled 2299 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 206226 # Total number of cycles that the CPU has spent unscheduled due to idling
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts 826877109 # Number of Instructions Simulated
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.cpi 1.010512 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.010512 # CPI: Total CPI of All Threads
system.cpu.ipc 0.989597 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.989597 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 2761971319 # number of integer regfile reads
system.cpu.int_regfile_writes 1465030124 # number of integer regfile writes
system.cpu.fp_regfile_reads 7481 # number of floating regfile reads
system.cpu.fp_regfile_writes 493 # number of floating regfile writes
system.cpu.cc_regfile_reads 600902917 # number of cc regfile reads
system.cpu.cc_regfile_writes 409659635 # number of cc regfile writes
system.cpu.misc_regfile_reads 990136590 # number of misc regfile reads
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.dcache.tags.replacements 2534249 # number of replacements
system.cpu.dcache.tags.tagsinuse 4087.994933 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 387820460 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2538345 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 152.784771 # Average number of references to valid blocks.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.warmup_cycle 1688557250 # Cycle when the warmup percentage was hit.
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.994933 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.998046 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.998046 # Average percentage of cache occupancy
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 869 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3173 # Occupied blocks per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.dcache.tags.tag_accesses 784768509 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 784768509 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 239165062 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 239165062 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148173846 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 148173846 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 387338908 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 387338908 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 387338908 # number of overall hits
system.cpu.dcache.overall_hits::total 387338908 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2789818 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2789818 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 986356 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 986356 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 3776174 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3776174 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3776174 # number of overall misses
system.cpu.dcache.overall_misses::total 3776174 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 60126724251 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 60126724251 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 31294703774 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 31294703774 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 91421428025 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 91421428025 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 91421428025 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 91421428025 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 241954880 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 241954880 # number of ReadReq accesses(hits+misses)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.dcache.demand_accesses::cpu.data 391115082 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 391115082 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 391115082 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 391115082 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011530 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.011530 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006613 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.006613 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.009655 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.009655 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.009655 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.009655 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21552.203137 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 21552.203137 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31727.595081 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31727.595081 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24210.067657 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 24210.067657 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24210.067657 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 24210.067657 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 10621 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 71 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1078 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 5 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.852505 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 14.200000 # average number of cycles each access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.dcache.writebacks::writebacks 2332976 # number of writebacks
system.cpu.dcache.writebacks::total 2332976 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1022764 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1022764 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18373 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 18373 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1041137 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1041137 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1041137 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1041137 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767054 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1767054 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 967983 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 967983 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2735037 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2735037 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2735037 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2735037 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32779636252 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 32779636252 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29507402723 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 29507402723 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62287038975 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 62287038975 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62287038975 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 62287038975 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007303 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007303 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006490 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006490 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006993 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.006993 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006993 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006993 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18550.443989 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18550.443989 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30483.389401 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30483.389401 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22773.746379 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22773.746379 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22773.746379 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22773.746379 # average overall mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.icache.tags.replacements 7023 # number of replacements
system.cpu.icache.tags.tagsinuse 1053.963479 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 179273130 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 8620 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 20797.346868 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.icache.tags.occ_blocks::cpu.inst 1053.963479 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.514631 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.514631 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1597 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 319 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1155 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.779785 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 359174294 # Number of tag accesses
system.cpu.icache.tags.data_accesses 359174294 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 179276307 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 179276307 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 179276307 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 179276307 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 179276307 # number of overall hits
system.cpu.icache.overall_hits::total 179276307 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 208110 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 208110 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 208110 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 208110 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 208110 # number of overall misses
system.cpu.icache.overall_misses::total 208110 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1327923993 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 1327923993 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 1327923993 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 1327923993 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 1327923993 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 1327923993 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 179484417 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 179484417 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 179484417 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 179484417 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 179484417 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 179484417 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001159 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.001159 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.001159 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.001159 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001159 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001159 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6380.875465 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 6380.875465 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 6380.875465 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 6380.875465 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 6380.875465 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 6380.875465 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 695 # number of cycles access was blocked
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 57.916667 # average number of cycles each access was blocked
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2649 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 2649 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 2649 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 2649 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 2649 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 2649 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205461 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 205461 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 205461 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 205461 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 205461 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 205461 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 892683754 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 892683754 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 892683754 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 892683754 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 892683754 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 892683754 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001145 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001145 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001145 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.001145 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001145 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.001145 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4344.784431 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4344.784431 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4344.784431 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 4344.784431 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4344.784431 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 4344.784431 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.l2cache.tags.replacements 354223 # number of replacements
system.cpu.l2cache.tags.tagsinuse 29619.061304 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3704244 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 386583 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 9.582015 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 197893481000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 21085.370146 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 251.812049 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 8281.879109 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.643474 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007685 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.252743 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.903902 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id
stats: x86: changes due to recent patches The change in 20.parser is from new x87 instructions. The change to pc-o3-timing is not clear to me. It seems that this test might be invoking some undefined behavior.
2015-04-14 18:01:11 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 242 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13363 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18671 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 41773644 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 41773644 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 5119 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1590451 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1595570 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 2332976 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 2332976 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1900 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 1900 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 564474 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 564474 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 5119 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 2154925 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2160044 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 5119 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 2154925 # number of overall hits
system.cpu.l2cache.overall_hits::total 2160044 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3526 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 176410 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 179936 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 194792 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 194792 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 207010 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 207010 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3526 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 383420 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 386946 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3526 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 383420 # number of overall misses
system.cpu.l2cache.overall_misses::total 386946 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 288437750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14275708250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 14564146000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 12898587 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 12898587 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16427155710 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 16427155710 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 288437750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 30702863960 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 30991301710 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 288437750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 30702863960 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 30991301710 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 8645 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1766861 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1775506 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 2332976 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 2332976 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 196692 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 196692 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 771484 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 771484 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 8645 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2538345 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2546990 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 8645 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2538345 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2546990 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.407866 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099844 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.101344 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990340 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990340 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268327 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.268327 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.407866 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.151051 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.151923 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.407866 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.151051 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.151923 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81803.105502 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80923.463806 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 80940.701138 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 66.217232 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 66.217232 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79354.406599 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79354.406599 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81803.105502 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80076.323509 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 80092.058608 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81803.105502 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80076.323509 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 80092.058608 # average overall miss latency
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.l2cache.writebacks::writebacks 294034 # number of writebacks
system.cpu.l2cache.writebacks::total 294034 # number of writebacks
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3525 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 176410 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 179935 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 194792 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 194792 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207010 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 207010 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3525 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 383420 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 386945 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3525 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 383420 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 386945 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 244319250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12068297250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12312616500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3517284221 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3517284221 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13838517790 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13838517790 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 244319250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25906815040 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 26151134290 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 244319250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25906815040 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 26151134290 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.407750 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099844 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101343 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990340 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990340 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268327 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268327 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.407750 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151051 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.151922 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.407750 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151051 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.151922 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69310.425532 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68410.505357 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68428.135160 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18056.615369 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18056.615369 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66849.513502 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66849.513502 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69310.425532 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67567.719576 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67583.595317 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69310.425532 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67567.719576 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67583.595317 # average overall mshr miss latency
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.toL2Bus.trans_dist::ReadReq 1972322 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 1972321 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 2332976 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 196692 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 196692 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 771484 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 771484 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 214105 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7803050 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 8017155 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 553216 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311764544 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 312317760 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 196816 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 5273474 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.toL2Bus.snoop_fanout::3 5273474 100.00% 100.00% # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.toL2Bus.snoop_fanout::total 5273474 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4998709391 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 308726995 # Layer occupancy (ticks)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 3988953025 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
system.membus.trans_dist::ReadReq 179934 # Transaction distribution
system.membus.trans_dist::ReadResp 179934 # Transaction distribution
system.membus.trans_dist::Writeback 294034 # Transaction distribution
system.membus.trans_dist::UpgradeReq 194832 # Transaction distribution
system.membus.trans_dist::UpgradeResp 194832 # Transaction distribution
system.membus.trans_dist::ReadExReq 206970 # Transaction distribution
system.membus.trans_dist::ReadExResp 206970 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1457506 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1457506 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1457506 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43580032 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43580032 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 43580032 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.membus.snoop_fanout::samples 875770 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.membus.snoop_fanout::0 875770 100.00% 100.00% # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.membus.snoop_fanout::total 875770 # Request fanout histogram
system.membus.reqLayer0.occupancy 2246779030 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.membus.respLayer1.occupancy 2437213959 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
stats: update 20.parser o3 now that it works. realview-o3 works too.
2011-04-25 23:18:08 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink