2011-02-07 10:23:16 +01:00
---------- Begin Simulation Statistics ----------
2015-12-05 01:11:25 +01:00
sim_seconds 5.194947 # Number of seconds simulated
sim_ticks 5194947216500 # Number of ticks simulated
final_tick 5194947216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-11-05 21:32:23 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2015-12-12 23:27:38 +01:00
host_inst_rate 409072 # Simulator instruction rate (inst/s)
host_op_rate 788480 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 16545970820 # Simulator tick rate (ticks/s)
host_mem_usage 604904 # Number of bytes of host memory used
host_seconds 313.97 # Real time elapsed on the host
2015-11-06 09:26:50 +01:00
sim_insts 128436556 # Number of instructions simulated
2015-12-05 01:11:25 +01:00
sim_ops 247559476 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2015-11-06 09:26:50 +01:00
system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
2012-06-29 17:19:03 +02:00
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
2015-11-06 09:26:50 +01:00
system.physmem.bytes_read::cpu.inst 821184 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9031104 # Number of bytes read from this memory
2014-11-17 09:16:36 +01:00
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
2015-11-06 09:26:50 +01:00
system.physmem.bytes_read::total 9881024 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 821184 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 821184 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8151488 # Number of bytes written to this memory
system.physmem.bytes_written::total 8151488 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
2012-06-29 17:19:03 +02:00
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
2015-11-06 09:26:50 +01:00
system.physmem.num_reads::cpu.inst 12831 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 141111 # Number of read requests responded to by this memory
2014-11-17 09:16:36 +01:00
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
2015-11-06 09:26:50 +01:00
system.physmem.num_reads::total 154391 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 127367 # Number of write requests responded to by this memory
system.physmem.num_writes::total 127367 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s)
2012-06-29 17:19:03 +02:00
system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
2015-12-05 01:11:25 +01:00
system.physmem.bw_read::cpu.inst 158074 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1738440 # Total read bandwidth from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_read::pc.south_bridge.ide 5458 # Total read bandwidth from this memory (bytes/s)
2015-12-05 01:11:25 +01:00
system.physmem.bw_read::total 1902045 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 158074 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 158074 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1569119 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1569119 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1569119 # Total bandwidth to/from this memory (bytes/s)
2015-11-06 09:26:50 +01:00
system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s)
2012-06-29 17:19:03 +02:00
system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
2015-12-05 01:11:25 +01:00
system.physmem.bw_total::cpu.inst 158074 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1738440 # Total bandwidth to/from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_total::pc.south_bridge.ide 5458 # Total bandwidth to/from this memory (bytes/s)
2015-12-05 01:11:25 +01:00
system.physmem.bw_total::total 3471164 # Total bandwidth to/from this memory (bytes/s)
2015-11-06 09:26:50 +01:00
system.physmem.readReqs 154391 # Number of read requests accepted
system.physmem.writeReqs 127367 # Number of write requests accepted
system.physmem.readBursts 154391 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 127367 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 9871424 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue
system.physmem.bytesWritten 8149376 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 9881024 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 8151488 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue
2015-07-03 16:15:03 +02:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
2015-11-06 09:26:50 +01:00
system.physmem.neitherReadNorWriteReqs 55287 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 10087 # Per bank write bursts
system.physmem.perBankRdBursts::1 9529 # Per bank write bursts
system.physmem.perBankRdBursts::2 9814 # Per bank write bursts
system.physmem.perBankRdBursts::3 9652 # Per bank write bursts
system.physmem.perBankRdBursts::4 10130 # Per bank write bursts
system.physmem.perBankRdBursts::5 9950 # Per bank write bursts
system.physmem.perBankRdBursts::6 9317 # Per bank write bursts
system.physmem.perBankRdBursts::7 9200 # Per bank write bursts
system.physmem.perBankRdBursts::8 8918 # Per bank write bursts
system.physmem.perBankRdBursts::9 9357 # Per bank write bursts
system.physmem.perBankRdBursts::10 9066 # Per bank write bursts
system.physmem.perBankRdBursts::11 9331 # Per bank write bursts
system.physmem.perBankRdBursts::12 9713 # Per bank write bursts
system.physmem.perBankRdBursts::13 9915 # Per bank write bursts
system.physmem.perBankRdBursts::14 10131 # Per bank write bursts
system.physmem.perBankRdBursts::15 10131 # Per bank write bursts
system.physmem.perBankWrBursts::0 8252 # Per bank write bursts
system.physmem.perBankWrBursts::1 7742 # Per bank write bursts
system.physmem.perBankWrBursts::2 7578 # Per bank write bursts
system.physmem.perBankWrBursts::3 7566 # Per bank write bursts
system.physmem.perBankWrBursts::4 7987 # Per bank write bursts
system.physmem.perBankWrBursts::5 8326 # Per bank write bursts
system.physmem.perBankWrBursts::6 7980 # Per bank write bursts
system.physmem.perBankWrBursts::7 7858 # Per bank write bursts
system.physmem.perBankWrBursts::8 7446 # Per bank write bursts
system.physmem.perBankWrBursts::9 8118 # Per bank write bursts
system.physmem.perBankWrBursts::10 7706 # Per bank write bursts
system.physmem.perBankWrBursts::11 7948 # Per bank write bursts
system.physmem.perBankWrBursts::12 8417 # Per bank write bursts
system.physmem.perBankWrBursts::13 8510 # Per bank write bursts
system.physmem.perBankWrBursts::14 8023 # Per bank write bursts
system.physmem.perBankWrBursts::15 7877 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2015-11-06 09:26:50 +01:00
system.physmem.numWrRetry 2 # Number of times write queue was full causing retry
2015-12-05 01:11:25 +01:00
system.physmem.totGap 5194947155500 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2015-11-06 09:26:50 +01:00
system.physmem.readPktSize::6 154391 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2015-11-06 09:26:50 +01:00
system.physmem.writePktSize::6 127367 # Write request sizes (log2)
2015-12-05 01:11:25 +01:00
system.physmem.rdQLenPdf::0 151032 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 2782 # What read queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.rdQLenPdf::4 39 # What read queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 38 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 27 # What read queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 24 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
2014-09-03 13:42:59 +02:00
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.wrQLenPdf::15 2416 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2856 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 6275 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6125 # What write queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.wrQLenPdf::19 6693 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.wrQLenPdf::20 6750 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 8169 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 7450 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 8822 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 9011 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 8677 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 10497 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7589 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 6906 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7071 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6415 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6214 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 6089 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 334 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 218 # What write queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.wrQLenPdf::35 191 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.wrQLenPdf::36 167 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 179 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 167 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 131 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 116 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 124 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 159 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 116 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 154 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 97 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 148 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 136 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 159 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 88 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 69 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 47 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.wrQLenPdf::58 16 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.wrQLenPdf::59 41 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 3 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 56850 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 316.988566 # Bytes accessed per row activation
2015-12-05 01:11:25 +01:00
system.physmem.bytesPerActivate::gmean 189.004327 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 329.313677 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 20115 35.38% 35.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 13762 24.21% 59.59% # Bytes accessed per row activation
2015-11-06 09:26:50 +01:00
system.physmem.bytesPerActivate::256-383 6339 11.15% 70.74% # Bytes accessed per row activation
2015-12-05 01:11:25 +01:00
system.physmem.bytesPerActivate::384-511 3489 6.14% 76.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2420 4.26% 81.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1597 2.81% 83.94% # Bytes accessed per row activation
2015-11-06 09:26:50 +01:00
system.physmem.bytesPerActivate::768-895 1162 2.04% 85.99% # Bytes accessed per row activation
2015-12-05 01:11:25 +01:00
system.physmem.bytesPerActivate::896-1023 977 1.72% 87.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 6989 12.29% 100.00% # Bytes accessed per row activation
2015-11-06 09:26:50 +01:00
system.physmem.bytesPerActivate::total 56850 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5891 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 26.179766 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 623.896687 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 5890 99.98% 99.98% # Reads before turning the bus around for writes
2014-09-03 13:42:59 +02:00
system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes
2015-11-06 09:26:50 +01:00
system.physmem.rdPerTurnAround::total 5891 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5891 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 21.615006 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 19.434725 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 14.404388 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 4837 82.11% 82.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 110 1.87% 83.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 36 0.61% 84.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 242 4.11% 88.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 18 0.31% 89.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 210 3.56% 92.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 69 1.17% 93.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 3 0.05% 93.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 13 0.22% 94.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 22 0.37% 94.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 8 0.14% 94.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 6 0.10% 94.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 244 4.14% 98.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 5 0.08% 98.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 4 0.07% 98.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 27 0.46% 99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 2 0.03% 99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 2 0.03% 99.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 1 0.02% 99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 2 0.03% 99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 1 0.02% 99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 2 0.03% 99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.02% 99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 18 0.31% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 1 0.02% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 1 0.02% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 1 0.02% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 2 0.03% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 3 0.05% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5891 # Writes before turning the bus around for reads
2015-12-05 01:11:25 +01:00
system.physmem.totQLat 1583291001 # Total ticks spent queuing
system.physmem.totMemAccLat 4475309751 # Total ticks spent from burst creation until serviced by the DRAM
2015-11-06 09:26:50 +01:00
system.physmem.totBusLat 771205000 # Total ticks spent in databus transfers
2015-12-05 01:11:25 +01:00
system.physmem.avgQLat 10265.05 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2015-12-05 01:11:25 +01:00
system.physmem.avgMemAccLat 29015.05 # Average memory access latency per DRAM burst
2015-11-06 09:26:50 +01:00
system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2012-10-25 19:14:42 +02:00
system.physmem.busUtil 0.03 # Data bus utilization in percentage
2014-09-03 13:42:59 +02:00
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
2015-03-02 11:04:20 +01:00
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
2014-09-03 13:42:59 +02:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
2015-11-06 09:26:50 +01:00
system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing
system.physmem.readRowHits 125535 # Number of row buffer hits during reads
system.physmem.writeRowHits 99190 # Number of row buffer hits during writes
system.physmem.readRowHitRate 81.39 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 77.88 # Row buffer hit rate for writes
2015-12-05 01:11:25 +01:00
system.physmem.avgGap 18437620.78 # Average gap between requests
2015-11-06 09:26:50 +01:00
system.physmem.pageHitRate 79.80 # Row buffer hit rate, read and write combined
2015-12-05 01:11:25 +01:00
system.physmem_0.actEnergy 210727440 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 114980250 # Energy for precharge commands per rank (pJ)
2015-11-06 09:26:50 +01:00
system.physmem_0.readEnergy 605896200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 410112720 # Energy for write commands per rank (pJ)
2015-12-05 01:11:25 +01:00
system.physmem_0.refreshEnergy 339308689200 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 137072684295 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 2996729192250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 3474452282355 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.813767 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 4985214188974 # Time in different power states
system.physmem_0.memoryStateTime::REF 173470440000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-12-05 01:11:25 +01:00
system.physmem_0.memoryStateTime::ACT 36262439776 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-12-05 01:11:25 +01:00
system.physmem_1.actEnergy 219058560 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 119526000 # Energy for precharge commands per rank (pJ)
2015-11-06 09:26:50 +01:00
system.physmem_1.readEnergy 597183600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 415011600 # Energy for write commands per rank (pJ)
2015-12-05 01:11:25 +01:00
system.physmem_1.refreshEnergy 339308689200 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 137519874945 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 2996336934750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 3474516278655 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.826083 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 4984554950984 # Time in different power states
system.physmem_1.memoryStateTime::REF 173470440000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-12-05 01:11:25 +01:00
system.physmem_1.memoryStateTime::ACT 36921702766 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
2015-12-05 01:11:25 +01:00
system.cpu.numCycles 10389894433 # number of cpu cycles simulated
2011-11-05 21:32:23 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-10-10 23:45:41 +02:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
2015-11-06 09:26:50 +01:00
system.cpu.committedInsts 128436556 # Number of instructions committed
2015-12-05 01:11:25 +01:00
system.cpu.committedOps 247559476 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 232158308 # Number of integer alu accesses
2015-01-11 01:06:43 +01:00
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
2015-11-06 09:26:50 +01:00
system.cpu.num_func_calls 2315823 # number of times a function call or return occured
2015-12-05 01:11:25 +01:00
system.cpu.num_conditional_control_insts 23152916 # number of instructions that are conditional controls
system.cpu.num_int_insts 232158308 # number of integer instructions
2015-01-11 01:06:43 +01:00
system.cpu.num_fp_insts 48 # number of float instructions
2015-12-05 01:11:25 +01:00
system.cpu.num_int_register_reads 434959182 # number of times the integer registers were read
system.cpu.num_int_register_writes 197962963 # number of times the integer registers were written
2015-01-11 01:06:43 +01:00
system.cpu.num_fp_register_reads 48 # number of times the floating registers were read
2011-11-05 21:32:23 +01:00
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
2015-12-05 01:11:25 +01:00
system.cpu.num_cc_register_reads 132872914 # number of times the CC registers were read
system.cpu.num_cc_register_writes 95460933 # number of times the CC registers were written
2015-11-06 09:26:50 +01:00
system.cpu.num_mem_refs 22321110 # number of memory refs
system.cpu.num_load_insts 13911495 # Number of load instructions
system.cpu.num_store_insts 8409615 # Number of store instructions
system.cpu.num_idle_cycles 9773995534.086119 # Number of idle cycles
2015-12-05 01:11:25 +01:00
system.cpu.num_busy_cycles 615898898.913881 # Number of busy cycles
system.cpu.not_idle_fraction 0.059279 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.940721 # Percentage of idle cycles
system.cpu.Branches 26327382 # Number of branches fetched
system.cpu.op_class::No_OpClass 172226 0.07% 0.07% # Class of executed instruction
2015-11-06 09:26:50 +01:00
system.cpu.op_class::IntAlu 224809718 90.81% 90.88% # Class of executed instruction
system.cpu.op_class::IntMult 140099 0.06% 90.94% # Class of executed instruction
2015-12-05 01:11:25 +01:00
system.cpu.op_class::IntDiv 122815 0.05% 90.99% # Class of executed instruction
2015-01-11 01:06:43 +01:00
system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::FloatCvt 16 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.99% # Class of executed instruction
2015-11-06 09:26:50 +01:00
system.cpu.op_class::MemRead 13906523 5.62% 96.60% # Class of executed instruction
system.cpu.op_class::MemWrite 8409615 3.40% 100.00% # Class of executed instruction
2014-05-10 00:58:50 +02:00
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
2015-12-05 01:11:25 +01:00
system.cpu.op_class::total 247561012 # Class of executed instruction
system.cpu.dcache.tags.replacements 1623700 # number of replacements
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.tagsinuse 511.995481 # Cycle average of tags in use
2015-12-05 01:11:25 +01:00
system.cpu.dcache.tags.total_refs 20139431 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1624212 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 12.399509 # Average number of references to valid blocks.
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.warmup_cycle 81561500 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 511.995481 # Average occupied blocks per requestor
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999991 # Average percentage of cache occupancy
2014-11-17 09:16:36 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
2014-11-17 09:16:36 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-12-05 01:11:25 +01:00
system.cpu.dcache.tags.tag_accesses 88718097 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 88718097 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 12002646 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 12002646 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8075476 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8075476 # number of WriteReq hits
2015-11-06 09:26:50 +01:00
system.cpu.dcache.SoftPFReq_hits::cpu.data 59092 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 59092 # number of SoftPFReq hits
2015-12-05 01:11:25 +01:00
system.cpu.dcache.demand_hits::cpu.data 20078122 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 20078122 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 20137214 # number of overall hits
system.cpu.dcache.overall_hits::total 20137214 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 907311 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 907311 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 326143 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 326143 # number of WriteReq misses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.SoftPFReq_misses::cpu.data 402797 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 402797 # number of SoftPFReq misses
2015-12-05 01:11:25 +01:00
system.cpu.dcache.demand_misses::cpu.data 1233454 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1233454 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1636251 # number of overall misses
system.cpu.dcache.overall_misses::total 1636251 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 13562069000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 13562069000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 18448528971 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 18448528971 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 32010597971 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 32010597971 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 32010597971 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 32010597971 # number of overall miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.dcache.ReadReq_accesses::cpu.data 12909957 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 12909957 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8401619 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8401619 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 461889 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 461889 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21311576 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21311576 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 21773465 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21773465 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070280 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.070280 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038819 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.038819 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872065 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.872065 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.057877 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.057877 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.075149 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.075149 # miss rate for overall accesses
2015-12-05 01:11:25 +01:00
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14947.541692 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14947.541692 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56565.767075 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 56565.767075 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 25951.999808 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 25951.999808 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19563.378706 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 19563.378706 # average overall miss latency
2015-11-06 09:26:50 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 18014 # number of cycles access was blocked
2014-11-17 09:16:36 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.dcache.blocked::no_mshrs 511 # number of cycles access was blocked
2014-11-17 09:16:36 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.252446 # average number of cycles each access was blocked
2014-11-17 09:16:36 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2015-12-05 01:11:25 +01:00
system.cpu.dcache.writebacks::writebacks 1540805 # number of writebacks
system.cpu.dcache.writebacks::total 1540805 # number of writebacks
2015-11-06 09:26:50 +01:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 287 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9476 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 9476 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 9763 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 9763 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 9763 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 9763 # number of overall MSHR hits
2015-12-05 01:11:25 +01:00
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 907024 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 907024 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316667 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 316667 # number of WriteReq MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402763 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 402763 # number of SoftPFReq MSHR misses
2015-12-05 01:11:25 +01:00
system.cpu.dcache.demand_mshr_misses::cpu.data 1223691 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1223691 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1626454 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1626454 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 546346 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 546346 # number of ReadReq MSHR uncacheable
2015-09-25 13:27:03 +02:00
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13920 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 13920 # number of WriteReq MSHR uncacheable
2015-11-06 09:26:50 +01:00
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 560266 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 560266 # number of overall MSHR uncacheable misses
2015-12-05 01:11:25 +01:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12652957000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 12652957000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17148864471 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 17148864471 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6516948000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6516948000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29801821471 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 29801821471 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36318769471 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 36318769471 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 95132083500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 95132083500 # number of ReadReq MSHR uncacheable cycles
2015-11-06 09:26:50 +01:00
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2786304500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2786304500 # number of WriteReq MSHR uncacheable cycles
2015-12-05 01:11:25 +01:00
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97918388000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 97918388000 # number of overall MSHR uncacheable cycles
2015-11-06 09:26:50 +01:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070258 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070258 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037691 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037691 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871991 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871991 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057419 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.057419 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074699 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.074699 # mshr miss rate for overall accesses
2015-12-05 01:11:25 +01:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13949.969350 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13949.969350 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54154.251851 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54154.251851 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16180.602488 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16180.602488 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24354.041560 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 24354.041560 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22330.031757 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22330.031757 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 174124.242696 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174124.242696 # average ReadReq mshr uncacheable latency
2015-11-06 09:26:50 +01:00
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200165.553161 # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200165.553161 # average WriteReq mshr uncacheable latency
2015-12-05 01:11:25 +01:00
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 174771.247943 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 174771.247943 # average overall mshr uncacheable latency
2014-11-17 09:16:36 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu.dtb_walker_cache.tags.replacements 7583 # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse 5.052194 # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs 13349 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs 7599 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs 1.756679 # Average number of references to valid blocks.
2015-12-05 01:11:25 +01:00
system.cpu.dtb_walker_cache.tags.warmup_cycle 5163358790000 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.052194 # Average occupied blocks per requestor
2015-09-25 13:27:03 +02:00
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315762 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315762 # Average percentage of cache occupancy
2015-11-06 09:26:50 +01:00
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id
2015-01-11 01:06:43 +01:00
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dtb_walker_cache.tags.tag_accesses 53077 # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses 53077 # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13349 # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 13349 # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13349 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 13349 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13349 # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 13349 # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8793 # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 8793 # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8793 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 8793 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8793 # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 8793 # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 96493000 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 96493000 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 96493000 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total 96493000 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 96493000 # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total 96493000 # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22142 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total 22142 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22142 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total 22142 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22142 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 22142 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.397119 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.397119 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.397119 # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.397119 # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.397119 # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.397119 # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10973.842830 # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10973.842830 # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10973.842830 # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10973.842830 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10973.842830 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10973.842830 # average overall miss latency
2014-11-17 09:16:36 +01:00
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.dtb_walker_cache.writebacks::writebacks 2984 # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total 2984 # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8793 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8793 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8793 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total 8793 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8793 # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total 8793 # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 87700000 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 87700000 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 87700000 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 87700000 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 87700000 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 87700000 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.397119 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.397119 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.397119 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.397119 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.397119 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.397119 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9973.842830 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9973.842830 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9973.842830 # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9973.842830 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9973.842830 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9973.842830 # average overall mshr miss latency
2014-11-17 09:16:36 +01:00
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.replacements 790533 # number of replacements
2015-12-05 01:11:25 +01:00
system.cpu.icache.tags.tagsinuse 510.213577 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 144635652 # Total number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.sampled_refs 791045 # Sample count of references to valid blocks.
2015-12-05 01:11:25 +01:00
system.cpu.icache.tags.avg_refs 182.841244 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 164551519500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 510.213577 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.996511 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.996511 # Average percentage of cache occupancy
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 292 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-12-05 01:11:25 +01:00
system.cpu.icache.tags.tag_accesses 146217756 # Number of tag accesses
system.cpu.icache.tags.data_accesses 146217756 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 144635652 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 144635652 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 144635652 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 144635652 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 144635652 # number of overall hits
system.cpu.icache.overall_hits::total 144635652 # number of overall hits
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_misses::cpu.inst 791052 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 791052 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 791052 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 791052 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 791052 # number of overall misses
system.cpu.icache.overall_misses::total 791052 # number of overall misses
2015-12-05 01:11:25 +01:00
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11851389500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 11851389500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 11851389500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 11851389500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 11851389500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 11851389500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 145426704 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 145426704 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 145426704 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 145426704 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 145426704 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 145426704 # number of overall (read+write) accesses
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005440 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.005440 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.005440 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.005440 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.005440 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.005440 # miss rate for overall accesses
2015-12-05 01:11:25 +01:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14981.808402 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14981.808402 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14981.808402 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14981.808402 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14981.808402 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14981.808402 # average overall miss latency
2011-11-05 21:32:23 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2011-11-05 21:32:23 +01:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.icache.writebacks::writebacks 790533 # number of writebacks
system.cpu.icache.writebacks::total 790533 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791052 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 791052 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 791052 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 791052 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 791052 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 791052 # number of overall MSHR misses
2015-12-05 01:11:25 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11060337500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 11060337500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11060337500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 11060337500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11060337500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 11060337500 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005440 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.005440 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.005440 # mshr miss rate for overall accesses
2015-12-05 01:11:25 +01:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13981.808402 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13981.808402 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13981.808402 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13981.808402 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13981.808402 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13981.808402 # average overall mshr miss latency
2011-11-05 21:32:23 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu.itb_walker_cache.tags.replacements 3383 # number of replacements
2015-12-05 01:11:25 +01:00
system.cpu.itb_walker_cache.tags.tagsinuse 3.069434 # Cycle average of tags in use
2015-11-06 09:26:50 +01:00
system.cpu.itb_walker_cache.tags.total_refs 7971 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs 3396 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs 2.347173 # Average number of references to valid blocks.
2015-12-05 01:11:25 +01:00
system.cpu.itb_walker_cache.tags.warmup_cycle 5168964583500 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.069434 # Average occupied blocks per requestor
2015-11-06 09:26:50 +01:00
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191840 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total 0.191840 # Average percentage of cache occupancy
2015-09-25 13:27:03 +02:00
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id
2015-01-11 01:06:43 +01:00
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
2015-07-03 16:15:03 +02:00
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id
2015-11-06 09:26:50 +01:00
system.cpu.itb_walker_cache.tags.tag_accesses 28685 # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses 28685 # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7970 # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total 7970 # number of ReadReq hits
2012-02-12 23:07:43 +01:00
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
2015-11-06 09:26:50 +01:00
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7972 # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total 7972 # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7972 # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total 7972 # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4247 # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total 4247 # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4247 # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total 4247 # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4247 # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total 4247 # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 44886000 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total 44886000 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 44886000 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total 44886000 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 44886000 # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total 44886000 # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12217 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total 12217 # number of ReadReq accesses(hits+misses)
2012-02-12 23:07:43 +01:00
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
2015-11-06 09:26:50 +01:00
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12219 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total 12219 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12219 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total 12219 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.347630 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.347630 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.347573 # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total 0.347573 # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.347573 # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total 0.347573 # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10568.872145 # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10568.872145 # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10568.872145 # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10568.872145 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10568.872145 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10568.872145 # average overall miss latency
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.itb_walker_cache.writebacks::writebacks 773 # number of writebacks
system.cpu.itb_walker_cache.writebacks::total 773 # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4247 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4247 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4247 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total 4247 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4247 # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total 4247 # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 40639000 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 40639000 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 40639000 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 40639000 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 40639000 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 40639000 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.347630 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.347630 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.347573 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.347573 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.347573 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.347573 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9568.872145 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9568.872145 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9568.872145 # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9568.872145 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9568.872145 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9568.872145 # average overall mshr miss latency
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.replacements 87285 # number of replacements
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.tags.tagsinuse 64590.437600 # Cycle average of tags in use
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.total_refs 4366421 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 151981 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 28.730045 # Average number of references to valid blocks.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 50117.146585 # Average occupied blocks per requestor
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006346 # Average occupied blocks per requestor
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.146882 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3409.592137 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 11063.545650 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.764727 # Average percentage of cache occupancy
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052026 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.168816 # Average percentage of cache occupancy
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.tags.occ_percent::total 0.985572 # Average percentage of cache occupancy
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 64696 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2800 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5473 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56265 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987183 # Percentage of cache occupancy per task id
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.tags.tag_accesses 39229727 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 39229727 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 1544562 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 1544562 # number of WritebackDirty hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.WritebackClean_hits::writebacks 790520 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 790520 # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 320 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 320 # number of UpgradeReq hits
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 200932 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 200932 # number of ReadExReq hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 778207 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 778207 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6472 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 2856 # number of ReadSharedReq hits
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1280545 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 1289873 # number of ReadSharedReq hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6472 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 2856 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 778207 # number of demand (read+write) hits
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.demand_hits::cpu.data 1481477 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2269012 # number of demand (read+write) hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6472 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 2856 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 778207 # number of overall hits
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.overall_hits::cpu.data 1481477 # number of overall hits
system.cpu.l2cache.overall_hits::total 2269012 # number of overall hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1406 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 1406 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 113512 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 113512 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 12832 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 12832 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 1 # number of ReadSharedReq misses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 28494 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 28500 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_misses::cpu.inst 12832 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 142006 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 154844 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_misses::cpu.inst 12832 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 142006 # number of overall misses
system.cpu.l2cache.overall_misses::total 154844 # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 53960000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 53960000 # number of UpgradeReq miss cycles
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14442540500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 14442540500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1692530000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 1692530000 # number of ReadCleanReq miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 147000 # number of ReadSharedReq miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 637500 # number of ReadSharedReq miss cycles
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3749093000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 3749877500 # number of ReadSharedReq miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 147000 # number of demand (read+write) miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 637500 # number of demand (read+write) miss cycles
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.inst 1692530000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 18191633500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 19884948000 # number of demand (read+write) miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 147000 # number of overall miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 637500 # number of overall miss cycles
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.overall_miss_latency::cpu.inst 1692530000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 18191633500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 19884948000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 1544562 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 1544562 # number of WritebackDirty accesses(hits+misses)
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.WritebackClean_accesses::writebacks 790520 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 790520 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1726 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 1726 # number of UpgradeReq accesses(hits+misses)
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314444 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 314444 # number of ReadExReq accesses(hits+misses)
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 791039 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 791039 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 6473 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 2861 # number of ReadSharedReq accesses(hits+misses)
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1309039 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 1318373 # number of ReadSharedReq accesses(hits+misses)
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6473 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2861 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 791039 # number of demand (read+write) accesses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.demand_accesses::cpu.data 1623483 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2423856 # number of demand (read+write) accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6473 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2861 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 791039 # number of overall (read+write) accesses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.overall_accesses::cpu.data 1623483 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2423856 # number of overall (read+write) accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.814600 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.814600 # miss rate for UpgradeReq accesses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.360993 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.360993 # miss rate for ReadExReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016222 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016222 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000154 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.001748 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.021767 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.021618 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000154 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001748 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016222 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.087470 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.063883 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000154 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001748 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016222 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.087470 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.063883 # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 38378.378378 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 38378.378378 # average UpgradeReq miss latency
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127233.600853 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127233.600853 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131899.158354 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131899.158354 # average ReadCleanReq miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 147000 # average ReadSharedReq miss latency
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 127500 # average ReadSharedReq miss latency
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 131574.822770 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 131574.649123 # average ReadSharedReq miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 147000 # average overall miss latency
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 127500 # average overall miss latency
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131899.158354 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128104.682197 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 128419.234843 # average overall miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 147000 # average overall miss latency
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 127500 # average overall miss latency
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131899.158354 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128104.682197 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 128419.234843 # average overall miss latency
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.writebacks::writebacks 80700 # number of writebacks
system.cpu.l2cache.writebacks::total 80700 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1406 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1406 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113512 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 113512 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 12832 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 12832 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 1 # number of ReadSharedReq MSHR misses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 5 # number of ReadSharedReq MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 28494 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 28500 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 12832 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 142006 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 154844 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 12832 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 142006 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 154844 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 546346 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 546346 # number of ReadReq MSHR uncacheable
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13920 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13920 # number of WriteReq MSHR uncacheable
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 560266 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 560266 # number of overall MSHR uncacheable misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 100407500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 100407500 # number of UpgradeReq MSHR miss cycles
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13307420500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13307420500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1564210000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1564210000 # number of ReadCleanReq MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 137000 # number of ReadSharedReq MSHR miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 587500 # number of ReadSharedReq MSHR miss cycles
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3464153000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3464877500 # number of ReadSharedReq MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 137000 # number of demand (read+write) MSHR miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 587500 # number of demand (read+write) MSHR miss cycles
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1564210000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16771573500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 18336508000 # number of demand (read+write) MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 137000 # number of overall MSHR miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 587500 # number of overall MSHR miss cycles
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1564210000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16771573500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 18336508000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88302753500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88302753500 # number of ReadReq MSHR uncacheable cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2626222500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2626222500 # number of WriteReq MSHR uncacheable cycles
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 90928976000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 90928976000 # number of overall MSHR uncacheable cycles
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.814600 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.814600 # mshr miss rate for UpgradeReq accesses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.360993 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.360993 # mshr miss rate for ReadExReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016222 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016222 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000154 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.001748 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.021767 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.021618 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000154 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001748 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016222 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087470 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.063883 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000154 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001748 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016222 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087470 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063883 # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71413.584637 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71413.584637 # average UpgradeReq mshr miss latency
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117233.600853 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117233.600853 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121899.158354 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121899.158354 # average ReadCleanReq mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 137000 # average ReadSharedReq mshr miss latency
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 117500 # average ReadSharedReq mshr miss latency
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 121574.822770 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 121574.649123 # average ReadSharedReq mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 137000 # average overall mshr miss latency
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121899.158354 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118104.682197 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118419.234843 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 137000 # average overall mshr miss latency
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121899.158354 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118104.682197 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118419.234843 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161624.233544 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161624.233544 # average ReadReq mshr uncacheable latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188665.409483 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188665.409483 # average WriteReq mshr uncacheable latency
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162296.080790 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 162296.080790 # average overall mshr uncacheable latency
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.snoop_filter.tot_requests 4855758 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425140 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11068 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 1020 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1020 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::ReadReq 546346 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.trans_dist::ReadResp 2660536 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.trans_dist::WriteReq 13920 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 13920 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.trans_dist::WritebackDirty 1671931 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::WritebackClean 790520 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 91754 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2230 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2230 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.trans_dist::ReadExReq 314450 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 314450 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::ReadCleanReq 791052 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1323669 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.trans_dist::MessageReq 1654 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2372611 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5995599 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8612 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19573 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.pkt_count::total 8396395 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 101219776 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204103080 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 232576 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 605248 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.pkt_size::total 306160680 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoops 189298 # Total snoops (count)
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.snoop_fanout::samples 3174835 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::mean 0.004492 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.077863 # Request fanout histogram
2014-11-17 09:16:36 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.snoop_fanout::0 3163101 99.63% 99.63% # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::1 9208 0.29% 99.92% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 2526 0.08% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
2014-11-17 09:16:36 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.snoop_fanout::total 3174835 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 5050067000 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoopLayer0.occupancy 571290 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 1186578000 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 2990780492 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.respLayer2.occupancy 6370500 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.respLayer3.occupancy 13189500 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.trans_dist::ReadReq 216035 # Transaction distribution
system.iobus.trans_dist::ReadResp 216035 # Transaction distribution
2015-01-07 09:31:09 +01:00
system.iobus.trans_dist::WriteReq 57726 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteResp 57726 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.iobus.trans_dist::MessageReq 1654 # Transaction distribution
system.iobus.trans_dist::MessageResp 1654 # Transaction distribution
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 408166 # Packet count per connected master and slave (bytes)
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
2014-11-22 02:22:19 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
2015-01-07 09:31:09 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_count_system.bridge.master::total 452398 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95124 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_count::total 550830 # Packet count per connected master and slave (bytes)
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 204083 # Cumulative packet size per connected master and slave (bytes)
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
2014-11-22 02:22:19 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
2015-01-07 09:31:09 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_size_system.bridge.master::total 232479 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027280 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027280 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_size::total 3266375 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 4013816 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer3.occupancy 10045000 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.occupancy 1094500 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer5.occupancy 79000 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer6.occupancy 50500 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer7.occupancy 26000 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer8.occupancy 306124500 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer9.occupancy 1113000 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer10.occupancy 177500 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 24284500 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer18.occupancy 240815899 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer19.occupancy 1216500 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.respLayer0.occupancy 441392000 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.respLayer1.occupancy 50036000 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iocache.tags.replacements 47507 # number of replacements
system.iocache.tags.tagsinuse 0.108263 # Cycle average of tags in use
2014-11-17 09:16:36 +01:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.iocache.tags.sampled_refs 47523 # Sample count of references to valid blocks.
2014-11-17 09:16:36 +01:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2015-12-05 01:11:25 +01:00
system.iocache.tags.warmup_cycle 5048330960000 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108263 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006766 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.006766 # Average percentage of cache occupancy
2014-11-17 09:16:36 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2015-11-06 09:26:50 +01:00
system.iocache.tags.tag_accesses 428058 # Number of tag accesses
system.iocache.tags.data_accesses 428058 # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide 842 # number of ReadReq misses
system.iocache.ReadReq_misses::total 842 # number of ReadReq misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses
2015-11-06 09:26:50 +01:00
system.iocache.demand_misses::pc.south_bridge.ide 842 # number of demand (read+write) misses
system.iocache.demand_misses::total 842 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 842 # number of overall misses
system.iocache.overall_misses::total 842 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141163690 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 141163690 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6072614209 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 6072614209 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 141163690 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 141163690 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 141163690 # number of overall miss cycles
system.iocache.overall_miss_latency::total 141163690 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 842 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 842 # number of ReadReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses)
2015-11-06 09:26:50 +01:00
system.iocache.demand_accesses::pc.south_bridge.ide 842 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 842 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 842 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 842 # number of overall (read+write) accesses
2014-11-17 09:16:36 +01:00
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-11-17 09:16:36 +01:00
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167652.838480 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 167652.838480 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129978.900021 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 129978.900021 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167652.838480 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 167652.838480 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167652.838480 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 167652.838480 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 694 # number of cycles access was blocked
2014-11-17 09:16:36 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.iocache.blocked::no_mshrs 67 # number of cycles access was blocked
2014-11-17 09:16:36 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 10.358209 # average number of cycles each access was blocked
2014-11-17 09:16:36 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
2014-11-17 09:16:36 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
2014-12-23 15:31:20 +01:00
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
2015-11-06 09:26:50 +01:00
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 842 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 842 # number of ReadReq MSHR misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses
2015-11-06 09:26:50 +01:00
system.iocache.demand_mshr_misses::pc.south_bridge.ide 842 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 842 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 842 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 842 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99063690 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 99063690 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3736614209 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 3736614209 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 99063690 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 99063690 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 99063690 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 99063690 # number of overall MSHR miss cycles
2014-11-17 09:16:36 +01:00
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-11-17 09:16:36 +01:00
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117652.838480 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 117652.838480 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79978.900021 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79978.900021 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117652.838480 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 117652.838480 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117652.838480 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 117652.838480 # average overall mshr miss latency
2014-11-17 09:16:36 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::ReadReq 546346 # Transaction distribution
system.membus.trans_dist::ReadResp 588520 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::WriteReq 13920 # Transaction distribution
system.membus.trans_dist::WriteResp 13920 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::WritebackDirty 127367 # Transaction distribution
system.membus.trans_dist::CleanEvict 6933 # Transaction distribution
system.membus.trans_dist::UpgradeReq 2156 # Transaction distribution
system.membus.trans_dist::UpgradeResp 1652 # Transaction distribution
system.membus.trans_dist::ReadExReq 113266 # Transaction distribution
system.membus.trans_dist::ReadExResp 113266 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 42174 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::MessageReq 1654 # Transaction distribution
system.membus.trans_dist::MessageResp 1654 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 452398 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 668134 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 399599 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1520131 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141762 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 141762 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1665201 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 232479 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1336265 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15017472 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16586216 # Cumulative packet size per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_size::total 19607872 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 1571 # Total snoops (count)
system.membus.snoop_fanout::samples 901008 # Request fanout histogram
system.membus.snoop_fanout::mean 1.001836 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.042806 # Request fanout histogram
2014-11-17 09:16:36 +01:00
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::1 899354 99.82% 99.82% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.membus.snoop_fanout::2 1654 0.18% 100.00% # Request fanout histogram
2014-11-17 09:16:36 +01:00
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.membus.snoop_fanout::max_value 2 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::total 901008 # Request fanout histogram
system.membus.reqLayer0.occupancy 344294500 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.membus.reqLayer1.occupancy 503567500 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.membus.reqLayer2.occupancy 4013184 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.membus.reqLayer3.occupancy 852595593 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.membus.respLayer0.occupancy 2359184 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.membus.respLayer2.occupancy 1928199616 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.membus.respLayer4.occupancy 85638132 # Layer occupancy (ticks)
2014-11-17 09:16:36 +01:00
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
2011-02-07 10:23:16 +01:00
---------- End Simulation Statistics ----------
