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gem5/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt

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X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
---------- Begin Simulation Statistics ----------
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
sim_seconds 5.188454 # Number of seconds simulated
sim_ticks 5188454477000 # Number of ticks simulated
final_tick 5188454477000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
host_inst_rate 1005236 # Simulator instruction rate (inst/s)
host_op_rate 1937641 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 40503850527 # Simulator tick rate (ticks/s)
host_mem_usage 596712 # Number of bytes of host memory used
host_seconds 128.10 # Real time elapsed on the host
sim_insts 128768549 # Number of instructions simulated
sim_ops 248207575 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.bytes_read::cpu.inst 828736 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9035840 # Number of bytes read from this memory
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.bytes_read::total 9893312 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 828736 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 828736 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8124416 # Number of bytes written to this memory
system.physmem.bytes_written::total 8124416 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.num_reads::cpu.inst 12949 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 141185 # Number of read requests responded to by this memory
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.num_reads::total 154583 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 126944 # Number of write requests responded to by this memory
system.physmem.num_writes::total 126944 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.bw_read::cpu.inst 159727 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1741528 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide 5464 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1906794 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 159727 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 159727 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1565864 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1565864 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1565864 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.bw_total::cpu.inst 159727 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1741528 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 5464 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3472658 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 154583 # Number of read requests accepted
system.physmem.writeReqs 173664 # Number of write requests accepted
system.physmem.readBursts 154583 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 173664 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 9885440 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 7872 # Total number of bytes read from write queue
system.physmem.bytesWritten 10960768 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 9893312 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 11114496 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 123 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2370 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 1582 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 10392 # Per bank write bursts
system.physmem.perBankRdBursts::1 9723 # Per bank write bursts
system.physmem.perBankRdBursts::2 9455 # Per bank write bursts
system.physmem.perBankRdBursts::3 9480 # Per bank write bursts
system.physmem.perBankRdBursts::4 9901 # Per bank write bursts
system.physmem.perBankRdBursts::5 9535 # Per bank write bursts
system.physmem.perBankRdBursts::6 9436 # Per bank write bursts
system.physmem.perBankRdBursts::7 9264 # Per bank write bursts
system.physmem.perBankRdBursts::8 9069 # Per bank write bursts
system.physmem.perBankRdBursts::9 9032 # Per bank write bursts
system.physmem.perBankRdBursts::10 9333 # Per bank write bursts
system.physmem.perBankRdBursts::11 9426 # Per bank write bursts
system.physmem.perBankRdBursts::12 9943 # Per bank write bursts
system.physmem.perBankRdBursts::13 10317 # Per bank write bursts
system.physmem.perBankRdBursts::14 10185 # Per bank write bursts
system.physmem.perBankRdBursts::15 9969 # Per bank write bursts
system.physmem.perBankWrBursts::0 11290 # Per bank write bursts
system.physmem.perBankWrBursts::1 10662 # Per bank write bursts
system.physmem.perBankWrBursts::2 11268 # Per bank write bursts
system.physmem.perBankWrBursts::3 10649 # Per bank write bursts
system.physmem.perBankWrBursts::4 10537 # Per bank write bursts
system.physmem.perBankWrBursts::5 10374 # Per bank write bursts
system.physmem.perBankWrBursts::6 10316 # Per bank write bursts
system.physmem.perBankWrBursts::7 10238 # Per bank write bursts
system.physmem.perBankWrBursts::8 10391 # Per bank write bursts
system.physmem.perBankWrBursts::9 10158 # Per bank write bursts
system.physmem.perBankWrBursts::10 10967 # Per bank write bursts
system.physmem.perBankWrBursts::11 11299 # Per bank write bursts
system.physmem.perBankWrBursts::12 11272 # Per bank write bursts
system.physmem.perBankWrBursts::13 11296 # Per bank write bursts
system.physmem.perBankWrBursts::14 10371 # Per bank write bursts
system.physmem.perBankWrBursts::15 10174 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.totGap 5188454413500 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.readPktSize::6 154583 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.writePktSize::6 173664 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 151266 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 2754 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 66 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 58 # What read queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.wrQLenPdf::15 2704 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 5147 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 8659 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 9857 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 10197 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 11221 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 11668 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 12698 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 12293 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 12864 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 11643 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 11117 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 9667 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 8924 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7393 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7022 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6948 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 6786 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 379 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 345 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 332 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 309 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 291 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 268 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 252 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 255 # What write queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.wrQLenPdf::41 243 # What write queue length does an incoming req see
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.wrQLenPdf::42 221 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 201 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 184 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 172 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 141 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 126 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 131 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 126 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 105 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 73 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 15 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 58761 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 354.761560 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 206.245927 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 358.668619 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 19719 33.56% 33.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 13641 23.21% 56.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5790 9.85% 66.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3461 5.89% 72.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2363 4.02% 76.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1647 2.80% 79.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1118 1.90% 81.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1023 1.74% 82.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 9999 17.02% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 58761 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6350 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 24.321575 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 600.921026 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 6349 99.98% 99.98% # Reads before turning the bus around for writes
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.rdPerTurnAround::total 6350 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6350 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 26.970394 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 21.564885 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 26.510023 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 4926 77.57% 77.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 38 0.60% 78.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 20 0.31% 78.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 294 4.63% 83.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 158 2.49% 85.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 56 0.88% 86.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 42 0.66% 87.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 42 0.66% 87.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 172 2.71% 90.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 12 0.19% 90.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 18 0.28% 90.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 13 0.20% 91.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 29 0.46% 91.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 15 0.24% 91.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 10 0.16% 92.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 51 0.80% 92.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 104 1.64% 94.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 11 0.17% 94.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 7 0.11% 94.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 15 0.24% 95.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 146 2.30% 97.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 5 0.08% 97.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 14 0.22% 97.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 3 0.05% 97.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 26 0.41% 98.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 2 0.03% 98.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 6 0.09% 98.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.02% 98.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 29 0.46% 98.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 4 0.06% 98.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 1 0.02% 98.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 9 0.14% 98.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 18 0.28% 99.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 10 0.16% 99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 2 0.03% 99.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.02% 99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 5 0.08% 99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 5 0.08% 99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171 2 0.03% 99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175 2 0.03% 99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 6 0.09% 99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187 1 0.02% 99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191 3 0.05% 99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195 1 0.02% 99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203 7 0.11% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::204-207 2 0.03% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-219 1 0.02% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::220-223 2 0.03% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-227 1 0.02% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::228-231 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::248-251 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6350 # Writes before turning the bus around for reads
system.physmem.totQLat 1440123750 # Total ticks spent queuing
system.physmem.totMemAccLat 4336248750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 772300000 # Total ticks spent in databus transfers
system.physmem.avgQLat 9323.60 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.avgMemAccLat 28073.60 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.avgWrBW 2.11 # Average achieved write bandwidth in MiByte/s
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.avgWrBWSys 2.14 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.busUtil 0.03 # Data bus utilization in percentage
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.avgWrQLen 22.93 # Average write queue length when enqueuing
system.physmem.readRowHits 126965 # Number of row buffer hits during reads
system.physmem.writeRowHits 139995 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.20 # Row buffer hit rate for reads
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.writeRowHitRate 81.73 # Row buffer hit rate for writes
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.avgGap 15806555.47 # Average gap between requests
system.physmem.pageHitRate 81.95 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 220290840 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 120198375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 602050800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 552964320 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 338884550160 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 134005273470 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 2995523664000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 3469908991965 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.775183 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 4983224613500 # Time in different power states
system.physmem_0.memoryStateTime::REF 173253860000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem_0.memoryStateTime::ACT 31975122750 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem_1.actEnergy 223942320 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 122190750 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 602729400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 556813440 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 338884550160 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 134550538605 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 2995045361250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 3469986125925 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.790049 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 4982425910500 # Time in different power states
system.physmem_1.memoryStateTime::REF 173253860000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem_1.memoryStateTime::ACT 32774591500 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.numCycles 10376908954 # number of cpu cycles simulated
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.committedInsts 128768549 # Number of instructions committed
system.cpu.committedOps 248207575 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 232776792 # Number of integer alu accesses
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.num_func_calls 2318393 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 23210237 # number of instructions that are conditional controls
system.cpu.num_int_insts 232776792 # number of integer instructions
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.num_fp_insts 0 # number of float instructions
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.num_int_register_reads 436093789 # number of times the integer registers were read
system.cpu.num_int_register_writes 198513181 # number of times the integer registers were written
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.num_cc_register_reads 133234655 # number of times the CC registers were read
system.cpu.num_cc_register_writes 95751573 # number of times the CC registers were written
system.cpu.num_mem_refs 22383387 # number of memory refs
system.cpu.num_load_insts 13964107 # Number of load instructions
system.cpu.num_store_insts 8419280 # Number of store instructions
system.cpu.num_idle_cycles 9778785583.998116 # Number of idle cycles
system.cpu.num_busy_cycles 598123370.001885 # Number of busy cycles
system.cpu.not_idle_fraction 0.057640 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.942360 # Percentage of idle cycles
system.cpu.Branches 26388104 # Number of branches fetched
system.cpu.op_class::No_OpClass 172612 0.07% 0.07% # Class of executed instruction
system.cpu.op_class::IntAlu 225394100 90.81% 90.88% # Class of executed instruction
system.cpu.op_class::IntMult 140617 0.06% 90.93% # Class of executed instruction
system.cpu.op_class::IntDiv 123416 0.05% 90.98% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.98% # Class of executed instruction
system.cpu.op_class::MemRead 13959118 5.62% 96.61% # Class of executed instruction
system.cpu.op_class::MemWrite 8419280 3.39% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.op_class::total 248209143 # Class of executed instruction
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.dcache.tags.replacements 1623444 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 20166944 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1623956 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 12.418405 # Average number of references to valid blocks.
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit.
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 87 # Occupied blocks per task id
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.dcache.tags.tag_accesses 88826058 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 88826058 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 12020150 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 12020150 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8085355 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8085355 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 59272 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 59272 # number of SoftPFReq hits
system.cpu.dcache.demand_hits::cpu.data 20105505 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 20105505 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 20164777 # number of overall hits
system.cpu.dcache.overall_hits::total 20164777 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 907010 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 907010 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 325954 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 325954 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 402776 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 402776 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 1232964 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1232964 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1635740 # number of overall misses
system.cpu.dcache.overall_misses::total 1635740 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12729308500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 12729308500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 11333106054 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 11333106054 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 24062414554 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 24062414554 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 24062414554 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 24062414554 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 12927160 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 12927160 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8411309 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8411309 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 462048 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 462048 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21338469 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21338469 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 21800517 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21800517 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070163 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.070163 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038752 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.038752 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871719 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.871719 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.057781 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.057781 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.075032 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.075032 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14034.364009 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14034.364009 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34769.035060 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 34769.035060 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19515.910078 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19515.910078 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14710.415197 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14710.415197 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 9503 # number of cycles access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.dcache.blocked::no_mshrs 92 # number of cycles access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 103.293478 # average number of cycles each access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.dcache.writebacks::writebacks 1539984 # number of writebacks
system.cpu.dcache.writebacks::total 1539984 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 290 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 290 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9259 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 9259 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 9549 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 9549 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 9549 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 9549 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906720 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 906720 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316695 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 316695 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402742 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 402742 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1223415 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1223415 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1626157 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1626157 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10908565500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10908565500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10195656140 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10195656140 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5345944000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5345944000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21104221640 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 21104221640 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26450165640 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 26450165640 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94247525000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94247525000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2568414500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2568414500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96815939500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 96815939500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070141 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070141 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037651 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037651 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871645 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871645 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057334 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.057334 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074593 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.074593 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12030.798372 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12030.798372 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32193.928354 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32193.928354 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13273.867637 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13273.867637 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17250.255751 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17250.255751 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16265.444013 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16265.444013 # average overall mshr miss latency
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.dtb_walker_cache.tags.replacements 8115 # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse 5.053285 # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs 13021 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs 8129 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs 1.601796 # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 5157393413000 # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.053285 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315830 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315830 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
system.cpu.dtb_walker_cache.tags.tag_accesses 54039 # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses 54039 # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13023 # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 13023 # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13023 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 13023 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13023 # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 13023 # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9331 # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 9331 # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9331 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 9331 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9331 # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 9331 # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 97236000 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 97236000 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 97236000 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total 97236000 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 97236000 # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total 97236000 # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22354 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total 22354 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22354 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total 22354 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22354 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 22354 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.417420 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.417420 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.417420 # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.417420 # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.417420 # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.417420 # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10420.748044 # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10420.748044 # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10420.748044 # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10420.748044 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10420.748044 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10420.748044 # average overall miss latency
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.dtb_walker_cache.writebacks::writebacks 3011 # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total 3011 # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9331 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9331 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9331 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total 9331 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9331 # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total 9331 # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 78573500 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 78573500 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 78573500 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 78573500 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 78573500 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 78573500 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.417420 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.417420 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.417420 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.417420 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.417420 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.417420 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8420.694459 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8420.694459 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8420.694459 # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8420.694459 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8420.694459 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8420.694459 # average overall mshr miss latency
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.icache.tags.replacements 793710 # number of replacements
system.cpu.icache.tags.tagsinuse 510.347195 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 145088955 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 794222 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 182.680604 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 161164789250 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 510.347195 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.996772 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.996772 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.icache.tags.tag_accesses 146677413 # Number of tag accesses
system.cpu.icache.tags.data_accesses 146677413 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 145088955 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 145088955 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 145088955 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 145088955 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 145088955 # number of overall hits
system.cpu.icache.overall_hits::total 145088955 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 794229 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 794229 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 794229 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 794229 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 794229 # number of overall misses
system.cpu.icache.overall_misses::total 794229 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11146745615 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 11146745615 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 11146745615 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 11146745615 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 11146745615 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 11146745615 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 145883184 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 145883184 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 145883184 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 145883184 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 145883184 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 145883184 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005444 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.005444 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.005444 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.005444 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.005444 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.005444 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14034.674653 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14034.674653 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14034.674653 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14034.674653 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14034.674653 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14034.674653 # average overall miss latency
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 794229 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 794229 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 794229 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 794229 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 794229 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 794229 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9553400385 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 9553400385 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9553400385 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 9553400385 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9553400385 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 9553400385 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005444 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.005444 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.005444 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12028.521226 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12028.521226 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12028.521226 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12028.521226 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12028.521226 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12028.521226 # average overall mshr miss latency
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.itb_walker_cache.tags.replacements 4028 # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse 3.070596 # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs 7432 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs 4039 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs 1.840059 # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5161717779000 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.070596 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191912 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total 0.191912 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id
system.cpu.itb_walker_cache.tags.tag_accesses 29565 # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses 29565 # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7435 # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total 7435 # number of ReadReq hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7437 # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total 7437 # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7437 # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total 7437 # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4897 # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total 4897 # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4897 # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total 4897 # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4897 # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total 4897 # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 48969750 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total 48969750 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 48969750 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total 48969750 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 48969750 # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total 48969750 # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12332 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total 12332 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12334 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total 12334 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12334 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total 12334 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.397097 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.397097 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.397033 # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total 0.397033 # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.397033 # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total 0.397033 # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9999.948948 # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9999.948948 # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9999.948948 # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9999.948948 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9999.948948 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9999.948948 # average overall miss latency
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.itb_walker_cache.writebacks::writebacks 802 # number of writebacks
system.cpu.itb_walker_cache.writebacks::total 802 # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4897 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4897 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4897 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total 4897 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4897 # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total 4897 # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 39174250 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 39174250 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 39174250 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 39174250 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 39174250 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 39174250 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.397097 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.397097 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.397033 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.397033 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.397033 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.397033 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7999.642638 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7999.642638 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7999.642638 # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7999.642638 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7999.642638 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7999.642638 # average overall mshr miss latency
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.l2cache.tags.replacements 87241 # number of replacements
system.cpu.l2cache.tags.tagsinuse 64748.665455 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3494859 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 151936 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 23.002179 # Average number of references to valid blocks.
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 50323.834449 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006391 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141287 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3224.989333 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 11199.693995 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.767881 # Average percentage of cache occupancy
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049209 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.170894 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.987986 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 64695 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3016 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5015 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56538 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987167 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 32251607 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 32251607 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6647 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3226 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 781266 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1280034 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2071173 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1543797 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1543797 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 314 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 314 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 201020 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 201020 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6647 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 3226 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 781266 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1481054 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2272193 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6647 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 3226 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 781266 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1481054 # number of overall hits
system.cpu.l2cache.overall_hits::total 2272193 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 12950 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 28613 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 41569 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1320 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 1320 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 113503 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 113503 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.l2cache.demand_misses::cpu.inst 12950 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 142116 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 155072 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.l2cache.overall_misses::cpu.inst 12950 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 142116 # number of overall misses
system.cpu.l2cache.overall_misses::total 155072 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 89250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 350750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 946380250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2143813000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 3090633250 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15722387 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 15722387 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7833269720 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 7833269720 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 89250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 350750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 946380250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 9977082720 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 10923902970 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 89250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 350750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 946380250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 9977082720 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 10923902970 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6648 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3231 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 794216 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1308647 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2112742 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1543797 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1543797 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1634 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 1634 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314523 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 314523 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6648 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3231 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 794216 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1623170 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2427265 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6648 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3231 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 794216 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1623170 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2427265 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000150 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001548 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016305 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021865 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.019675 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.807834 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.807834 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.360873 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.360873 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000150 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001548 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016305 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.087555 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.063888 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000150 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001548 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016305 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.087555 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.063888 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89250 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 70150 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73079.555985 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74924.439940 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74349.473165 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11910.899242 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11910.899242 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69013.768094 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69013.768094 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 70150 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73079.555985 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70203.796335 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 70444.070948 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 70150 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73079.555985 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70203.796335 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 70444.070948 # average overall miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.l2cache.writebacks::writebacks 80277 # number of writebacks
system.cpu.l2cache.writebacks::total 80277 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12950 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28613 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 41569 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1320 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1320 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113503 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 113503 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 12950 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 142116 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 155072 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 12950 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 142116 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 155072 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 287750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 784145750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1785561500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2570071250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14126802 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14126802 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6414530780 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6414530780 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 287750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 784145750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8200092280 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 8984602030 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 76250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 287750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 784145750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8200092280 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 8984602030 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86686810500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86686810500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2401284000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2401284000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89088094500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89088094500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000150 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001548 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016305 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021865 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019675 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.807834 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.807834 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.360873 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.360873 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000150 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001548 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016305 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087555 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.063888 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000150 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001548 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016305 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087555 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063888 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 57550 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60551.795367 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62403.854891 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61826.631625 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10702.122727 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10702.122727 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56514.195924 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56514.195924 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60551.795367 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57699.993526 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57938.261130 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60551.795367 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57699.993526 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57938.261130 # average overall mshr miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.toL2Bus.trans_dist::ReadReq 2700360 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2699834 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 13918 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 13918 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 1543797 # Transaction distribution
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.toL2Bus.trans_dist::UpgradeReq 2180 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2180 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 314528 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 314528 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1588445 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5982302 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8930 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18990 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7598667 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50829824 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204129411 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 258112 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 618176 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 255835523 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 53618 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 4025992 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 3.011815 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.108054 # Request fanout histogram
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.toL2Bus.snoop_fanout::3 3978424 98.82% 98.82% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 47568 1.18% 100.00% # Request fanout histogram
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.toL2Bus.snoop_fanout::total 4025992 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 3837723500 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.toL2Bus.snoopLayer0.occupancy 483000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 1193787115 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 3055897582 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.toL2Bus.respLayer2.occupancy 7346250 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu.toL2Bus.respLayer3.occupancy 13996750 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.trans_dist::ReadReq 230300 # Transaction distribution
system.iobus.trans_dist::ReadResp 230300 # Transaction distribution
system.iobus.trans_dist::WriteReq 57726 # Transaction distribution
system.iobus.trans_dist::WriteResp 11006 # Transaction distribution
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.trans_dist::MessageReq 1653 # Transaction distribution
system.iobus.trans_dist::MessageResp 1653 # Transaction distribution
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.pkt_count_system.bridge.master::total 480916 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95136 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95136 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3306 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3306 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 579358 # Packet count per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.pkt_size_system.bridge.master::total 246738 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027328 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027328 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6612 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6612 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 3280678 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 3941856 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.reqLayer19.occupancy 448381627 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.respLayer0.occupancy 469910000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.respLayer1.occupancy 52236750 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.respLayer2.occupancy 1653000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iocache.tags.replacements 47513 # number of replacements
system.iocache.tags.tagsinuse 0.108235 # Cycle average of tags in use
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iocache.tags.sampled_refs 47529 # Sample count of references to valid blocks.
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iocache.tags.warmup_cycle 5045848693000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108235 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006765 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.006765 # Average percentage of cache occupancy
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iocache.tags.tag_accesses 428112 # Number of tag accesses
system.iocache.tags.data_accesses 428112 # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide 848 # number of ReadReq misses
system.iocache.ReadReq_misses::total 848 # number of ReadReq misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iocache.demand_misses::pc.south_bridge.ide 848 # number of demand (read+write) misses
system.iocache.demand_misses::total 848 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 848 # number of overall misses
system.iocache.overall_misses::total 848 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144284936 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 144284936 # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12370106941 # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total 12370106941 # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 144284936 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 144284936 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 144284936 # number of overall miss cycles
system.iocache.overall_miss_latency::total 144284936 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 848 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 848 # number of ReadReq accesses(hits+misses)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iocache.demand_accesses::pc.south_bridge.ide 848 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 848 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 848 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 848 # number of overall (read+write) accesses
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170147.330189 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 170147.330189 # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264771.124593 # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 264771.124593 # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170147.330189 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 170147.330189 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170147.330189 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 170147.330189 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 70958 # number of cycles access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iocache.blocked::no_mshrs 9208 # number of cycles access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 7.706125 # average number of cycles each access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 848 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 848 # number of ReadReq MSHR misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iocache.demand_mshr_misses::pc.south_bridge.ide 848 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 848 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 848 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 848 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100162436 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 100162436 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9940666941 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9940666941 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100162436 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 100162436 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100162436 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 100162436 # number of overall MSHR miss cycles
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 118116.080189 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 118116.080189 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212771.124593 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212771.124593 # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 118116.080189 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 118116.080189 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 118116.080189 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 118116.080189 # average overall mshr miss latency
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.membus.trans_dist::ReadReq 624010 # Transaction distribution
system.membus.trans_dist::ReadResp 624010 # Transaction distribution
system.membus.trans_dist::WriteReq 13918 # Transaction distribution
system.membus.trans_dist::WriteResp 13918 # Transaction distribution
system.membus.trans_dist::Writeback 126944 # Transaction distribution
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.membus.trans_dist::UpgradeReq 2146 # Transaction distribution
system.membus.trans_dist::UpgradeResp 1600 # Transaction distribution
system.membus.trans_dist::ReadExReq 113223 # Transaction distribution
system.membus.trans_dist::ReadExResp 113223 # Transaction distribution
system.membus.trans_dist::MessageReq 1653 # Transaction distribution
system.membus.trans_dist::MessageResp 1653 # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3306 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 3306 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480916 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710106 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392937 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1583959 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141398 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 141398 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1728663 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6612 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total 6612 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246738 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420209 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15002688 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16669635 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.membus.pkt_size::total 22681367 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 1621 # Total snoops (count)
system.membus.snoop_fanout::samples 331450 # Request fanout histogram
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.membus.snoop_fanout::1 331450 100.00% 100.00% # Request fanout histogram
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.membus.snoop_fanout::total 331450 # Request fanout histogram
system.membus.reqLayer0.occupancy 257308500 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.membus.reqLayer1.occupancy 358085000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.membus.reqLayer2.occupancy 3306000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.membus.reqLayer3.occupancy 1729709500 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.membus.respLayer0.occupancy 1653000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.membus.respLayer2.occupancy 2618865668 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.membus.respLayer4.occupancy 54365250 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
---------- End Simulation Statistics ----------
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