2008-10-21 01:00:07 +02:00
---------- Begin Simulation Statistics ----------
2016-12-05 22:48:34 +01:00
sim_seconds 1.865010 # Number of seconds simulated
sim_ticks 1865009748000 # Number of ticks simulated
final_tick 1865009748000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2008-10-21 01:00:07 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-12-05 22:48:34 +01:00
host_inst_rate 235871 # Simulator instruction rate (inst/s)
host_op_rate 235870 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 8303287371 # Simulator tick rate (ticks/s)
host_mem_usage 337912 # Number of bytes of host memory used
host_seconds 224.61 # Real time elapsed on the host
sim_insts 52979108 # Number of instructions simulated
sim_ops 52979108 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-12-05 22:48:34 +01:00
system.physmem.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 962240 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24880192 # Number of bytes read from this memory
2014-09-03 13:42:59 +02:00
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
2016-12-05 22:48:34 +01:00
system.physmem.bytes_read::total 25843392 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 962240 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 962240 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7516224 # Number of bytes written to this memory
system.physmem.bytes_written::total 7516224 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 15035 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 388753 # Number of read requests responded to by this memory
2014-09-03 13:42:59 +02:00
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
2016-12-05 22:48:34 +01:00
system.physmem.num_reads::total 403803 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 117441 # Number of write requests responded to by this memory
system.physmem.num_writes::total 117441 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 515944 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 13340516 # Total read bandwidth from this memory (bytes/s)
2016-10-14 00:21:40 +02:00
system.physmem.bw_read::tsunami.ide 515 # Total read bandwidth from this memory (bytes/s)
2016-12-05 22:48:34 +01:00
system.physmem.bw_read::total 13856974 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 515944 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 515944 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4030126 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4030126 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4030126 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 515944 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 13340516 # Total bandwidth to/from this memory (bytes/s)
2016-10-14 00:21:40 +02:00
system.physmem.bw_total::tsunami.ide 515 # Total bandwidth to/from this memory (bytes/s)
2016-12-05 22:48:34 +01:00
system.physmem.bw_total::total 17887100 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 403803 # Number of read requests accepted
system.physmem.writeReqs 117441 # Number of write requests accepted
system.physmem.readBursts 403803 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 117441 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 25835712 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue
system.physmem.bytesWritten 7515136 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 25843392 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7516224 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue
2015-07-03 16:15:03 +02:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-12-05 22:48:34 +01:00
system.physmem.perBankRdBursts::0 25444 # Per bank write bursts
system.physmem.perBankRdBursts::1 25611 # Per bank write bursts
system.physmem.perBankRdBursts::2 25628 # Per bank write bursts
system.physmem.perBankRdBursts::3 25719 # Per bank write bursts
system.physmem.perBankRdBursts::4 25100 # Per bank write bursts
system.physmem.perBankRdBursts::5 25088 # Per bank write bursts
system.physmem.perBankRdBursts::6 24758 # Per bank write bursts
system.physmem.perBankRdBursts::7 24649 # Per bank write bursts
system.physmem.perBankRdBursts::8 24903 # Per bank write bursts
system.physmem.perBankRdBursts::9 25188 # Per bank write bursts
system.physmem.perBankRdBursts::10 25284 # Per bank write bursts
system.physmem.perBankRdBursts::11 25005 # Per bank write bursts
system.physmem.perBankRdBursts::12 24375 # Per bank write bursts
system.physmem.perBankRdBursts::13 25430 # Per bank write bursts
system.physmem.perBankRdBursts::14 25804 # Per bank write bursts
system.physmem.perBankRdBursts::15 25697 # Per bank write bursts
system.physmem.perBankWrBursts::0 7804 # Per bank write bursts
system.physmem.perBankWrBursts::1 7583 # Per bank write bursts
system.physmem.perBankWrBursts::2 7900 # Per bank write bursts
system.physmem.perBankWrBursts::3 7698 # Per bank write bursts
system.physmem.perBankWrBursts::4 7224 # Per bank write bursts
system.physmem.perBankWrBursts::5 7092 # Per bank write bursts
system.physmem.perBankWrBursts::6 6759 # Per bank write bursts
system.physmem.perBankWrBursts::7 6515 # Per bank write bursts
system.physmem.perBankWrBursts::8 7053 # Per bank write bursts
system.physmem.perBankWrBursts::9 6824 # Per bank write bursts
system.physmem.perBankWrBursts::10 7197 # Per bank write bursts
system.physmem.perBankWrBursts::11 7005 # Per bank write bursts
system.physmem.perBankWrBursts::12 6955 # Per bank write bursts
system.physmem.perBankWrBursts::13 7882 # Per bank write bursts
system.physmem.perBankWrBursts::14 8018 # Per bank write bursts
2016-10-14 00:21:40 +02:00
system.physmem.perBankWrBursts::15 7915 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2016-12-05 22:48:34 +01:00
system.physmem.numWrRetry 65 # Number of times write queue was full causing retry
system.physmem.totGap 1865004470500 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-12-05 22:48:34 +01:00
system.physmem.readPktSize::6 403803 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2016-12-05 22:48:34 +01:00
system.physmem.writePktSize::6 117441 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 314056 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 36501 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 28766 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 24237 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 106 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see
2015-03-02 11:04:20 +01:00
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
2014-09-03 13:42:59 +02:00
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
2013-11-01 16:56:34 +01:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2016-12-05 22:48:34 +01:00
system.physmem.wrQLenPdf::15 1442 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2555 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 3197 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4247 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5578 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6335 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 7132 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 8220 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 6784 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 7296 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7880 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 7649 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 6878 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 6959 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 6763 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7138 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6050 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 6195 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 763 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 457 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 336 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 326 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 298 # What write queue length does an incoming req see
2016-10-14 00:21:40 +02:00
system.physmem.wrQLenPdf::38 301 # What write queue length does an incoming req see
2016-12-05 22:48:34 +01:00
system.physmem.wrQLenPdf::39 245 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 233 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 257 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 275 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 379 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 349 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 350 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 345 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 347 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 294 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 315 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 278 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 235 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 212 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 315 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 191 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 373 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 288 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 189 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 129 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 159 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 61362 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 543.503536 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 333.365701 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 417.323842 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 13476 21.96% 21.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 10707 17.45% 39.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 4479 7.30% 46.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2678 4.36% 51.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2195 3.58% 54.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1843 3.00% 57.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1874 3.05% 60.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1552 2.53% 63.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 22558 36.76% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 61362 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5160 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 78.231977 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 2938.731055 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191 5157 99.94% 99.94% # Reads before turning the bus around for writes
2016-04-09 18:13:40 +02:00
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
2016-12-05 22:48:34 +01:00
system.physmem.rdPerTurnAround::total 5160 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5160 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 22.756589 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.921420 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 24.589297 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23 4641 89.94% 89.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31 34 0.66% 90.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39 173 3.35% 93.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47 9 0.17% 94.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55 2 0.04% 94.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63 16 0.31% 94.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71 8 0.16% 94.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79 3 0.06% 94.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87 29 0.56% 95.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95 4 0.08% 95.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103 150 2.91% 98.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111 19 0.37% 98.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119 6 0.12% 98.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127 5 0.10% 98.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135 7 0.14% 98.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143 2 0.04% 98.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151 1 0.02% 99.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167 3 0.06% 99.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175 7 0.14% 99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183 5 0.10% 99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191 10 0.19% 99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199 13 0.25% 99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207 1 0.02% 99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-223 4 0.08% 99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231 4 0.08% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263 3 0.06% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5160 # Writes before turning the bus around for reads
system.physmem.totQLat 7817102750 # Total ticks spent queuing
system.physmem.totMemAccLat 15386159000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2018415000 # Total ticks spent in databus transfers
system.physmem.avgQLat 19364.46 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-12-05 22:48:34 +01:00
system.physmem.avgMemAccLat 38114.46 # Average memory access latency per DRAM burst
2016-10-14 00:21:40 +02:00
system.physmem.avgRdBW 13.85 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 4.03 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 13.86 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 4.03 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-03-02 11:04:20 +01:00
system.physmem.busUtil 0.14 # Data bus utilization in percentage
2014-09-03 13:42:59 +02:00
system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
2015-07-03 16:15:03 +02:00
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
2016-12-05 22:48:34 +01:00
system.physmem.avgRdQLen 1.99 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.83 # Average write queue length when enqueuing
system.physmem.readRowHits 364427 # Number of row buffer hits during reads
system.physmem.writeRowHits 95317 # Number of row buffer hits during writes
system.physmem.readRowHitRate 90.28 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 81.16 # Row buffer hit rate for writes
system.physmem.avgGap 3577987.41 # Average gap between requests
system.physmem.pageHitRate 88.22 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 216106380 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 114863265 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1442258580 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 305761500 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3620229600.000001 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 4158564390 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 232346880 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 8004158310 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 4220231520 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 438996708360 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 461312299845 # Total energy per rank (pJ)
system.physmem_0.averagePower 247.351146 # Core power per rank (mW)
system.physmem_0.totalIdleTime 1855244620250 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 361602000 # Time in different power states
system.physmem_0.memoryStateTime::REF 1537874000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 1826739481250 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 10990187750 # Time in different power states
system.physmem_0.memoryStateTime::ACT 7827619250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 17552983750 # Time in different power states
system.physmem_1.actEnergy 222025440 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 118005525 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1440038040 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 307191780 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3620229600.000001 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 4104344850 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 228211680 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 8096599200 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 4247999520 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 438951182175 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 461336536560 # Total energy per rank (pJ)
system.physmem_1.averagePower 247.364142 # Core power per rank (mW)
system.physmem_1.totalIdleTime 1855407985250 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 350582750 # Time in different power states
system.physmem_1.memoryStateTime::REF 1537736000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 1826594899250 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 11062498750 # Time in different power states
system.physmem_1.memoryStateTime::ACT 7708202750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 17755828500 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 19556212 # Number of BP lookups
system.cpu.branchPred.condPredicted 16618547 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 593854 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 12802975 # Number of BTB lookups
system.cpu.branchPred.BTBHits 5420040 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-12-05 22:48:34 +01:00
system.cpu.branchPred.BTBHitPct 42.334223 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1126473 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 42524 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 6261380 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 563797 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 5697583 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 265016 # Number of mispredicted indirect branches.
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2009-04-09 07:21:30 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
2011-07-10 19:56:09 +02:00
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
2016-12-05 22:48:34 +01:00
system.cpu.dtb.read_hits 11131129 # DTB read hits
system.cpu.dtb.read_misses 49734 # DTB read misses
system.cpu.dtb.read_acv 613 # DTB read access violations
system.cpu.dtb.read_accesses 995788 # DTB read accesses
system.cpu.dtb.write_hits 6783534 # DTB write hits
system.cpu.dtb.write_misses 12230 # DTB write misses
system.cpu.dtb.write_acv 435 # DTB write access violations
system.cpu.dtb.write_accesses 345368 # DTB write accesses
system.cpu.dtb.data_hits 17914663 # DTB hits
system.cpu.dtb.data_misses 61964 # DTB misses
system.cpu.dtb.data_acv 1048 # DTB access violations
system.cpu.dtb.data_accesses 1341156 # DTB accesses
system.cpu.itb.fetch_hits 1815343 # ITB hits
system.cpu.itb.fetch_misses 10369 # ITB misses
system.cpu.itb.fetch_acv 759 # ITB acv
system.cpu.itb.fetch_accesses 1825712 # ITB accesses
2011-07-10 19:56:09 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
2016-08-12 15:12:59 +02:00
system.cpu.numPwrStateTransitions 12878 # Number of power state transitions
system.cpu.pwrStateClkGateDist::samples 6439 # Distribution of time spent in the clock gated state
2016-12-05 22:48:34 +01:00
system.cpu.pwrStateClkGateDist::mean 279575452.943004 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::stdev 438968142.754116 # Distribution of time spent in the clock gated state
2016-08-12 15:12:59 +02:00
system.cpu.pwrStateClkGateDist::1000-5e+10 6439 100.00% 100.00% # Distribution of time spent in the clock gated state
2016-12-05 22:48:34 +01:00
system.cpu.pwrStateClkGateDist::min_value 71000 # Distribution of time spent in the clock gated state
2016-06-06 18:16:44 +02:00
system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state
2016-08-12 15:12:59 +02:00
system.cpu.pwrStateClkGateDist::total 6439 # Distribution of time spent in the clock gated state
2016-12-05 22:48:34 +01:00
system.cpu.pwrStateResidencyTicks::ON 64823406500 # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::CLK_GATED 1800186341500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 129653253 # number of cpu cycles simulated
2011-07-10 19:56:09 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-12-05 22:48:34 +01:00
system.cpu.fetch.icacheStallCycles 30226306 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 85761758 # Number of instructions fetch has processed
system.cpu.fetch.Branches 19556212 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 7110310 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 91828962 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1682802 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 214 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 31116 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 206972 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 428466 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 497 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 9929941 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 408418 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 123563934 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.694068 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.023639 # Number of instructions fetched each cycle (Total)
2009-07-07 00:49:48 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-12-05 22:48:34 +01:00
system.cpu.fetch.rateDist::0 107716203 87.17% 87.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1033964 0.84% 88.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 2108086 1.71% 89.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 968916 0.78% 90.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 2910075 2.36% 92.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 665807 0.54% 93.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 808204 0.65% 94.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1035117 0.84% 94.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 6317562 5.11% 100.00% # Number of instructions fetched each cycle (Total)
2009-07-07 00:49:48 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2016-12-05 22:48:34 +01:00
system.cpu.fetch.rateDist::total 123563934 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.150835 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.661470 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 24256271 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 86199481 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 10262767 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 2038754 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 806660 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 739137 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 35567 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 74091152 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 113387 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 806660 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 25262123 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 56608165 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 20046193 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 11227977 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 9612814 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 71075345 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 200089 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 2115758 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 264182 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 5312560 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 47887128 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 85631010 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 85450068 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 168489 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 38179018 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 9708102 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1730208 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 277739 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 13892500 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 11673351 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 7232744 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1724750 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1099672 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 62753291 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2208700 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 60568136 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 94532 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 11982878 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 5316307 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1547451 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 123563934 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.490176 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.236204 # Number of insts issued each cycle
2011-07-10 19:56:09 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-12-05 22:48:34 +01:00
system.cpu.iq.issued_per_cycle::0 99014105 80.13% 80.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 10422330 8.43% 88.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 4419921 3.58% 92.14% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 3179961 2.57% 94.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 3252538 2.63% 97.35% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 1603803 1.30% 98.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1099991 0.89% 99.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 433312 0.35% 99.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 137973 0.11% 100.00% # Number of insts issued each cycle
2011-07-10 19:56:09 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2016-12-05 22:48:34 +01:00
system.cpu.iq.issued_per_cycle::total 123563934 # Number of insts issued each cycle
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-12-05 22:48:34 +01:00
system.cpu.iq.fu_full::IntAlu 206621 16.55% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMisc 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.55% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 610635 48.92% 65.47% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 372589 29.85% 95.32% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemRead 31948 2.56% 97.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemWrite 26502 2.12% 100.00% # attempts to use FU when none available
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2016-12-05 22:48:34 +01:00
system.cpu.iq.FU_type_0::No_OpClass 7279 0.01% 0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 40937281 67.59% 67.60% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 62136 0.10% 67.70% # Type of FU issued
2016-04-09 18:13:40 +02:00
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.70% # Type of FU issued
2016-12-05 22:48:34 +01:00
system.cpu.iq.FU_type_0::FloatAdd 38562 0.06% 67.77% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.77% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.77% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.77% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.77% # Type of FU issued
2016-04-09 18:13:40 +02:00
system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 67.77% # Type of FU issued
2016-10-19 12:20:04 +02:00
system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.77% # Type of FU issued
2016-04-09 18:13:40 +02:00
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.77% # Type of FU issued
2016-12-05 22:48:34 +01:00
system.cpu.iq.FU_type_0::MemRead 11522525 19.02% 86.80% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 6750152 11.14% 97.94% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemRead 156092 0.26% 98.20% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemWrite 141347 0.23% 98.43% # Type of FU issued
2016-10-14 00:21:40 +02:00
system.cpu.iq.FU_type_0::IprAccess 949126 1.57% 100.00% # Type of FU issued
2011-07-10 19:56:09 +02:00
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-12-05 22:48:34 +01:00
system.cpu.iq.FU_type_0::total 60568136 # Type of FU issued
system.cpu.iq.rate 0.467155 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1248295 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.020610 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 245303428 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 76606948 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 58345447 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 739604 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 359470 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 336798 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 61411065 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 398087 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 692317 # Number of loads that had data forwarded from stores
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-12-05 22:48:34 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 2580830 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 3930 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 22198 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 854795 # Number of stores squashed
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-12-05 22:48:34 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 17998 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 456632 # Number of times an access to memory failed due to the cache being blocked
2011-07-10 19:56:09 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-12-05 22:48:34 +01:00
system.cpu.iew.iewSquashCycles 806660 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 52694504 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1340713 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 68945664 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 202125 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 11673351 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 7232744 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1959731 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 45749 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 1091638 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 22198 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 229988 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 630611 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 860599 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 59710531 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 11213503 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 857604 # Number of squashed instructions skipped in execute
2011-07-10 19:56:09 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
2016-12-05 22:48:34 +01:00
system.cpu.iew.exec_nop 3983673 # number of nop insts executed
system.cpu.iew.exec_refs 18029484 # number of memory reference insts executed
system.cpu.iew.exec_branches 9387402 # Number of branches executed
system.cpu.iew.exec_stores 6815981 # Number of stores executed
system.cpu.iew.exec_rate 0.460540 # Inst execution rate
system.cpu.iew.wb_sent 58927059 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 58682245 # cumulative count of insts written-back
system.cpu.iew.wb_producers 29779151 # num instructions producing a value
system.cpu.iew.wb_consumers 41279871 # num instructions consuming a value
system.cpu.iew.wb_rate 0.452609 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.721396 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 12584544 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 661249 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 770143 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 121389515 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.462724 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.395132 # Number of insts commited each cycle
2011-07-10 19:56:09 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-12-05 22:48:34 +01:00
system.cpu.commit.committed_per_cycle::0 101523124 83.63% 83.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 7984339 6.58% 90.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4194668 3.46% 93.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2261790 1.86% 95.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1754136 1.45% 96.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 633873 0.52% 97.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 481376 0.40% 97.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 513083 0.42% 98.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 2043126 1.68% 100.00% # Number of insts commited each cycle
2011-07-10 19:56:09 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-12-05 22:48:34 +01:00
system.cpu.commit.committed_per_cycle::total 121389515 # Number of insts commited each cycle
system.cpu.commit.committedInsts 56169799 # Number of instructions committed
system.cpu.commit.committedOps 56169799 # Number of ops (including micro ops) committed
2011-07-10 19:56:09 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2016-12-05 22:48:34 +01:00
system.cpu.commit.refs 15470470 # Number of memory references committed
system.cpu.commit.loads 9092521 # Number of loads committed
system.cpu.commit.membars 226360 # Number of memory barriers committed
system.cpu.commit.branches 8440690 # Number of branches committed
2015-07-03 16:15:03 +02:00
system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions.
2016-12-05 22:48:34 +01:00
system.cpu.commit.int_insts 52019202 # Number of committed integer instructions.
system.cpu.commit.function_calls 740566 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 3197964 5.69% 5.69% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 36217526 64.48% 70.17% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 60675 0.11% 70.28% # Class of committed instruction
2015-07-03 16:15:03 +02:00
system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction
2016-10-19 12:20:04 +02:00
system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction
2015-09-25 13:27:03 +02:00
system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction
2016-10-19 12:20:04 +02:00
system.cpu.commit.op_class_0::FloatMisc 0 0.00% 70.35% # Class of committed instruction
2015-09-25 13:27:03 +02:00
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction
2016-12-05 22:48:34 +01:00
system.cpu.commit.op_class_0::MemRead 9174285 16.33% 86.69% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 6245839 11.12% 97.81% # Class of committed instruction
2016-10-19 12:20:04 +02:00
system.cpu.commit.op_class_0::FloatMemRead 144596 0.26% 98.06% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemWrite 138067 0.25% 98.31% # Class of committed instruction
2016-10-14 00:21:40 +02:00
system.cpu.commit.op_class_0::IprAccess 949126 1.69% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-12-05 22:48:34 +01:00
system.cpu.commit.op_class_0::total 56169799 # Class of committed instruction
system.cpu.commit.bw_lim_events 2043126 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 187851195 # The number of ROB reads
system.cpu.rob.rob_writes 139687376 # The number of ROB writes
system.cpu.timesIdled 556781 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 6089319 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 3600366244 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 52979108 # Number of Instructions Simulated
system.cpu.committedOps 52979108 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 2.447252 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.447252 # CPI: Total CPI of All Threads
system.cpu.ipc 0.408622 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.408622 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 77910051 # number of integer regfile reads
system.cpu.int_regfile_writes 42617580 # number of integer regfile writes
system.cpu.fp_regfile_reads 166665 # number of floating regfile reads
system.cpu.fp_regfile_writes 175716 # number of floating regfile writes
system.cpu.misc_regfile_reads 2001313 # number of misc regfile reads
system.cpu.misc_regfile_writes 939513 # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 1405851 # number of replacements
2016-10-14 00:21:40 +02:00
system.cpu.dcache.tags.tagsinuse 511.994060 # Cycle average of tags in use
2016-12-05 22:48:34 +01:00
system.cpu.dcache.tags.total_refs 12629128 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1406363 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 8.979992 # Average number of references to valid blocks.
2016-10-14 00:21:40 +02:00
system.cpu.dcache.tags.warmup_cycle 28232500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.994060 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999988 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999988 # Average percentage of cache occupancy
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 414 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-12-05 22:48:34 +01:00
system.cpu.dcache.tags.tag_accesses 67152661 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 67152661 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 8020035 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 8020035 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4180765 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4180765 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 212398 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 212398 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 215680 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 215680 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 12200800 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 12200800 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 12200800 # number of overall hits
system.cpu.dcache.overall_hits::total 12200800 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1817327 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1817327 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1966706 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1966706 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 23570 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 23570 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 93 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 93 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 3784033 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3784033 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3784033 # number of overall misses
system.cpu.dcache.overall_misses::total 3784033 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 45159601500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 45159601500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 92703832258 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 92703832258 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 420302500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 420302500 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 1299500 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 1299500 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 137863433758 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 137863433758 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 137863433758 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 137863433758 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 9837362 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 9837362 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6147471 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6147471 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235968 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 235968 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 215773 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 215773 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 15984833 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 15984833 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 15984833 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 15984833 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184737 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.184737 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319921 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.319921 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.099886 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.099886 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000431 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000431 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.236726 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.236726 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.236726 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.236726 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24849.463800 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 24849.463800 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47136.599094 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 47136.599094 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17832.095885 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17832.095885 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13973.118280 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13973.118280 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 36432.936435 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 36432.936435 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 36432.936435 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 36432.936435 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 4933871 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 2725 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 132268 # number of cycles access was blocked
2016-10-14 00:21:40 +02:00
system.cpu.dcache.blocked::no_targets 28 # number of cycles access was blocked
2016-12-05 22:48:34 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.302076 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 97.321429 # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 844182 # number of writebacks
system.cpu.dcache.writebacks::total 844182 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717105 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 717105 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1677249 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1677249 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6763 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 6763 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2394354 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2394354 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2394354 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2394354 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1100222 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1100222 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289457 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 289457 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16807 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 16807 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 93 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 93 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1389679 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1389679 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1389679 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1389679 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
2016-10-14 00:21:40 +02:00
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses
2016-12-05 22:48:34 +01:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33013560500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 33013560500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14384695133 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 14384695133 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 210983000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 210983000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 1206500 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 1206500 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47398255633 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 47398255633 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47398255633 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 47398255633 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1535352000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1535352000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1535352000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 1535352000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.111841 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.111841 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047086 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047086 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.071226 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.071226 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000431 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000431 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086937 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.086937 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086937 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.086937 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30006.271916 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30006.271916 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49695.447452 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49695.447452 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12553.281371 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12553.281371 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12973.118280 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12973.118280 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34107.341072 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 34107.341072 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34107.341072 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 34107.341072 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221551.515152 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221551.515152 # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92888.378002 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92888.378002 # average overall mshr uncacheable latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 1077480 # number of replacements
system.cpu.icache.tags.tagsinuse 509.004193 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 8783075 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1077988 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 8.147656 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 30284131500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 509.004193 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.994149 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.994149 # Average percentage of cache occupancy
2014-12-02 12:08:25 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id
2016-12-05 22:48:34 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id
2014-12-02 12:08:25 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id
2016-12-05 22:48:34 +01:00
system.cpu.icache.tags.tag_accesses 11008225 # Number of tag accesses
system.cpu.icache.tags.data_accesses 11008225 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 8783075 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 8783075 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 8783075 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 8783075 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 8783075 # number of overall hits
system.cpu.icache.overall_hits::total 8783075 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1146854 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1146854 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1146854 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1146854 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1146854 # number of overall misses
system.cpu.icache.overall_misses::total 1146854 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16347552990 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 16347552990 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 16347552990 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 16347552990 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 16347552990 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 16347552990 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 9929929 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 9929929 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 9929929 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 9929929 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 9929929 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 9929929 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115495 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.115495 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.115495 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.115495 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.115495 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.115495 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14254.258162 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14254.258162 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14254.258162 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14254.258162 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14254.258162 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14254.258162 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 8615 # number of cycles access was blocked
2014-12-02 12:08:25 +01:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-12-05 22:48:34 +01:00
system.cpu.icache.blocked::no_mshrs 335 # number of cycles access was blocked
2014-12-02 12:08:25 +01:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2016-12-05 22:48:34 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 25.716418 # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-12-05 22:48:34 +01:00
system.cpu.icache.writebacks::writebacks 1077480 # number of writebacks
system.cpu.icache.writebacks::total 1077480 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68558 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 68558 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 68558 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 68558 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 68558 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 68558 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1078296 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1078296 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1078296 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1078296 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1078296 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1078296 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14436755994 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 14436755994 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14436755994 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 14436755994 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14436755994 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 14436755994 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108591 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108591 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108591 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.108591 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108591 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.108591 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13388.490724 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13388.490724 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13388.490724 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13388.490724 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13388.490724 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13388.490724 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.tags.replacements 338614 # number of replacements
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.tags.tagsinuse 65420.361718 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4561143 # Total number of references to valid blocks.
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.tags.sampled_refs 404136 # Sample count of references to valid blocks.
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.tags.avg_refs 11.286159 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 6414386000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 255.267028 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 5315.608032 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 59849.486658 # Average occupied blocks per requestor
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.tags.occ_percent::writebacks 0.003895 # Average percentage of cache occupancy
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081110 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.913231 # Average percentage of cache occupancy
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.tags.occ_percent::total 0.998235 # Average percentage of cache occupancy
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 896 # Occupied blocks per task id
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 446 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5595 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 58579 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.tags.tag_accesses 40130556 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 40130556 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 844182 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 844182 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1076791 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1076791 # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 68 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 68 # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 93 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 93 # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 185239 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 185239 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1062874 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1062874 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 831967 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 831967 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1062874 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1017206 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2080080 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 1062874 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1017206 # number of overall hits
system.cpu.l2cache.overall_hits::total 2080080 # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data 7 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 7 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 114698 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 114698 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15038 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 15038 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 274508 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 274508 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 15038 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 389206 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 404244 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 15038 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 389206 # number of overall misses
system.cpu.l2cache.overall_misses::total 404244 # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 357500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 357500 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12064669000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 12064669000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1519815000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 1519815000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22385224000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 22385224000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 1519815000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 34449893000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 35969708000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 1519815000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 34449893000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 35969708000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 844182 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 844182 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 1076791 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1076791 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 75 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 75 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 93 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 93 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 299937 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 299937 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1077912 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 1077912 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1106475 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 1106475 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 1077912 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1406412 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2484324 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1077912 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1406412 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2484324 # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.093333 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.093333 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382407 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.382407 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.013951 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.013951 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248092 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248092 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.013951 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.276737 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.162718 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.013951 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.276737 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.162718 # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 51071.428571 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 51071.428571 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105186.393834 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105186.393834 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 101064.968746 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 101064.968746 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81546.709021 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81546.709021 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 101064.968746 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88513.262899 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 88980.190182 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 101064.968746 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88513.262899 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 88980.190182 # average overall miss latency
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.writebacks::writebacks 75929 # number of writebacks
system.cpu.l2cache.writebacks::total 75929 # number of writebacks
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 7 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 7 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 114698 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 114698 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15037 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15037 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 274508 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 274508 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 15037 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 389206 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 404243 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 15037 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 389206 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 404243 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses
2016-12-05 22:48:34 +01:00
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 287500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 287500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10917688501 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10917688501 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1369353500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1369353500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19646288000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19646288000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1369353500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 30563976501 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 31933330001 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1369353500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 30563976501 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 31933330001 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1448711500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1448711500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1448711500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1448711500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.093333 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.093333 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382407 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382407 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013950 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013950 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248092 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248092 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013950 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276737 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.162718 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013950 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276737 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.162718 # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 41071.428571 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 41071.428571 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95186.389484 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95186.389484 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 91065.604841 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 91065.604841 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71569.090883 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71569.090883 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 91065.604841 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78529.047602 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78995.381493 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 91065.604841 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78529.047602 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78995.381493 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209049.278499 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209049.278499 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87646.651340 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87646.651340 # average overall mshr uncacheable latency
system.cpu.toL2Bus.snoop_filter.tot_requests 4968207 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2483449 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 5093 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.snoop_filter.tot_snoops 951 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 951 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.trans_dist::ReadResp 2191810 # Transaction distribution
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 9599 # Transaction distribution
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.trans_dist::WritebackDirty 920111 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1077480 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 824354 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 75 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 93 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 168 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 299937 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 299937 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1078296 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106636 # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError 47 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3233688 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4252227 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7485915 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137945088 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144089148 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 282034236 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 339553 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 4894016 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 2840416 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.002130 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.046099 # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.snoop_fanout::0 2834367 99.79% 99.79% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 6049 0.21% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.snoop_fanout::total 2840416 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4418829500 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.snoopLayer0.occupancy 292883 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 1618554275 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 2121571625 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
2016-12-05 22:48:34 +01:00
system.iobus.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
2013-05-30 18:54:18 +02:00
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
2016-10-14 00:21:40 +02:00
system.iobus.trans_dist::WriteReq 51151 # Transaction distribution
system.iobus.trans_dist::WriteResp 51151 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5054 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes)
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.iobus.pkt_count_system.bridge.master::total 33058 # Packet count per connected master and slave (bytes)
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.iobus.pkt_count::total 116508 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20216 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes)
2014-09-20 23:18:53 +02:00
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.iobus.pkt_size_system.bridge.master::total 44156 # Cumulative packet size per connected master and slave (bytes)
2014-09-20 23:18:53 +02:00
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.iobus.pkt_size::total 2705764 # Cumulative packet size per connected master and slave (bytes)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer0.occupancy 5364500 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer1.occupancy 813500 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer6.occupancy 10500 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer22.occupancy 178500 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer23.occupancy 14114000 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer24.occupancy 2179500 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer25.occupancy 6040500 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer26.occupancy 88500 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer27.occupancy 216207792 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.respLayer0.occupancy 23459000 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2015-07-03 16:15:03 +02:00
system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
2014-12-02 12:08:25 +01:00
system.iocache.tags.replacements 41685 # number of replacements
2016-12-05 22:48:34 +01:00
system.iocache.tags.tagsinuse 1.265392 # Cycle average of tags in use
2014-12-02 12:08:25 +01:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2016-12-05 22:48:34 +01:00
system.iocache.tags.warmup_cycle 1714257470000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide 1.265392 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide 0.079087 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.079087 # Average percentage of cache occupancy
2014-12-02 12:08:25 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
system.iocache.tags.data_accesses 375525 # Number of data accesses
2016-12-05 22:48:34 +01:00
system.iocache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
2016-04-21 10:48:24 +02:00
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
system.iocache.overall_misses::total 41725 # number of overall misses
2016-12-05 22:48:34 +01:00
system.iocache.ReadReq_miss_latency::tsunami.ide 21940383 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21940383 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::tsunami.ide 4930799409 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4930799409 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 4952739792 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 4952739792 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 4952739792 # number of overall miss cycles
system.iocache.overall_miss_latency::total 4952739792 # number of overall miss cycles
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
2016-04-21 10:48:24 +02:00
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-12-02 12:08:25 +01:00
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2016-12-05 22:48:34 +01:00
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126823.023121 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 126823.023121 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118665.753971 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118665.753971 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 118699.575602 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 118699.575602 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 118699.575602 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 118699.575602 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 1416 # number of cycles access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-12-05 22:48:34 +01:00
system.iocache.blocked::no_mshrs 13 # number of cycles access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2016-12-05 22:48:34 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 108.923077 # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.writebacks::writebacks 41512 # number of writebacks
system.iocache.writebacks::total 41512 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
2016-04-21 10:48:24 +02:00
system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
2016-12-05 22:48:34 +01:00
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13290383 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 13290383 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2850780302 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2850780302 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 2864070685 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 2864070685 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 2864070685 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 2864070685 # number of overall MSHR miss cycles
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-12-02 12:08:25 +01:00
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2016-12-05 22:48:34 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76823.023121 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 76823.023121 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68607.535185 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68607.535185 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68641.598203 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 68641.598203 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68641.598203 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 68641.598203 # average overall mshr miss latency
system.membus.snoop_filter.tot_requests 825546 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 380389 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 528 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-08-12 15:12:59 +02:00
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-12-05 22:48:34 +01:00
system.membus.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::ReadReq 6930 # Transaction distribution
2016-12-05 22:48:34 +01:00
system.membus.trans_dist::ReadResp 296601 # Transaction distribution
2016-10-14 00:21:40 +02:00
system.membus.trans_dist::WriteReq 9599 # Transaction distribution
system.membus.trans_dist::WriteResp 9599 # Transaction distribution
2016-12-05 22:48:34 +01:00
system.membus.trans_dist::WritebackDirty 117441 # Transaction distribution
system.membus.trans_dist::CleanEvict 262065 # Transaction distribution
2016-10-14 00:21:40 +02:00
system.membus.trans_dist::UpgradeReq 137 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.membus.trans_dist::UpgradeResp 3 # Transaction distribution
2016-12-05 22:48:34 +01:00
system.membus.trans_dist::ReadExReq 114568 # Transaction distribution
system.membus.trans_dist::ReadExResp 114568 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 289718 # Transaction distribution
system.membus.trans_dist::BadAddressError 47 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
2016-12-05 22:48:34 +01:00
system.membus.trans_dist::InvalidateResp 124 # Transaction distribution
2016-10-14 00:21:40 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33058 # Packet count per connected master and slave (bytes)
2016-12-05 22:48:34 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145812 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 94 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1178964 # Packet count per connected master and slave (bytes)
2016-02-10 10:08:27 +01:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes)
2016-12-05 22:48:34 +01:00
system.membus.pkt_count::total 1262389 # Packet count per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44156 # Cumulative packet size per connected master and slave (bytes)
2016-12-05 22:48:34 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30701888 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30746044 # Cumulative packet size per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes)
2016-12-05 22:48:34 +01:00
system.membus.pkt_size::total 33403772 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 563 # Total snoops (count)
system.membus.snoopTraffic 27904 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 462504 # Request fanout histogram
system.membus.snoop_fanout::mean 0.001466 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.038259 # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-12-05 22:48:34 +01:00
system.membus.snoop_fanout::0 461826 99.85% 99.85% # Request fanout histogram
system.membus.snoop_fanout::1 678 0.15% 100.00% # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2016-12-05 22:48:34 +01:00
system.membus.snoop_fanout::total 462504 # Request fanout histogram
system.membus.reqLayer0.occupancy 28800500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.membus.reqLayer1.occupancy 1313542061 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.membus.reqLayer2.occupancy 57500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.membus.respLayer1.occupancy 2137882250 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.membus.respLayer2.occupancy 1056521 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
2014-12-02 12:08:25 +01:00
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
2016-12-05 22:48:34 +01:00
system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states
2008-10-21 01:00:07 +02:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
2016-08-12 15:12:59 +02:00
system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed
2016-10-14 00:21:40 +02:00
system.cpu.kern.inst.hwrei 211030 # number of hwrei instructions executed
system.cpu.kern.ipl_count::0 74670 40.97% 40.97% # number of times we switched to this ipl
2012-10-15 14:09:54 +02:00
system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl
2016-10-14 00:21:40 +02:00
system.cpu.kern.ipl_count::22 1881 1.03% 42.07% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31 105578 57.93% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total 182260 # number of times we switched to this ipl
system.cpu.kern.ipl_good::0 73303 49.32% 49.32% # number of times we switched to this ipl from a different ipl
2012-10-15 14:09:54 +02:00
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
2016-10-14 00:21:40 +02:00
system.cpu.kern.ipl_good::22 1881 1.27% 50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73303 49.32% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl
2016-12-05 22:48:34 +01:00
system.cpu.kern.ipl_ticks::0 1819124828000 97.54% 97.54% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21 67368000 0.00% 97.54% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 565513500 0.03% 97.57% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 45251211500 2.43% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1865008921000 # number of cycles we spent at this ipl
2016-10-14 00:21:40 +02:00
system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl
2009-04-22 19:25:17 +02:00
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
2016-10-14 00:21:40 +02:00
system.cpu.kern.ipl_used::31 0.694302 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total 0.815418 # fraction of swpipl calls that actually changed the ipl
2011-07-10 19:56:09 +02:00
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
2015-07-03 16:15:03 +02:00
system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed
2012-10-15 14:09:54 +02:00
system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed
2012-09-10 17:57:37 +02:00
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
2016-10-14 00:21:40 +02:00
system.cpu.kern.callpal::swpipl 175141 91.22% 93.43% # number of callpals executed
system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed
2012-10-15 14:09:54 +02:00
system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
2012-09-10 17:57:37 +02:00
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
2012-10-15 14:09:54 +02:00
system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed
system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed
2016-10-14 00:21:40 +02:00
system.cpu.kern.callpal::rti 5106 2.66% 99.64% # number of callpals executed
2011-07-10 19:56:09 +02:00
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
2016-10-14 00:21:40 +02:00
system.cpu.kern.callpal::total 191988 # number of callpals executed
2016-12-05 22:48:34 +01:00
system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches
2016-10-14 00:21:40 +02:00
system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
2016-12-05 22:48:34 +01:00
system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
2016-10-14 00:21:40 +02:00
system.cpu.kern.mode_good::kernel 1908
system.cpu.kern.mode_good::user 1738
2011-08-19 22:08:06 +02:00
system.cpu.kern.mode_good::idle 170
2016-12-05 22:48:34 +01:00
system.cpu.kern.mode_switch_good::kernel 0.326098 # fraction of useful protection mode switches
2011-07-10 19:56:09 +02:00
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
2016-12-05 22:48:34 +01:00
system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches
2016-10-14 00:21:40 +02:00
system.cpu.kern.mode_switch_good::total 0.393971 # fraction of useful protection mode switches
2016-12-05 22:48:34 +01:00
system.cpu.kern.mode_ticks::kernel 29666586000 1.59% 1.59% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 2759246500 0.15% 1.74% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1832583080500 98.26% 100.00% # number of ticks spent at the given mode
2015-07-03 16:15:03 +02:00
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
2008-10-21 01:00:07 +02:00
---------- End Simulation Statistics ----------
