2008-10-21 01:00:07 +02:00
---------- Begin Simulation Statistics ----------
2016-12-05 22:48:34 +01:00
sim_seconds 1.909484 # Number of seconds simulated
sim_ticks 1909483951500 # Number of ticks simulated
final_tick 1909483951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2008-10-21 01:00:07 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-12-05 22:48:34 +01:00
host_inst_rate 164890 # Simulator instruction rate (inst/s)
host_op_rate 164890 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5556117262 # Simulator tick rate (ticks/s)
host_mem_usage 341236 # Number of bytes of host memory used
host_seconds 343.67 # Real time elapsed on the host
sim_insts 56668174 # Number of instructions simulated
sim_ops 56668174 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-12-05 22:48:34 +01:00
system.physmem.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.inst 857600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 24440064 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 121024 # Number of bytes read from this memory
2016-10-14 00:21:40 +02:00
system.physmem.bytes_read::cpu1.data 888256 # Number of bytes read from this memory
2014-12-02 12:08:05 +01:00
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
2016-12-05 22:48:34 +01:00
system.physmem.bytes_read::total 26307904 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 857600 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 121024 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 978624 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7910400 # Number of bytes written to this memory
system.physmem.bytes_written::total 7910400 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 13400 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 381876 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 1891 # Number of read requests responded to by this memory
2016-10-14 00:21:40 +02:00
system.physmem.num_reads::cpu1.data 13879 # Number of read requests responded to by this memory
2014-12-02 12:08:05 +01:00
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
2016-12-05 22:48:34 +01:00
system.physmem.num_reads::total 411061 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 123600 # Number of write requests responded to by this memory
system.physmem.num_writes::total 123600 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 449127 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 12799303 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 63380 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 465181 # Total read bandwidth from this memory (bytes/s)
2016-10-14 00:21:40 +02:00
system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s)
2016-12-05 22:48:34 +01:00
system.physmem.bw_read::total 13777494 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 449127 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 63380 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 512507 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4142690 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4142690 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4142690 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 449127 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 12799303 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 63380 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 465181 # Total bandwidth to/from this memory (bytes/s)
2016-10-14 00:21:40 +02:00
system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s)
2016-12-05 22:48:34 +01:00
system.physmem.bw_total::total 17920184 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 411061 # Number of read requests accepted
system.physmem.writeReqs 123600 # Number of write requests accepted
system.physmem.readBursts 411061 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 123600 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 26300672 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue
system.physmem.bytesWritten 7909120 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 26307904 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7910400 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue
2015-07-03 16:15:03 +02:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-12-05 22:48:34 +01:00
system.physmem.perBankRdBursts::0 26241 # Per bank write bursts
system.physmem.perBankRdBursts::1 25988 # Per bank write bursts
system.physmem.perBankRdBursts::2 25972 # Per bank write bursts
system.physmem.perBankRdBursts::3 25684 # Per bank write bursts
system.physmem.perBankRdBursts::4 25579 # Per bank write bursts
system.physmem.perBankRdBursts::5 25567 # Per bank write bursts
system.physmem.perBankRdBursts::6 25634 # Per bank write bursts
system.physmem.perBankRdBursts::7 25346 # Per bank write bursts
2016-10-14 00:21:40 +02:00
system.physmem.perBankRdBursts::8 25590 # Per bank write bursts
2016-12-05 22:48:34 +01:00
system.physmem.perBankRdBursts::9 25694 # Per bank write bursts
system.physmem.perBankRdBursts::10 25928 # Per bank write bursts
system.physmem.perBankRdBursts::11 25514 # Per bank write bursts
2016-10-14 00:21:40 +02:00
system.physmem.perBankRdBursts::12 26076 # Per bank write bursts
2016-12-05 22:48:34 +01:00
system.physmem.perBankRdBursts::13 25422 # Per bank write bursts
system.physmem.perBankRdBursts::14 25093 # Per bank write bursts
system.physmem.perBankRdBursts::15 25620 # Per bank write bursts
system.physmem.perBankWrBursts::0 8582 # Per bank write bursts
2016-10-14 00:21:40 +02:00
system.physmem.perBankWrBursts::1 8090 # Per bank write bursts
2016-12-05 22:48:34 +01:00
system.physmem.perBankWrBursts::2 7941 # Per bank write bursts
system.physmem.perBankWrBursts::3 7423 # Per bank write bursts
system.physmem.perBankWrBursts::4 7276 # Per bank write bursts
system.physmem.perBankWrBursts::5 7412 # Per bank write bursts
system.physmem.perBankWrBursts::6 7548 # Per bank write bursts
system.physmem.perBankWrBursts::7 7160 # Per bank write bursts
2016-10-14 00:21:40 +02:00
system.physmem.perBankWrBursts::8 7532 # Per bank write bursts
2016-12-05 22:48:34 +01:00
system.physmem.perBankWrBursts::9 7637 # Per bank write bursts
system.physmem.perBankWrBursts::10 7817 # Per bank write bursts
system.physmem.perBankWrBursts::11 7733 # Per bank write bursts
system.physmem.perBankWrBursts::12 8265 # Per bank write bursts
system.physmem.perBankWrBursts::13 7849 # Per bank write bursts
system.physmem.perBankWrBursts::14 7512 # Per bank write bursts
system.physmem.perBankWrBursts::15 7803 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2016-12-05 22:48:34 +01:00
system.physmem.numWrRetry 80 # Number of times write queue was full causing retry
system.physmem.totGap 1909479571500 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-12-05 22:48:34 +01:00
system.physmem.readPktSize::6 411061 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2016-12-05 22:48:34 +01:00
system.physmem.writePktSize::6 123600 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 316679 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 38784 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 30185 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 25115 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 141 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 22 # What read queue length does an incoming req see
2016-10-14 00:21:40 +02:00
system.physmem.rdQLenPdf::6 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 7 # What read queue length does an incoming req see
2014-09-03 13:42:59 +02:00
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
2014-06-22 23:33:09 +02:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2016-12-05 22:48:34 +01:00
system.physmem.wrQLenPdf::15 1477 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 3412 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4577 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5796 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6656 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 7441 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 8582 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 7129 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 7665 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 8220 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 7944 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7247 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7324 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7178 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7546 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6498 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 6754 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 798 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 487 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 326 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 272 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 275 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 245 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 278 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 286 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 283 # What write queue length does an incoming req see
2016-10-14 00:21:40 +02:00
system.physmem.wrQLenPdf::43 340 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 374 # What write queue length does an incoming req see
2016-12-05 22:48:34 +01:00
system.physmem.wrQLenPdf::45 370 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 293 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 324 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 323 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 387 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 313 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 229 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 255 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 217 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 199 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 212 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 274 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 193 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 390 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 387 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 255 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 165 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 213 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 64366 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 531.481590 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 324.184214 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 415.960810 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 14447 22.45% 22.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 11484 17.84% 40.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5025 7.81% 48.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2916 4.53% 52.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2241 3.48% 56.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1886 2.93% 59.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1937 3.01% 62.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1616 2.51% 64.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 22814 35.44% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 64366 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5520 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 74.445833 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 2823.039428 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191 5517 99.95% 99.95% # Reads before turning the bus around for writes
2015-03-02 11:04:20 +01:00
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
2014-09-03 13:42:59 +02:00
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
2016-12-05 22:48:34 +01:00
system.physmem.rdPerTurnAround::total 5520 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5520 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 22.387681 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.753213 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 23.953412 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23 4982 90.25% 90.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31 46 0.83% 91.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39 181 3.28% 94.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47 8 0.14% 94.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55 3 0.05% 94.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63 15 0.27% 94.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71 3 0.05% 94.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79 1 0.02% 94.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87 37 0.67% 95.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95 6 0.11% 95.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103 147 2.66% 98.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111 11 0.20% 98.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119 11 0.20% 98.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127 1 0.02% 98.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135 13 0.24% 99.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143 5 0.09% 99.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159 2 0.04% 99.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167 2 0.04% 99.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175 4 0.07% 99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183 6 0.11% 99.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191 8 0.14% 99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199 11 0.20% 99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215 1 0.02% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-223 8 0.14% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231 6 0.11% 99.96% # Writes before turning the bus around for reads
2016-10-14 00:21:40 +02:00
system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads
2016-12-05 22:48:34 +01:00
system.physmem.wrPerTurnAround::total 5520 # Writes before turning the bus around for reads
system.physmem.totQLat 8180795500 # Total ticks spent queuing
system.physmem.totMemAccLat 15886070500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2054740000 # Total ticks spent in databus transfers
system.physmem.avgQLat 19907.13 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-12-05 22:48:34 +01:00
system.physmem.avgMemAccLat 38657.13 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 4.14 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 4.14 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-07-03 16:15:03 +02:00
system.physmem.busUtil 0.14 # Data bus utilization in percentage
2014-09-03 13:42:59 +02:00
system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
2015-07-03 16:15:03 +02:00
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
2016-12-05 22:48:34 +01:00
system.physmem.avgRdQLen 2.22 # Average read queue length when enqueuing
system.physmem.avgWrQLen 25.94 # Average write queue length when enqueuing
system.physmem.readRowHits 370615 # Number of row buffer hits during reads
system.physmem.writeRowHits 99546 # Number of row buffer hits during writes
2016-10-14 00:21:40 +02:00
system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads
2016-12-05 22:48:34 +01:00
system.physmem.writeRowHitRate 80.54 # Row buffer hit rate for writes
system.physmem.avgGap 3571383.68 # Average gap between requests
2016-10-14 00:21:40 +02:00
system.physmem.pageHitRate 87.95 # Row buffer hit rate, read and write combined
2016-12-05 22:48:34 +01:00
system.physmem_0.actEnergy 229044060 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 121739805 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1470918540 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 320675040 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3850719600.000001 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 4272567240 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 246889440 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 8425769640 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 4664365920 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 449143940805 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 472747584480 # Total energy per rank (pJ)
system.physmem_0.averagePower 247.578716 # Core power per rank (mW)
system.physmem_0.totalIdleTime 1899455525250 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 389729500 # Time in different power states
system.physmem_0.memoryStateTime::REF 1635812000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 1868844860000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 12146835250 # Time in different power states
system.physmem_0.memoryStateTime::ACT 7989359750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 18477355000 # Time in different power states
system.physmem_1.actEnergy 230536320 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 122529165 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1463250180 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 324412560 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3755450400.000001 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 4276202130 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 236380800 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 8298087360 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 4412246880 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 449354887095 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 472475862540 # Total energy per rank (pJ)
system.physmem_1.averagePower 247.436414 # Core power per rank (mW)
system.physmem_1.totalIdleTime 1899482388000 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 371395250 # Time in different power states
system.physmem_1.memoryStateTime::REF 1595272000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 1869798792500 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 11490281750 # Time in different power states
system.physmem_1.memoryStateTime::ACT 8030486500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 18197723500 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.cpu0.branchPred.lookups 16749334 # Number of BP lookups
system.cpu0.branchPred.condPredicted 14325553 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 462257 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 10374415 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 4757954 # Number of BTB hits
2014-12-02 12:08:05 +01:00
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-12-05 22:48:34 +01:00
system.cpu0.branchPred.BTBHitPct 45.862384 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 926589 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 34524 # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups 4807269 # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits 496703 # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses 4310566 # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted 206845 # Number of mispredicted indirect branches.
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2011-07-10 19:56:09 +02:00
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
2016-12-05 22:48:34 +01:00
system.cpu0.dtb.read_hits 9423503 # DTB read hits
system.cpu0.dtb.read_misses 34044 # DTB read misses
system.cpu0.dtb.read_acv 602 # DTB read access violations
system.cpu0.dtb.read_accesses 567323 # DTB read accesses
system.cpu0.dtb.write_hits 5707426 # DTB write hits
system.cpu0.dtb.write_misses 8375 # DTB write misses
system.cpu0.dtb.write_acv 432 # DTB write access violations
system.cpu0.dtb.write_accesses 185068 # DTB write accesses
system.cpu0.dtb.data_hits 15130929 # DTB hits
system.cpu0.dtb.data_misses 42419 # DTB misses
system.cpu0.dtb.data_acv 1034 # DTB access violations
system.cpu0.dtb.data_accesses 752391 # DTB accesses
system.cpu0.itb.fetch_hits 1309826 # ITB hits
system.cpu0.itb.fetch_misses 6979 # ITB misses
system.cpu0.itb.fetch_acv 608 # ITB acv
system.cpu0.itb.fetch_accesses 1316805 # ITB accesses
2011-07-10 19:56:09 +02:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
2016-12-05 22:48:34 +01:00
system.cpu0.numPwrStateTransitions 12955 # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples 6478 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean 285544950.833745 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev 440803858.104390 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10 6477 99.98% 100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
2016-06-06 18:16:44 +02:00
system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state
2016-12-05 22:48:34 +01:00
system.cpu0.pwrStateClkGateDist::total 6478 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON 59723759999 # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849760191501 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 119453997 # number of cpu cycles simulated
2011-07-10 19:56:09 +02:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-12-05 22:48:34 +01:00
system.cpu0.fetch.icacheStallCycles 25744550 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 73396662 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 16749334 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 6181246 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 86853986 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 1333740 # Number of cycles fetch has spent squashing
2016-10-14 00:21:40 +02:00
system.cpu0.fetch.TlbCycles 1 # Number of cycles fetch has spent waiting for tlb
2016-12-05 22:48:34 +01:00
system.cpu0.fetch.MiscStallCycles 29854 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 138979 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 426939 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 8448706 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 314842 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples 113861488 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.644614 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 1.955082 # Number of instructions fetched each cycle (Total)
2011-07-10 19:56:09 +02:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-12-05 22:48:34 +01:00
system.cpu0.fetch.rateDist::0 100232411 88.03% 88.03% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 886423 0.78% 88.81% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 1866278 1.64% 90.45% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 772305 0.68% 91.13% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 2608424 2.29% 93.42% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 580288 0.51% 93.93% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 680998 0.60% 94.52% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 835244 0.73% 95.26% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 5399117 4.74% 100.00% # Number of instructions fetched each cycle (Total)
2011-07-10 19:56:09 +02:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2016-12-05 22:48:34 +01:00
system.cpu0.fetch.rateDist::total 113861488 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.140216 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.614435 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 20674409 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 82009104 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 8737077 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 1802336 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 638561 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 612096 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 28873 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 63730808 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 85670 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 638561 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 21537349 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 55655987 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 17571911 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 9607617 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 8850061 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 61287779 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 195487 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 2001492 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 247198 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 4966656 # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands 41332689 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 73998496 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 73867344 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 122420 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 33806898 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 7525791 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 1421231 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 231053 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 12310515 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 9804371 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 6066029 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1436076 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 935297 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 54210960 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1853678 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 52617678 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 75373 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 9354795 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 4029114 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 1289525 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 113861488 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.462120 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.203620 # Number of insts issued each cycle
2011-07-10 19:56:09 +02:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-12-05 22:48:34 +01:00
system.cpu0.iq.issued_per_cycle::0 92467205 81.21% 81.21% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 9144132 8.03% 89.24% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 3819872 3.35% 92.60% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 2741139 2.41% 95.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 2853722 2.51% 97.51% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 1412384 1.24% 98.75% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 945124 0.83% 99.58% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 360447 0.32% 99.90% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 117463 0.10% 100.00% # Number of insts issued each cycle
2011-07-10 19:56:09 +02:00
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2016-12-05 22:48:34 +01:00
system.cpu0.iq.issued_per_cycle::total 113861488 # Number of insts issued each cycle
2011-07-10 19:56:09 +02:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-12-05 22:48:34 +01:00
system.cpu0.iq.fu_full::IntAlu 167498 16.72% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMisc 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 489097 48.82% 65.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 297116 29.66% 95.20% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMemRead 26550 2.65% 97.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMemWrite 21561 2.15% 100.00% # attempts to use FU when none available
2011-07-10 19:56:09 +02:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2016-12-05 22:48:34 +01:00
system.cpu0.iq.FU_type_0::No_OpClass 2541 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 36104376 68.62% 68.62% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 55717 0.11% 68.73% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.73% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 25404 0.05% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 9732272 18.50% 87.27% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 5684196 10.80% 98.08% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMemRead 122332 0.23% 98.31% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMemWrite 110816 0.21% 98.52% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 778757 1.48% 100.00% # Type of FU issued
2011-07-10 19:56:09 +02:00
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-12-05 22:48:34 +01:00
system.cpu0.iq.FU_type_0::total 52617678 # Type of FU issued
system.cpu0.iq.rate 0.440485 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 1001822 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.019040 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 219604859 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 65162997 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 50893555 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 569180 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 274272 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 257685 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 53309029 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 307930 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 608555 # Number of loads that had data forwarded from stores
2011-07-10 19:56:09 +02:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-12-05 22:48:34 +01:00
system.cpu0.iew.lsq.thread0.squashedLoads 1940010 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 3457 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 18333 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 663404 # Number of stores squashed
2011-07-10 19:56:09 +02:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-12-05 22:48:34 +01:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 18340 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 362661 # Number of times an access to memory failed due to the cache being blocked
2011-07-10 19:56:09 +02:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-12-05 22:48:34 +01:00
system.cpu0.iew.iewSquashCycles 638561 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 52164612 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 1031418 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 59600447 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 153776 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 9804371 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 6066029 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 1643055 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 39666 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 791016 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 18333 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 179892 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 504278 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 684170 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 51936356 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 9483037 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 681322 # Number of squashed instructions skipped in execute
2011-07-10 19:56:09 +02:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
2016-12-05 22:48:34 +01:00
system.cpu0.iew.exec_nop 3535809 # number of nop insts executed
system.cpu0.iew.exec_refs 15215766 # number of memory reference insts executed
system.cpu0.iew.exec_branches 8258108 # Number of branches executed
system.cpu0.iew.exec_stores 5732729 # Number of stores executed
system.cpu0.iew.exec_rate 0.434781 # Inst execution rate
system.cpu0.iew.wb_sent 51332154 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 51151240 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 26231692 # num instructions producing a value
system.cpu0.iew.wb_consumers 36261297 # num instructions consuming a value
system.cpu0.iew.wb_rate 0.428209 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.723407 # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts 9848757 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 564153 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 610679 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 112148809 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.442210 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.364760 # Number of insts commited each cycle
2011-04-20 03:45:23 +02:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-12-05 22:48:34 +01:00
system.cpu0.commit.committed_per_cycle::0 94602668 84.35% 84.35% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 6980008 6.22% 90.58% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 3776982 3.37% 93.95% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 2002013 1.79% 95.73% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 1561505 1.39% 97.12% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 569175 0.51% 97.63% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 418696 0.37% 98.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 452906 0.40% 98.41% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1784856 1.59% 100.00% # Number of insts commited each cycle
2011-04-20 03:45:23 +02:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-12-05 22:48:34 +01:00
system.cpu0.commit.committed_per_cycle::total 112148809 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 49593272 # Number of instructions committed
system.cpu0.commit.committedOps 49593272 # Number of ops (including micro ops) committed
2011-04-20 03:45:23 +02:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
2016-12-05 22:48:34 +01:00
system.cpu0.commit.refs 13266986 # Number of memory references committed
system.cpu0.commit.loads 7864361 # Number of loads committed
system.cpu0.commit.membars 192313 # Number of memory barriers committed
system.cpu0.commit.branches 7507748 # Number of branches committed
system.cpu0.commit.fp_insts 248828 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 45902219 # Number of committed integer instructions.
system.cpu0.commit.function_calls 632222 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 2885965 5.82% 5.82% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu 32382704 65.30% 71.12% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 54404 0.11% 71.23% # Class of committed instruction
2016-10-14 00:21:40 +02:00
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.23% # Class of committed instruction
2016-12-05 22:48:34 +01:00
system.cpu0.commit.op_class_0::FloatAdd 24932 0.05% 71.28% # Class of committed instruction
2016-10-14 00:21:40 +02:00
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.28% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.28% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.28% # Class of committed instruction
2016-10-19 12:20:04 +02:00
system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 71.28% # Class of committed instruction
2016-10-14 00:21:40 +02:00
system.cpu0.commit.op_class_0::FloatDiv 1267 0.00% 71.28% # Class of committed instruction
2016-10-19 12:20:04 +02:00
system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 71.28% # Class of committed instruction
2016-10-14 00:21:40 +02:00
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.28% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.28% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.28% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.28% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.28% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.28% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.28% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.28% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.28% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.28% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.28% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.28% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.28% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.28% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.28% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.28% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.28% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.28% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.28% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.28% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.28% # Class of committed instruction
2016-12-05 22:48:34 +01:00
system.cpu0.commit.op_class_0::MemRead 7943457 16.02% 87.30% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 5299157 10.69% 97.98% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMemRead 113217 0.23% 98.21% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMemWrite 109412 0.22% 98.43% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 778757 1.57% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-12-05 22:48:34 +01:00
system.cpu0.commit.op_class_0::total 49593272 # Class of committed instruction
system.cpu0.commit.bw_lim_events 1784856 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 169631516 # The number of ROB reads
system.cpu0.rob.rob_writes 120597460 # The number of ROB writes
system.cpu0.timesIdled 479927 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 5592509 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 3698912124 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 46709842 # Number of Instructions Simulated
system.cpu0.committedOps 46709842 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 2.557362 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 2.557362 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.391028 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.391028 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 67996788 # number of integer regfile reads
system.cpu0.int_regfile_writes 37259313 # number of integer regfile writes
system.cpu0.fp_regfile_reads 121463 # number of floating regfile reads
system.cpu0.fp_regfile_writes 130119 # number of floating regfile writes
system.cpu0.misc_regfile_reads 1657761 # number of misc regfile reads
system.cpu0.misc_regfile_writes 782234 # number of misc regfile writes
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 1252644 # number of replacements
system.cpu0.dcache.tags.tagsinuse 506.062362 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 10655904 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1253074 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 8.503811 # Average number of references to valid blocks.
2016-10-14 00:21:40 +02:00
system.cpu0.dcache.tags.warmup_cycle 28164500 # Cycle when the warmup percentage was hit.
2016-12-05 22:48:34 +01:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.062362 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988403 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.988403 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 409 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.839844 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 56905298 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 56905298 # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 6776069 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 6776069 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3521167 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 3521167 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174528 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 174528 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 179927 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 179927 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 10297236 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 10297236 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 10297236 # number of overall hits
system.cpu0.dcache.overall_hits::total 10297236 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 1551541 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1551541 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1684277 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1684277 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20385 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 20385 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3031 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 3031 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 3235818 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 3235818 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 3235818 # number of overall misses
system.cpu0.dcache.overall_misses::total 3235818 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41541989000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 41541989000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 84989668522 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 84989668522 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 383673500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 383673500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 17049500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 17049500 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 126531657522 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 126531657522 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 126531657522 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 126531657522 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 8327610 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 8327610 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5205444 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 5205444 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194913 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 194913 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182958 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 182958 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 13533054 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 13533054 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 13533054 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 13533054 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.186313 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.186313 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323561 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.323561 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104585 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.104585 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016567 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.016567 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.239105 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.239105 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.239105 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.239105 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26774.664028 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 26774.664028 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50460.624067 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 50460.624067 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18821.363748 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18821.363748 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5625.041241 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5625.041241 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39103.453137 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 39103.453137 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39103.453137 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 39103.453137 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 4484959 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 5749 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 107356 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 120 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.776510 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 47.908333 # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 737573 # number of writebacks
system.cpu0.dcache.writebacks::total 737573 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 550277 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 550277 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1432731 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1432731 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5546 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5546 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1983008 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1983008 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1983008 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1983008 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1001264 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 1001264 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251546 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 251546 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14839 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14839 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3031 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 3031 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 1252810 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 1252810 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 1252810 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 1252810 # number of overall MSHR misses
2016-10-14 00:21:40 +02:00
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 6977 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 6977 # number of ReadReq MSHR uncacheable
2016-12-05 22:48:34 +01:00
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9910 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9910 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16887 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16887 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 31631751000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 31631751000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 13189939409 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13189939409 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 172118000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 172118000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14018500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14018500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 44821690409 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 44821690409 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 44821690409 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 44821690409 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1557150500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1557150500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1557150500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1557150500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120234 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.120234 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048324 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048324 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.076131 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.076131 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016567 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016567 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092574 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.092574 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092574 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.092574 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31591.818941 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31591.818941 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 52435.496525 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 52435.496525 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11599.029584 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11599.029584 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4625.041241 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4625.041241 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35776.925798 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35776.925798 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35776.925798 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35776.925798 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223183.388276 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223183.388276 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92210.013620 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92210.013620 # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 892272 # number of replacements
system.cpu0.icache.tags.tagsinuse 509.350681 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 7503325 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 892783 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 8.404422 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 30334536500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.350681 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994826 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.994826 # Average percentage of cache occupancy
2016-08-12 15:12:59 +02:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.cpu0.icache.tags.age_task_id_blocks_1024::2 501 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
2016-12-05 22:48:34 +01:00
system.cpu0.icache.tags.tag_accesses 9341754 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 9341754 # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 7503325 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 7503325 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 7503325 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 7503325 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 7503325 # number of overall hits
system.cpu0.icache.overall_hits::total 7503325 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 945376 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 945376 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 945376 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 945376 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 945376 # number of overall misses
system.cpu0.icache.overall_misses::total 945376 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13858102494 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 13858102494 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 13858102494 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 13858102494 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 13858102494 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 13858102494 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 8448701 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 8448701 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 8448701 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 8448701 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 8448701 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 8448701 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111896 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.111896 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111896 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.111896 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111896 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.111896 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14658.826217 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14658.826217 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14658.826217 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14658.826217 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14658.826217 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14658.826217 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 6578 # number of cycles access was blocked
2014-12-02 12:08:05 +01:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-12-05 22:48:34 +01:00
system.cpu0.icache.blocked::no_mshrs 245 # number of cycles access was blocked
2014-12-02 12:08:05 +01:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
2016-12-05 22:48:34 +01:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.848980 # average number of cycles each access was blocked
2014-12-02 12:08:05 +01:00
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-12-05 22:48:34 +01:00
system.cpu0.icache.writebacks::writebacks 892272 # number of writebacks
system.cpu0.icache.writebacks::total 892272 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 52323 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 52323 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 52323 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 52323 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 52323 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 52323 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 893053 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 893053 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 893053 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 893053 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 893053 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 893053 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12259429995 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 12259429995 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12259429995 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 12259429995 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12259429995 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 12259429995 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105703 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.105703 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.105703 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13727.550319 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13727.550319 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13727.550319 # average overall mshr miss latency
system.cpu1.branchPred.lookups 4441555 # Number of BP lookups
system.cpu1.branchPred.condPredicted 3820450 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 114047 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 2322340 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 883836 # Number of BTB hits
2014-12-02 12:08:05 +01:00
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-12-05 22:48:34 +01:00
system.cpu1.branchPred.BTBHitPct 38.057993 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 229553 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 8671 # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups 1262341 # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits 163265 # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses 1099076 # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted 40828 # Number of mispredicted indirect branches.
2014-12-02 12:08:05 +01:00
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
2016-12-05 22:48:34 +01:00
system.cpu1.dtb.read_hits 2431988 # DTB read hits
system.cpu1.dtb.read_misses 15687 # DTB read misses
system.cpu1.dtb.read_acv 78 # DTB read access violations
system.cpu1.dtb.read_accesses 432427 # DTB read accesses
system.cpu1.dtb.write_hits 1439876 # DTB write hits
system.cpu1.dtb.write_misses 3853 # DTB write misses
system.cpu1.dtb.write_acv 69 # DTB write access violations
system.cpu1.dtb.write_accesses 163205 # DTB write accesses
system.cpu1.dtb.data_hits 3871864 # DTB hits
system.cpu1.dtb.data_misses 19540 # DTB misses
system.cpu1.dtb.data_acv 147 # DTB access violations
system.cpu1.dtb.data_accesses 595632 # DTB accesses
system.cpu1.itb.fetch_hits 677957 # ITB hits
system.cpu1.itb.fetch_misses 3440 # ITB misses
system.cpu1.itb.fetch_acv 149 # ITB acv
system.cpu1.itb.fetch_accesses 681397 # ITB accesses
2014-12-02 12:08:05 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
2016-12-05 22:48:34 +01:00
system.cpu1.numPwrStateTransitions 5092 # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples 2546 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean 746545753.142184 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev 396892720.756326 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10 2546 100.00% 100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value 350000 # Distribution of time spent in the clock gated state
2016-10-14 00:21:40 +02:00
system.cpu1.pwrStateClkGateDist::max_value 975495000 # Distribution of time spent in the clock gated state
2016-12-05 22:48:34 +01:00
system.cpu1.pwrStateClkGateDist::total 2546 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON 8778464000 # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 1900705487500 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 17559475 # number of cpu cycles simulated
2014-12-02 12:08:05 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-12-05 22:48:34 +01:00
system.cpu1.fetch.icacheStallCycles 7089129 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 17628986 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 4441555 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 1276654 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 9239971 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 379390 # Number of cycles fetch has spent squashing
system.cpu1.fetch.MiscStallCycles 26991 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 67759 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 51232 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 58 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 1981137 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 84838 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples 16664835 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.057855 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.464288 # Number of instructions fetched each cycle (Total)
2011-07-10 19:56:09 +02:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-12-05 22:48:34 +01:00
system.cpu1.fetch.rateDist::0 13565594 81.40% 81.40% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 195508 1.17% 82.58% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 331371 1.99% 84.56% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 236250 1.42% 85.98% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 403775 2.42% 88.40% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 149802 0.90% 89.30% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 175422 1.05% 90.36% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 211560 1.27% 91.63% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 1395553 8.37% 100.00% # Number of instructions fetched each cycle (Total)
2011-07-10 19:56:09 +02:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2016-12-05 22:48:34 +01:00
system.cpu1.fetch.rateDist::total 16664835 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.252943 # Number of branch fetches per cycle
system.cpu1.fetch.rate 1.003959 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 5800433 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 8202202 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 2197206 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 282756 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 182237 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 153534 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 7597 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 14400936 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 23892 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 182237 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 5989487 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 906248 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 6023778 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 2292128 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 1270955 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 13634993 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 3736 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 109479 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 34532 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 648624 # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands 9050025 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 16251882 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 16185746 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 59544 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 7082137 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 1967880 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 511648 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 53659 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 2285085 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 2543631 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 1545283 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 323334 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 171078 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 11953372 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 586667 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 11470583 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 27894 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 2581702 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 1224765 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 432970 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 16664835 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.688311 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.414763 # Number of insts issued each cycle
2011-07-10 19:56:09 +02:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-12-05 22:48:34 +01:00
system.cpu1.iq.issued_per_cycle::0 11964424 71.79% 71.79% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 2022081 12.13% 83.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 866450 5.20% 89.13% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 621081 3.73% 92.85% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 573042 3.44% 96.29% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 300412 1.80% 98.10% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 196836 1.18% 99.28% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 86957 0.52% 99.80% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 33552 0.20% 100.00% # Number of insts issued each cycle
2011-07-10 19:56:09 +02:00
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2016-12-05 22:48:34 +01:00
system.cpu1.iq.issued_per_cycle::total 16664835 # Number of insts issued each cycle
2011-07-10 19:56:09 +02:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-12-05 22:48:34 +01:00
system.cpu1.iq.fu_full::IntAlu 33610 10.34% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMisc 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 173421 53.34% 63.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 102626 31.57% 95.25% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMemRead 8052 2.48% 97.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMemWrite 7405 2.28% 100.00% # attempts to use FU when none available
2011-07-10 19:56:09 +02:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2016-08-12 15:12:59 +02:00
system.cpu1.iq.FU_type_0::No_OpClass 4751 0.04% 0.04% # Type of FU issued
2016-12-05 22:48:34 +01:00
system.cpu1.iq.FU_type_0::IntAlu 7105969 61.95% 61.99% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 17120 0.15% 62.14% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 14007 0.12% 62.26% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.26% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.26% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.26% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 62.26% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 2511504 21.90% 84.18% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 1426032 12.43% 96.61% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMemRead 45143 0.39% 97.00% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMemWrite 43776 0.38% 97.39% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 299906 2.61% 100.00% # Type of FU issued
2011-07-10 19:56:09 +02:00
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-12-05 22:48:34 +01:00
system.cpu1.iq.FU_type_0::total 11470583 # Type of FU issued
system.cpu1.iq.rate 0.653242 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 325114 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.028343 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 39732906 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 15018676 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 10950208 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 226102 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 108058 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 105069 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 11670188 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 120758 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 118257 # Number of loads that had data forwarded from stores
2011-07-10 19:56:09 +02:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-12-05 22:48:34 +01:00
system.cpu1.iew.lsq.thread0.squashedLoads 553253 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 1093 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 5172 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 179987 # Number of stores squashed
2011-07-10 19:56:09 +02:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-12-05 22:48:34 +01:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 535 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 99855 # Number of times an access to memory failed due to the cache being blocked
2011-07-10 19:56:09 +02:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-12-05 22:48:34 +01:00
system.cpu1.iew.iewSquashCycles 182237 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 561579 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 275117 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 13190679 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 58497 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 2543631 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 1545283 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 532703 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 6805 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 266988 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 5172 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 45989 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 148806 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 194795 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 11280251 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 2456871 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 190331 # Number of squashed instructions skipped in execute
2011-07-10 19:56:09 +02:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
2016-12-05 22:48:34 +01:00
system.cpu1.iew.exec_nop 650640 # number of nop insts executed
system.cpu1.iew.exec_refs 3907176 # number of memory reference insts executed
system.cpu1.iew.exec_branches 1689156 # Number of branches executed
system.cpu1.iew.exec_stores 1450305 # Number of stores executed
system.cpu1.iew.exec_rate 0.642403 # Inst execution rate
system.cpu1.iew.wb_sent 11110028 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 11055277 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 5286560 # num instructions producing a value
system.cpu1.iew.wb_consumers 7445661 # num instructions consuming a value
system.cpu1.iew.wb_rate 0.629590 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.710019 # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts 2598878 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 153697 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 169517 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 16202334 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.644600 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.619525 # Number of insts commited each cycle
2011-04-20 03:45:23 +02:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-12-05 22:48:34 +01:00
system.cpu1.commit.committed_per_cycle::0 12420063 76.66% 76.66% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 1746761 10.78% 87.44% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 624490 3.85% 91.29% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 388127 2.40% 93.69% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 294767 1.82% 95.51% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 125393 0.77% 96.28% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 112323 0.69% 96.97% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 119344 0.74% 97.71% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 371066 2.29% 100.00% # Number of insts commited each cycle
2011-04-20 03:45:23 +02:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-12-05 22:48:34 +01:00
system.cpu1.commit.committed_per_cycle::total 16202334 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 10444029 # Number of instructions committed
system.cpu1.commit.committedOps 10444029 # Number of ops (including micro ops) committed
2011-04-20 03:45:23 +02:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
2016-12-05 22:48:34 +01:00
system.cpu1.commit.refs 3355674 # Number of memory references committed
system.cpu1.commit.loads 1990378 # Number of loads committed
system.cpu1.commit.membars 48933 # Number of memory barriers committed
system.cpu1.commit.branches 1499197 # Number of branches committed
system.cpu1.commit.fp_insts 102946 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 9701123 # Number of committed integer instructions.
system.cpu1.commit.function_calls 163891 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 490447 4.70% 4.70% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu 6215282 59.51% 64.21% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 16829 0.16% 64.37% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.37% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 13998 0.13% 64.50% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.50% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.50% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.50% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 64.50% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.52% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 64.52% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.52% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.52% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.52% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.52% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.52% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.52% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.52% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.52% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.52% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.52% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.52% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.52% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.52% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.52% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.52% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.52% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.52% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.52% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.52% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.52% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.52% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 1994471 19.10% 83.62% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 1324148 12.68% 96.30% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMemRead 44840 0.43% 96.73% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMemWrite 41733 0.40% 97.13% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 299906 2.87% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-12-05 22:48:34 +01:00
system.cpu1.commit.op_class_0::total 10444029 # Class of committed instruction
system.cpu1.commit.bw_lim_events 371066 # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads 28763808 # The number of ROB reads
system.cpu1.rob.rob_writes 26546353 # The number of ROB writes
system.cpu1.timesIdled 134909 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 894640 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 3801408429 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 9958332 # Number of Instructions Simulated
system.cpu1.committedOps 9958332 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 1.763295 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.763295 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.567120 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.567120 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 14511646 # number of integer regfile reads
system.cpu1.int_regfile_writes 7905629 # number of integer regfile writes
system.cpu1.fp_regfile_reads 58867 # number of floating regfile reads
system.cpu1.fp_regfile_writes 57930 # number of floating regfile writes
system.cpu1.misc_regfile_reads 573957 # number of misc regfile reads
system.cpu1.misc_regfile_writes 245081 # number of misc regfile writes
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 131073 # number of replacements
system.cpu1.dcache.tags.tagsinuse 488.756113 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 3063603 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 131585 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 23.282312 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 49534380500 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 488.756113 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.954602 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.954602 # Average percentage of cache occupancy
2016-02-10 10:08:27 +01:00
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-12-05 22:48:34 +01:00
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id
2016-02-10 10:08:27 +01:00
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-12-05 22:48:34 +01:00
system.cpu1.dcache.tags.tag_accesses 14519091 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 14519091 # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 1948296 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 1948296 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 1026442 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 1026442 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40668 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 40668 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 37243 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 37243 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 2974738 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 2974738 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 2974738 # number of overall hits
system.cpu1.dcache.overall_hits::total 2974738 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 241303 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 241303 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 292103 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 292103 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5304 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 5304 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3101 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 3101 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 533406 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 533406 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 533406 # number of overall misses
system.cpu1.dcache.overall_misses::total 533406 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3375705500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 3375705500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12203212844 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 12203212844 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 54365500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 54365500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 17261500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 17261500 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 15578918344 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 15578918344 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 15578918344 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 15578918344 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 2189599 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 2189599 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 1318545 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 1318545 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 45972 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 45972 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 40344 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 40344 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 3508144 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 3508144 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 3508144 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 3508144 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110204 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.110204 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.221534 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.221534 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.115375 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.115375 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.076864 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.076864 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.152048 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.152048 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.152048 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.152048 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13989.488320 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 13989.488320 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41777.088370 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 41777.088370 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10249.905732 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10249.905732 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5566.430184 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5566.430184 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29206.492510 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 29206.492510 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29206.492510 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 29206.492510 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 720965 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 386 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 24769 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 19 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 29.107554 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 20.315789 # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks 84598 # number of writebacks
system.cpu1.dcache.writebacks::total 84598 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148074 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 148074 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 243671 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 243671 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 852 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 852 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 391745 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 391745 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 391745 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 391745 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 93229 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 93229 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 48432 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 48432 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4452 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4452 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3100 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 3100 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 141661 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 141661 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 141661 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 141661 # number of overall MSHR misses
2016-10-14 00:21:40 +02:00
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 218 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 218 # number of ReadReq MSHR uncacheable
2016-12-05 22:48:34 +01:00
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3157 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3157 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3375 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3375 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1262260500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1262260500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1962212693 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1962212693 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 40045500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 40045500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14161500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14161500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3224473193 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 3224473193 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3224473193 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 3224473193 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 41860500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 41860500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 41860500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 41860500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042578 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042578 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036731 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036731 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.096842 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.096842 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.076839 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.076839 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040381 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.040381 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040381 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.040381 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13539.354707 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13539.354707 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40514.797923 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40514.797923 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8994.946092 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8994.946092 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4568.225806 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4568.225806 # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22761.897721 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22761.897721 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22761.897721 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22761.897721 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 192020.642202 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192020.642202 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 12403.111111 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 12403.111111 # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 256867 # number of replacements
system.cpu1.icache.tags.tagsinuse 470.812016 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 1711658 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 257379 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 6.650341 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 1882992885500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.812016 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919555 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.919555 # Average percentage of cache occupancy
2016-10-14 00:21:40 +02:00
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-12-05 22:48:34 +01:00
system.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.cpu1.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
2016-12-05 22:48:34 +01:00
system.cpu1.icache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-12-05 22:48:34 +01:00
system.cpu1.icache.tags.tag_accesses 2238596 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 2238596 # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 1711658 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 1711658 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 1711658 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 1711658 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 1711658 # number of overall hits
system.cpu1.icache.overall_hits::total 1711658 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 269479 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 269479 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 269479 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 269479 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 269479 # number of overall misses
system.cpu1.icache.overall_misses::total 269479 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3760599998 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 3760599998 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 3760599998 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 3760599998 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 3760599998 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 3760599998 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 1981137 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 1981137 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 1981137 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 1981137 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 1981137 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 1981137 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.136022 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.136022 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.136022 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.136022 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.136022 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.136022 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13955.076269 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13955.076269 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13955.076269 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13955.076269 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13955.076269 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13955.076269 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 535 # number of cycles access was blocked
2014-12-02 12:08:05 +01:00
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-12-05 22:48:34 +01:00
system.cpu1.icache.blocked::no_mshrs 47 # number of cycles access was blocked
2014-12-02 12:08:05 +01:00
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
2016-12-05 22:48:34 +01:00
system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.382979 # average number of cycles each access was blocked
2014-12-02 12:08:05 +01:00
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-12-05 22:48:34 +01:00
system.cpu1.icache.writebacks::writebacks 256867 # number of writebacks
system.cpu1.icache.writebacks::total 256867 # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12020 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 12020 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 12020 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 12020 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 12020 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 12020 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 257459 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 257459 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 257459 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 257459 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 257459 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 257459 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3369785998 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 3369785998 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3369785998 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 3369785998 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3369785998 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 3369785998 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.129955 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.129955 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.129955 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.129955 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.129955 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.129955 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13088.631580 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 13088.631580 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 13088.631580 # average overall mshr miss latency
2014-12-02 12:08:05 +01:00
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
2016-12-05 22:48:34 +01:00
system.iobus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
2016-08-12 15:12:59 +02:00
system.iobus.trans_dist::ReadReq 7374 # Transaction distribution
system.iobus.trans_dist::ReadResp 7374 # Transaction distribution
2016-12-05 22:48:34 +01:00
system.iobus.trans_dist::WriteReq 54619 # Transaction distribution
system.iobus.trans_dist::WriteResp 54619 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11924 # Packet count per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes)
2016-07-21 18:19:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
2016-12-05 22:48:34 +01:00
system.iobus.pkt_count_system.bridge.master::total 40524 # Packet count per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes)
2016-12-05 22:48:34 +01:00
system.iobus.pkt_count::total 123986 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47696 # Cumulative packet size per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes)
2016-07-21 18:19:18 +02:00
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
2016-12-05 22:48:34 +01:00
system.iobus.pkt_size_system.bridge.master::total 73922 # Cumulative packet size per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes)
2016-12-05 22:48:34 +01:00
system.iobus.pkt_size::total 2735578 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 12373500 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer1.occupancy 816500 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer6.occupancy 10500 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer22.occupancy 179500 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer23.occupancy 14090000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer24.occupancy 2829500 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer25.occupancy 6041501 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer26.occupancy 89000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer27.occupancy 216274759 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.respLayer0.occupancy 27457000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.respLayer1.occupancy 41958000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
2016-08-12 15:12:59 +02:00
system.iocache.tags.replacements 41699 # number of replacements
2016-12-05 22:48:34 +01:00
system.iocache.tags.tagsinuse 0.506657 # Cycle average of tags in use
2014-12-02 12:08:05 +01:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2016-08-12 15:12:59 +02:00
system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks.
2014-12-02 12:08:05 +01:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2016-12-05 22:48:34 +01:00
system.iocache.tags.warmup_cycle 1714262526000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide 0.506657 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide 0.031666 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.031666 # Average percentage of cache occupancy
2014-12-02 12:08:05 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
2014-12-02 12:08:05 +01:00
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2016-08-12 15:12:59 +02:00
system.iocache.tags.tag_accesses 375579 # Number of tag accesses
system.iocache.tags.data_accesses 375579 # Number of data accesses
2016-12-05 22:48:34 +01:00
system.iocache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
2016-08-12 15:12:59 +02:00
system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses
system.iocache.ReadReq_misses::total 179 # number of ReadReq misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
2016-08-12 15:12:59 +02:00
system.iocache.demand_misses::tsunami.ide 41731 # number of demand (read+write) misses
system.iocache.demand_misses::total 41731 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses
system.iocache.overall_misses::total 41731 # number of overall misses
2016-12-05 22:48:34 +01:00
system.iocache.ReadReq_miss_latency::tsunami.ide 22653383 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 22653383 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::tsunami.ide 4913989376 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4913989376 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 4936642759 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 4936642759 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 4936642759 # number of overall miss cycles
system.iocache.overall_miss_latency::total 4936642759 # number of overall miss cycles
2016-08-12 15:12:59 +02:00
system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
2016-08-12 15:12:59 +02:00
system.iocache.demand_accesses::tsunami.ide 41731 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses
2014-12-02 12:08:05 +01:00
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-12-02 12:08:05 +01:00
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2016-12-05 22:48:34 +01:00
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126555.212291 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 126555.212291 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118261.199846 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118261.199846 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 118296.775994 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 118296.775994 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 118296.775994 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 118296.775994 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 945 # number of cycles access was blocked
2014-12-02 12:08:05 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-12-05 22:48:34 +01:00
system.iocache.blocked::no_mshrs 7 # number of cycles access was blocked
2014-12-02 12:08:05 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2016-12-05 22:48:34 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 135 # average number of cycles each access was blocked
2014-12-02 12:08:05 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2015-09-15 15:14:09 +02:00
system.iocache.writebacks::writebacks 41520 # number of writebacks
system.iocache.writebacks::total 41520 # number of writebacks
2016-08-12 15:12:59 +02:00
system.iocache.ReadReq_mshr_misses::tsunami.ide 179 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
2016-08-12 15:12:59 +02:00
system.iocache.demand_mshr_misses::tsunami.ide 41731 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses
2016-12-05 22:48:34 +01:00
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13703383 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 13703383 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2833958851 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2833958851 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 2847662234 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 2847662234 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 2847662234 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 2847662234 # number of overall MSHR miss cycles
2014-12-02 12:08:05 +01:00
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-12-02 12:08:05 +01:00
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2016-12-05 22:48:34 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76555.212291 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 76555.212291 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68202.706272 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68202.706272 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68238.533321 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 68238.533321 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68238.533321 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 68238.533321 # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 345934 # number of replacements
system.l2c.tags.tagsinuse 65423.183339 # Cycle average of tags in use
system.l2c.tags.total_refs 4331268 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 411456 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 10.526686 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 6416563000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 293.472249 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 5322.167822 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 58815.337446 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 207.084290 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 785.121532 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.004478 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.081210 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.897451 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.003160 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.011980 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.998279 # Average percentage of cache occupancy
2016-10-14 00:21:40 +02:00
system.l2c.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id
2016-12-05 22:48:34 +01:00
system.l2c.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 1689 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 1849 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 9122 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 52734 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.l2c.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id
2016-12-05 22:48:34 +01:00
system.l2c.tags.tag_accesses 38356372 # Number of tag accesses
system.l2c.tags.data_accesses 38356372 # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 822171 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 822171 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 873935 # number of WritebackClean hits
system.l2c.WritebackClean_hits::total 873935 # number of WritebackClean hits
2016-10-14 00:21:40 +02:00
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2016-12-05 22:48:34 +01:00
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2016-08-12 15:12:59 +02:00
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2016-12-05 22:48:34 +01:00
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2014-12-02 12:08:05 +01:00
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2016-12-05 22:48:34 +01:00
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2016-08-12 15:12:59 +02:00
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2016-04-09 18:13:40 +02:00
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2016-08-12 15:12:59 +02:00
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2016-04-09 18:13:40 +02:00
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2016-08-12 15:12:59 +02:00
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2016-04-09 18:13:40 +02:00
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2016-08-12 15:12:59 +02:00
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2016-12-05 22:48:34 +01:00
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2016-08-12 15:12:59 +02:00
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2016-12-05 22:48:34 +01:00
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2016-10-14 00:21:40 +02:00
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2016-08-12 15:12:59 +02:00
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2016-12-05 22:48:34 +01:00
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2016-08-12 15:12:59 +02:00
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2016-12-05 22:48:34 +01:00
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2015-07-03 16:15:03 +02:00
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
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2016-12-05 22:48:34 +01:00
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system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013295 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.274178 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.022799 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254149 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015010 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.305763 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007346 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.108677 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.162692 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015010 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.305763 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007346 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.108677 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.162692 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 38750 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18750 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 32083.333333 # average UpgradeReq mshr miss latency
2016-08-12 15:12:59 +02:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 18500 # average SCUpgradeReq mshr miss latency
2016-12-05 22:48:34 +01:00
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93283.663814 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116991.422972 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 95637.198290 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 91029.359838 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 71548.632457 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106013.245033 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71794.968708 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77775.532822 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 115455.417035 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 79552.837512 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77775.532822 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 115455.417035 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 79552.837512 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210679.661746 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179520.642202 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209735.580264 # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87043.998342 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 11595.703704 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 74476.729839 # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests 852121 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 399760 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 540 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-05-31 12:07:18 +02:00
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-12-05 22:48:34 +01:00
system.membus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
2016-08-12 15:12:59 +02:00
system.membus.trans_dist::ReadReq 7195 # Transaction distribution
2016-12-05 22:48:34 +01:00
system.membus.trans_dist::ReadResp 297263 # Transaction distribution
system.membus.trans_dist::WriteReq 13067 # Transaction distribution
system.membus.trans_dist::WriteResp 13067 # Transaction distribution
system.membus.trans_dist::WritebackDirty 123600 # Transaction distribution
system.membus.trans_dist::CleanEvict 263134 # Transaction distribution
system.membus.trans_dist::UpgradeReq 6631 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 5160 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.membus.trans_dist::UpgradeResp 3 # Transaction distribution
2016-12-05 22:48:34 +01:00
system.membus.trans_dist::ReadExReq 121851 # Transaction distribution
system.membus.trans_dist::ReadExResp 121443 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 290113 # Transaction distribution
system.membus.trans_dist::BadAddressError 45 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
2016-12-05 22:48:34 +01:00
system.membus.trans_dist::InvalidateResp 134 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40524 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179612 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 90 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 1220226 # Packet count per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83445 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 83445 # Packet count per connected master and slave (bytes)
2016-12-05 22:48:34 +01:00
system.membus.pkt_count::total 1303671 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73922 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31560064 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 31633986 # Cumulative packet size per connected master and slave (bytes)
2015-09-15 15:14:09 +02:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes)
2016-12-05 22:48:34 +01:00
system.membus.pkt_size::total 34292226 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 12662 # Total snoops (count)
2016-10-14 00:21:40 +02:00
system.membus.snoopTraffic 28800 # Total snoop traffic (bytes)
2016-12-05 22:48:34 +01:00
system.membus.snoop_fanout::samples 485569 # Request fanout histogram
system.membus.snoop_fanout::mean 0.001425 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.037724 # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-12-05 22:48:34 +01:00
system.membus.snoop_fanout::0 484877 99.86% 99.86% # Request fanout histogram
system.membus.snoop_fanout::1 692 0.14% 100.00% # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2016-05-31 12:07:18 +02:00
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2016-12-05 22:48:34 +01:00
system.membus.snoop_fanout::total 485569 # Request fanout histogram
system.membus.reqLayer0.occupancy 36441999 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.membus.reqLayer1.occupancy 1353891077 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.membus.reqLayer2.occupancy 56500 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.membus.respLayer1.occupancy 2179677750 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.membus.respLayer2.occupancy 1104580 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 5103299 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 2546186 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 356313 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 1076 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 1008 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-12-05 22:48:34 +01:00
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
2016-08-12 15:12:59 +02:00
system.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution
2016-12-05 22:48:34 +01:00
system.toL2Bus.trans_dist::ReadResp 2260964 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 13067 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 13067 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 904251 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 1149139 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 825400 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 10906 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 6131 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 17037 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 299755 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 299755 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 1150512 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 1103306 # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError 45 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2678185 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3810494 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 771737 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 418186 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 7678602 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 114248448 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 127253332 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32913792 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13701358 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 288116930 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 382331 # Total snoops (count)
system.toL2Bus.snoopTraffic 6809920 # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples 2937042 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.126206 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.332589 # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-12-05 22:48:34 +01:00
system.toL2Bus.snoop_fanout::0 2566846 87.40% 87.40% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 369740 12.59% 99.98% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 436 0.01% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 20 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
2016-12-05 22:48:34 +01:00
system.toL2Bus.snoop_fanout::total 2937042 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 4539664918 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.toL2Bus.snoopLayer0.occupancy 302885 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.toL2Bus.respLayer0.occupancy 1341208229 # Layer occupancy (ticks)
2015-09-15 15:14:09 +02:00
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.toL2Bus.respLayer1.occupancy 1910262297 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.toL2Bus.respLayer2.occupancy 387640565 # Layer occupancy (ticks)
2014-12-23 15:31:20 +01:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.toL2Bus.respLayer3.occupancy 217884535 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
2014-12-02 12:08:05 +01:00
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
2016-12-05 22:48:34 +01:00
system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
2011-07-10 19:56:09 +02:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
2016-12-05 22:48:34 +01:00
system.cpu0.kern.inst.quiesce 6478 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 176731 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 62783 40.27% 40.27% # number of times we switched to this ipl
2016-10-14 00:21:40 +02:00
system.cpu0.kern.ipl_count::21 131 0.08% 40.36% # number of times we switched to this ipl
2016-12-05 22:48:34 +01:00
system.cpu0.kern.ipl_count::22 1927 1.24% 41.60% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30 182 0.12% 41.71% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31 90863 58.29% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 155886 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 61769 49.18% 49.18% # number of times we switched to this ipl from a different ipl
2016-10-14 00:21:40 +02:00
system.cpu0.kern.ipl_good::21 131 0.10% 49.29% # number of times we switched to this ipl from a different ipl
2016-12-05 22:48:34 +01:00
system.cpu0.kern.ipl_good::22 1927 1.53% 50.82% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30 182 0.14% 50.96% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 61587 49.04% 100.00% # number of times we switched to this ipl from a different ipl
2016-10-14 00:21:40 +02:00
system.cpu0.kern.ipl_good::total 125596 # number of times we switched to this ipl from a different ipl
2016-12-05 22:48:34 +01:00
system.cpu0.kern.ipl_ticks::0 1864292107000 97.65% 97.65% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 64306500 0.00% 97.65% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 577089500 0.03% 97.68% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30 88747000 0.00% 97.69% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 44160796000 2.31% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1909183046000 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.983849 # fraction of swpipl calls that actually changed the ipl
2011-07-10 19:56:09 +02:00
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
2016-12-05 22:48:34 +01:00
system.cpu0.kern.ipl_used::31 0.677801 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total 0.805691 # fraction of swpipl calls that actually changed the ipl
2011-07-10 19:56:09 +02:00
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
2016-12-05 22:48:34 +01:00
system.cpu0.kern.callpal::wripir 294 0.18% 0.18% # number of callpals executed
2016-10-14 00:21:40 +02:00
system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed
2016-12-05 22:48:34 +01:00
system.cpu0.kern.callpal::swpctx 3351 2.05% 2.23% # number of callpals executed
2016-10-14 00:21:40 +02:00
system.cpu0.kern.callpal::tbi 48 0.03% 2.26% # number of callpals executed
2016-12-05 22:48:34 +01:00
system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed
system.cpu0.kern.callpal::swpipl 149332 91.35% 93.61% # number of callpals executed
system.cpu0.kern.callpal::rdps 5685 3.48% 97.09% # number of callpals executed
2016-10-14 00:21:40 +02:00
system.cpu0.kern.callpal::wrkgp 1 0.00% 97.09% # number of callpals executed
system.cpu0.kern.callpal::wrusp 1 0.00% 97.09% # number of callpals executed
2016-12-05 22:48:34 +01:00
system.cpu0.kern.callpal::rdusp 8 0.00% 97.09% # number of callpals executed
2016-10-14 00:21:40 +02:00
system.cpu0.kern.callpal::whami 2 0.00% 97.10% # number of callpals executed
2016-12-05 22:48:34 +01:00
system.cpu0.kern.callpal::rti 4313 2.64% 99.73% # number of callpals executed
2016-10-14 00:21:40 +02:00
system.cpu0.kern.callpal::callsys 303 0.19% 99.92% # number of callpals executed
2016-08-12 15:12:59 +02:00
system.cpu0.kern.callpal::imb 132 0.08% 100.00% # number of callpals executed
2016-12-05 22:48:34 +01:00
system.cpu0.kern.callpal::total 163481 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 6669 # number of protection mode switches
2016-10-14 00:21:40 +02:00
system.cpu0.kern.mode_switch::user 1070 # number of protection mode switches
2011-07-10 19:56:09 +02:00
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
2016-10-14 00:21:40 +02:00
system.cpu0.kern.mode_good::kernel 1070
system.cpu0.kern.mode_good::user 1070
2011-07-10 19:56:09 +02:00
system.cpu0.kern.mode_good::idle 0
2016-12-05 22:48:34 +01:00
system.cpu0.kern.mode_switch_good::kernel 0.160444 # fraction of useful protection mode switches
2011-07-10 19:56:09 +02:00
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
2012-05-09 20:52:14 +02:00
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
2016-12-05 22:48:34 +01:00
system.cpu0.kern.mode_switch_good::total 0.276522 # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 1907148784500 99.91% 99.91% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 1683022000 0.09% 100.00% # number of ticks spent at the given mode
2011-07-10 19:56:09 +02:00
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
2016-12-05 22:48:34 +01:00
system.cpu0.kern.swap_context 3352 # number of times the context was actually changed
2008-10-21 01:00:07 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
2016-12-05 22:48:34 +01:00
system.cpu1.kern.inst.quiesce 2546 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 62928 # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0 19570 37.60% 37.60% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22 1925 3.70% 41.30% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30 294 0.56% 41.86% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31 30260 58.14% 100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total 52049 # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0 19207 47.61% 47.61% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22 1925 4.77% 52.39% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30 294 0.73% 53.11% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31 18913 46.89% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total 40339 # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0 1874881279000 98.19% 98.19% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22 565111500 0.03% 98.22% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30 141720000 0.01% 98.22% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31 33895004500 1.78% 100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total 1909483115000 # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0 0.981451 # fraction of swpipl calls that actually changed the ipl
2009-04-22 19:25:17 +02:00
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
2016-12-05 22:48:34 +01:00
system.cpu1.kern.ipl_used::31 0.625017 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total 0.775020 # fraction of swpipl calls that actually changed the ipl
2011-07-10 19:56:09 +02:00
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
2016-12-05 22:48:34 +01:00
system.cpu1.kern.callpal::wripir 182 0.33% 0.34% # number of callpals executed
2016-08-12 15:12:59 +02:00
system.cpu1.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed
system.cpu1.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed
2016-12-05 22:48:34 +01:00
system.cpu1.kern.callpal::swpctx 1230 2.25% 2.59% # number of callpals executed
2016-10-14 00:21:40 +02:00
system.cpu1.kern.callpal::tbi 5 0.01% 2.60% # number of callpals executed
system.cpu1.kern.callpal::wrent 7 0.01% 2.61% # number of callpals executed
2016-12-05 22:48:34 +01:00
system.cpu1.kern.callpal::swpipl 46579 85.30% 87.91% # number of callpals executed
system.cpu1.kern.callpal::rdps 3079 5.64% 93.55% # number of callpals executed
system.cpu1.kern.callpal::wrkgp 1 0.00% 93.55% # number of callpals executed
system.cpu1.kern.callpal::wrusp 6 0.01% 93.56% # number of callpals executed
system.cpu1.kern.callpal::rdusp 1 0.00% 93.56% # number of callpals executed
2016-10-14 00:21:40 +02:00
system.cpu1.kern.callpal::whami 3 0.01% 93.57% # number of callpals executed
2016-12-05 22:48:34 +01:00
system.cpu1.kern.callpal::rti 3250 5.95% 99.52% # number of callpals executed
2016-10-14 00:21:40 +02:00
system.cpu1.kern.callpal::callsys 212 0.39% 99.91% # number of callpals executed
2016-08-12 15:12:59 +02:00
system.cpu1.kern.callpal::imb 48 0.09% 100.00% # number of callpals executed
2011-07-10 19:56:09 +02:00
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
2016-12-05 22:48:34 +01:00
system.cpu1.kern.callpal::total 54607 # number of callpals executed
system.cpu1.kern.mode_switch::kernel 1700 # number of protection mode switches
system.cpu1.kern.mode_switch::user 670 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 2433 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 890
system.cpu1.kern.mode_good::user 670
system.cpu1.kern.mode_good::idle 220
system.cpu1.kern.mode_switch_good::kernel 0.523529 # fraction of useful protection mode switches
2009-04-22 19:25:17 +02:00
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
2016-12-05 22:48:34 +01:00
system.cpu1.kern.mode_switch_good::idle 0.090423 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total 0.370602 # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 5328500500 0.28% 0.28% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 1057436000 0.06% 0.33% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 1903097170500 99.67% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context 1231 # number of times the context was actually changed
2008-10-21 01:00:07 +02:00
---------- End Simulation Statistics ----------
