2013-01-07 19:05:52 +01:00
---------- Begin Simulation Statistics ----------
2016-03-16 21:03:49 +01:00
sim_seconds 2.823493 # Number of seconds simulated
sim_ticks 2823493079000 # Number of ticks simulated
final_tick 2823493079000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2013-01-07 19:05:52 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-03-16 21:03:49 +01:00
host_inst_rate 90172 # Simulator instruction rate (inst/s)
host_op_rate 109444 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2177949659 # Simulator tick rate (ticks/s)
host_mem_usage 568424 # Number of bytes of host memory used
host_seconds 1296.40 # Real time elapsed on the host
sim_insts 116899487 # Number of instructions simulated
sim_ops 141883778 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2015-12-05 01:11:25 +01:00
system.physmem.bytes_read::cpu0.dtb.walker 3648 # Number of bytes read from this memory
2014-06-22 23:33:09 +02:00
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
2016-03-16 21:03:49 +01:00
system.physmem.bytes_read::cpu0.inst 661248 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 5289056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 5312 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 712448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 4516488 # Number of bytes read from this memory
2014-11-12 15:05:25 +01:00
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
2016-03-16 21:03:49 +01:00
system.physmem.bytes_read::total 11189224 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 661248 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 712448 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1373696 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8440896 # Number of bytes written to this memory
2014-10-30 05:18:29 +01:00
system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory
2016-03-16 21:03:49 +01:00
system.physmem.bytes_written::total 8458420 # Number of bytes written to this memory
2015-12-05 01:11:25 +01:00
system.physmem.num_reads::cpu0.dtb.walker 57 # Number of read requests responded to by this memory
2014-06-22 23:33:09 +02:00
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
2016-03-16 21:03:49 +01:00
system.physmem.num_reads::cpu0.inst 10332 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 83160 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 83 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 11132 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 70572 # Number of read requests responded to by this memory
2014-11-12 15:05:25 +01:00
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
2016-03-16 21:03:49 +01:00
system.physmem.num_reads::total 175352 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 131889 # Number of write requests responded to by this memory
2014-10-30 05:18:29 +01:00
system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
2016-03-16 21:03:49 +01:00
system.physmem.num_writes::total 136270 # Number of write requests responded to by this memory
2015-12-05 01:11:25 +01:00
system.physmem.bw_read::cpu0.dtb.walker 1292 # Total read bandwidth from this memory (bytes/s)
2014-10-30 05:18:29 +01:00
system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
2016-03-16 21:03:49 +01:00
system.physmem.bw_read::cpu0.inst 234195 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1873231 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 1881 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 252329 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1599610 # Total read bandwidth from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
2016-03-16 21:03:49 +01:00
system.physmem.bw_read::total 3962901 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 234195 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 252329 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 486524 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2989522 # Write bandwidth from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_write::cpu0.data 6204 # Write bandwidth from this memory (bytes/s)
2014-10-30 05:18:29 +01:00
system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
2016-03-16 21:03:49 +01:00
system.physmem.bw_write::total 2995729 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2989522 # Total bandwidth to/from this memory (bytes/s)
2015-12-05 01:11:25 +01:00
system.physmem.bw_total::cpu0.dtb.walker 1292 # Total bandwidth to/from this memory (bytes/s)
2014-10-30 05:18:29 +01:00
system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
2016-03-16 21:03:49 +01:00
system.physmem.bw_total::cpu0.inst 234195 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1879435 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 1881 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 252329 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 1599613 # Total bandwidth to/from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
2016-03-16 21:03:49 +01:00
system.physmem.bw_total::total 6958630 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 175353 # Number of read requests accepted
system.physmem.writeReqs 136270 # Number of write requests accepted
system.physmem.readBursts 175353 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 136270 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 11214528 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue
system.physmem.bytesWritten 8470656 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 11189288 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 8458420 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue
2015-09-25 13:27:03 +02:00
system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-03-16 21:03:49 +01:00
system.physmem.perBankRdBursts::0 11394 # Per bank write bursts
system.physmem.perBankRdBursts::1 10988 # Per bank write bursts
system.physmem.perBankRdBursts::2 11451 # Per bank write bursts
system.physmem.perBankRdBursts::3 11269 # Per bank write bursts
2016-02-10 10:08:27 +01:00
system.physmem.perBankRdBursts::4 11015 # Per bank write bursts
2016-03-16 21:03:49 +01:00
system.physmem.perBankRdBursts::5 10539 # Per bank write bursts
system.physmem.perBankRdBursts::6 11408 # Per bank write bursts
system.physmem.perBankRdBursts::7 11336 # Per bank write bursts
system.physmem.perBankRdBursts::8 11237 # Per bank write bursts
system.physmem.perBankRdBursts::9 11286 # Per bank write bursts
system.physmem.perBankRdBursts::10 10494 # Per bank write bursts
system.physmem.perBankRdBursts::11 10073 # Per bank write bursts
system.physmem.perBankRdBursts::12 10670 # Per bank write bursts
system.physmem.perBankRdBursts::13 11521 # Per bank write bursts
system.physmem.perBankRdBursts::14 10545 # Per bank write bursts
system.physmem.perBankRdBursts::15 10001 # Per bank write bursts
system.physmem.perBankWrBursts::0 8622 # Per bank write bursts
system.physmem.perBankWrBursts::1 8285 # Per bank write bursts
system.physmem.perBankWrBursts::2 8892 # Per bank write bursts
system.physmem.perBankWrBursts::3 8784 # Per bank write bursts
system.physmem.perBankWrBursts::4 7852 # Per bank write bursts
system.physmem.perBankWrBursts::5 7876 # Per bank write bursts
system.physmem.perBankWrBursts::6 8452 # Per bank write bursts
system.physmem.perBankWrBursts::7 8530 # Per bank write bursts
system.physmem.perBankWrBursts::8 8484 # Per bank write bursts
system.physmem.perBankWrBursts::9 8682 # Per bank write bursts
system.physmem.perBankWrBursts::10 7871 # Per bank write bursts
system.physmem.perBankWrBursts::11 7713 # Per bank write bursts
system.physmem.perBankWrBursts::12 8237 # Per bank write bursts
system.physmem.perBankWrBursts::13 8870 # Per bank write bursts
system.physmem.perBankWrBursts::14 7879 # Per bank write bursts
2015-12-05 01:11:25 +01:00
system.physmem.perBankWrBursts::15 7325 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2016-03-16 21:03:49 +01:00
system.physmem.numWrRetry 11 # Number of times write queue was full causing retry
system.physmem.totGap 2823492901000 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
2015-05-05 09:22:39 +02:00
system.physmem.readPktSize::2 542 # Read request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.readPktSize::3 14 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-03-16 21:03:49 +01:00
system.physmem.readPktSize::6 174797 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2016-03-16 21:03:49 +01:00
system.physmem.writePktSize::6 131889 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 107608 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 59040 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 6836 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1721 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
2014-10-30 05:18:29 +01:00
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
2013-11-27 00:05:25 +01:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
2013-01-07 19:05:52 +01:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2016-03-16 21:03:49 +01:00
system.physmem.wrQLenPdf::0 113 # What write queue length does an incoming req see
2016-02-10 10:08:27 +01:00
system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see
2016-03-16 21:03:49 +01:00
system.physmem.wrQLenPdf::2 95 # What write queue length does an incoming req see
2015-12-05 01:11:25 +01:00
system.physmem.wrQLenPdf::3 96 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 95 # What write queue length does an incoming req see
2016-02-10 10:08:27 +01:00
system.physmem.wrQLenPdf::5 93 # What write queue length does an incoming req see
2016-03-16 21:03:49 +01:00
system.physmem.wrQLenPdf::6 92 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 93 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 93 # What write queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.wrQLenPdf::9 89 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 88 # What write queue length does an incoming req see
2016-03-16 21:03:49 +01:00
system.physmem.wrQLenPdf::11 88 # What write queue length does an incoming req see
2016-02-10 10:08:27 +01:00
system.physmem.wrQLenPdf::12 87 # What write queue length does an incoming req see
2016-03-16 21:03:49 +01:00
system.physmem.wrQLenPdf::13 88 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 85 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1941 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2907 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5808 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 7418 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6882 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6758 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6986 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 7655 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 7371 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7983 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 8766 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7926 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 8469 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 10022 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7945 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7725 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 7533 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1171 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 348 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 257 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 269 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 261 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 247 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 194 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 180 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 148 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 117 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 115 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 131 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 77 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 97 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 82 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 67 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 89 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 62 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 88 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 89 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 58 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 75 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 62 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 48 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 50 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 23 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 65667 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 299.771879 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 177.410204 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 322.899744 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 24666 37.56% 37.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 16246 24.74% 62.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6758 10.29% 72.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3770 5.74% 78.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2852 4.34% 82.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1648 2.51% 85.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1102 1.68% 86.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1095 1.67% 88.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7530 11.47% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 65667 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6540 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 26.788379 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 487.878156 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 6538 99.97% 99.97% # Reads before turning the bus around for writes
2015-11-06 09:26:50 +01:00
system.physmem.rdPerTurnAround::6144-8191 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::36864-38911 1 0.02% 100.00% # Reads before turning the bus around for writes
2016-03-16 21:03:49 +01:00
system.physmem.rdPerTurnAround::total 6540 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6540 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.237615 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.280340 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 13.729615 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 19 0.29% 0.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 5 0.08% 0.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11 5 0.08% 0.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15 11 0.17% 0.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 5728 87.58% 88.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 148 2.26% 90.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 45 0.69% 91.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 64 0.98% 92.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 38 0.58% 92.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 19 0.29% 93.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 47 0.72% 93.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 11 0.17% 93.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 150 2.29% 96.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 8 0.12% 96.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 5 0.08% 96.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 7 0.11% 96.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 70 1.07% 97.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 6 0.09% 97.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 6 0.09% 97.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 27 0.41% 98.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 96 1.47% 99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 1 0.02% 99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 1 0.02% 99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 1 0.02% 99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 2 0.03% 99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 2 0.03% 99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 4 0.06% 99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 2 0.03% 99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 6 0.09% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 3 0.05% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 1 0.02% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6540 # Writes before turning the bus around for reads
system.physmem.totQLat 2749640001 # Total ticks spent queuing
system.physmem.totMemAccLat 6035146251 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 876135000 # Total ticks spent in databus transfers
system.physmem.avgQLat 15691.87 # Average queueing delay per DRAM burst
2015-09-25 13:27:03 +02:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-03-16 21:03:49 +01:00
system.physmem.avgMemAccLat 34441.87 # Average memory access latency per DRAM burst
2015-09-25 13:27:03 +02:00
system.physmem.avgRdBW 3.97 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.96 # Average system read bandwidth in MiByte/s
2016-03-16 21:03:49 +01:00
system.physmem.avgWrBWSys 3.00 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-07-03 16:15:03 +02:00
system.physmem.busUtil 0.05 # Data bus utilization in percentage
2014-10-30 05:18:29 +01:00
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
2015-07-03 16:15:03 +02:00
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
2015-11-06 09:26:50 +01:00
system.physmem.avgRdQLen 1.46 # Average read queue length when enqueuing
2016-03-16 21:03:49 +01:00
system.physmem.avgWrQLen 13.00 # Average write queue length when enqueuing
system.physmem.readRowHits 144282 # Number of row buffer hits during reads
system.physmem.writeRowHits 97631 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 73.75 # Row buffer hit rate for writes
system.physmem.avgGap 9060604.96 # Average gap between requests
system.physmem.pageHitRate 78.64 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 255898440 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 139627125 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 697320000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 436058640 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 184416570000 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 80131577265 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1623802634250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1889879685720 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.341932 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2701224800750 # Time in different power states
system.physmem_0.memoryStateTime::REF 94282500000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-03-16 21:03:49 +01:00
system.physmem_0.memoryStateTime::ACT 27981865500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-03-16 21:03:49 +01:00
system.physmem_1.actEnergy 240544080 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 131249250 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 669442800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 421595280 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 184416570000 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 79215076260 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1624606582500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1889701060170 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.278668 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2702572917000 # Time in different power states
system.physmem_1.memoryStateTime::REF 94282500000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-03-16 21:03:49 +01:00
system.physmem_1.memoryStateTime::ACT 26637651500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-07-03 16:15:03 +02:00
system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory
2015-09-25 13:27:03 +02:00
system.realview.nvmem.bw_read::cpu0.inst 249 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 249 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 249 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 249 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 249 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 249 # Total bandwidth to/from this memory (bytes/s)
2013-01-07 19:05:52 +01:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
2014-10-30 05:18:29 +01:00
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
2016-03-16 21:03:49 +01:00
system.cpu0.branchPred.lookups 26562225 # Number of BP lookups
system.cpu0.branchPred.condPredicted 13713319 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 500857 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 15697125 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 12422609 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-03-16 21:03:49 +01:00
system.cpu0.branchPred.BTBHitPct 79.139390 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 6635585 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 27692 # Number of incorrect RAS predictions.
2014-11-12 15:05:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-12-23 15:31:20 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-03-16 21:03:49 +01:00
system.cpu0.dtb.walker.walks 56581 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 56581 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17171 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 13789 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 25621 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 30960 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean 892.441860 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 5515.724394 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-16383 30478 98.44% 98.44% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-32767 319 1.03% 99.47% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-49151 90 0.29% 99.76% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::49152-65535 32 0.10% 99.87% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-81919 19 0.06% 99.93% # Table walker wait (enqueue to first request) latency
2016-02-10 10:08:27 +01:00
system.cpu0.dtb.walker.walkWaitTime::81920-98303 5 0.02% 99.95% # Table walker wait (enqueue to first request) latency
2016-03-16 21:03:49 +01:00
system.cpu0.dtb.walker.walkWaitTime::98304-114687 6 0.02% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::114688-131071 6 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-147455 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
2015-11-06 09:26:50 +01:00
system.cpu0.dtb.walker.walkWaitTime::147456-163839 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency
2016-03-16 21:03:49 +01:00
system.cpu0.dtb.walker.walkWaitTime::total 30960 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 12756 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 13625.744748 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 11059.152446 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 9336.432793 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383 9266 72.64% 72.64% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767 3226 25.29% 97.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151 240 1.88% 99.81% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.03% 99.84% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-81919 2 0.02% 99.86% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.01% 99.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-147455 13 0.10% 99.97% # Table walker service (enqueue to completion) latency
2016-02-10 10:08:27 +01:00
system.cpu0.dtb.walker.walkCompletionTime::147456-163839 3 0.02% 99.99% # Table walker service (enqueue to completion) latency
2016-03-16 21:03:49 +01:00
system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 12756 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 91893354244 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.629728 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.506061 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1 91810040244 99.91% 99.91% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3 56305000 0.06% 99.97% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5 12880500 0.01% 99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7 5151500 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9 2494500 0.00% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11 1674000 0.00% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13 953500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15 2585000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17 396500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::18-19 403500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::20-21 80000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::22-23 39000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::24-25 135500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::26-27 32000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::28-29 29000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::30-31 154500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 91893354244 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 3474 69.45% 69.45% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M 1528 30.55% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 5002 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 56581 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-03-16 21:03:49 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 56581 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5002 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-03-16 21:03:49 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5002 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 61583 # Table walker requests started/completed, data/inst
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
2016-03-16 21:03:49 +01:00
system.cpu0.dtb.read_hits 13951355 # DTB read hits
system.cpu0.dtb.read_misses 47293 # DTB read misses
system.cpu0.dtb.write_hits 10502243 # DTB write hits
system.cpu0.dtb.write_misses 9288 # DTB write misses
system.cpu0.dtb.flush_tlb 177 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 479 # Number of times TLB was flushed by MVA
2014-10-30 05:18:29 +01:00
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-03-16 21:03:49 +01:00
system.cpu0.dtb.flush_entries 3270 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 756 # Number of TLB faults due to alignment restrictions
2016-02-10 10:08:27 +01:00
system.cpu0.dtb.prefetch_faults 1257 # Number of TLB faults due to prefetch
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-03-16 21:03:49 +01:00
system.cpu0.dtb.perms_faults 577 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 13998648 # DTB read accesses
system.cpu0.dtb.write_accesses 10511531 # DTB write accesses
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
2016-03-16 21:03:49 +01:00
system.cpu0.dtb.hits 24453598 # DTB hits
system.cpu0.dtb.misses 56581 # DTB misses
system.cpu0.dtb.accesses 24510179 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-03-16 21:03:49 +01:00
system.cpu0.itb.walker.walks 8148 # Table walker walks requested
system.cpu0.itb.walker.walksShort 8148 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2287 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5071 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore 790 # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples 7358 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean 1843.571623 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 7891.595546 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-16383 7065 96.02% 96.02% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-32767 220 2.99% 99.01% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-49151 36 0.49% 99.50% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::49152-65535 18 0.24% 99.74% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-81919 7 0.10% 99.84% # Table walker wait (enqueue to first request) latency
2016-02-10 10:08:27 +01:00
system.cpu0.itb.walker.walkWaitTime::81920-98303 3 0.04% 99.88% # Table walker wait (enqueue to first request) latency
2016-03-16 21:03:49 +01:00
system.cpu0.itb.walker.walkWaitTime::98304-114687 4 0.05% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::114688-131071 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-147455 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::147456-163839 2 0.03% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 7358 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 3026 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 13026.107072 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 10729.463375 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 8131.043208 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-16383 2342 77.40% 77.40% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-32767 631 20.85% 98.25% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-49151 50 1.65% 99.90% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.03% 99.93% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-81919 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 3026 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 23173609508 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 0.733481 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev 0.443211 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 6183538408 26.68% 26.68% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 16984817600 73.29% 99.98% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2 4062000 0.02% 99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3 741500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4 212000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::5 115000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::6 49000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::7 74000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 23173609508 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 1678 75.04% 75.04% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M 558 24.96% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 2236 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-03-16 21:03:49 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 8148 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 8148 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-03-16 21:03:49 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2236 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2236 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 10384 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 20133708 # ITB inst hits
system.cpu0.itb.inst_misses 8148 # ITB inst misses
2013-01-07 19:05:52 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
2016-03-16 21:03:49 +01:00
system.cpu0.itb.flush_tlb 177 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 479 # Number of times TLB was flushed by MVA
2014-10-30 05:18:29 +01:00
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-03-16 21:03:49 +01:00
system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB
2013-01-07 19:05:52 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-03-16 21:03:49 +01:00
system.cpu0.itb.perms_faults 1247 # Number of TLB faults due to permissions restrictions
2013-01-07 19:05:52 +01:00
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
2016-03-16 21:03:49 +01:00
system.cpu0.itb.inst_accesses 20141856 # ITB inst accesses
system.cpu0.itb.hits 20133708 # DTB hits
system.cpu0.itb.misses 8148 # DTB misses
system.cpu0.itb.accesses 20141856 # DTB accesses
system.cpu0.numCycles 111776852 # number of cpu cycles simulated
2013-01-07 19:05:52 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-03-16 21:03:49 +01:00
system.cpu0.fetch.icacheStallCycles 39403190 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 103921497 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 26562225 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 19058194 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 67156695 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 3114917 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 123726 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 4268 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles 480 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles 186283 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 122357 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 649 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 20132007 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 351323 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 4252 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 108555069 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 1.151171 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.270996 # Number of instructions fetched each cycle (Total)
2013-01-07 19:05:52 +01:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-03-16 21:03:49 +01:00
system.cpu0.fetch.rateDist::0 79990801 73.69% 73.69% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 3808874 3.51% 77.20% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 2395058 2.21% 79.40% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 7998029 7.37% 86.77% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 1538152 1.42% 88.19% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 1084902 1.00% 89.19% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 6043071 5.57% 94.75% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 1032645 0.95% 95.70% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 4663537 4.30% 100.00% # Number of instructions fetched each cycle (Total)
2013-01-07 19:05:52 +01:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2016-03-16 21:03:49 +01:00
system.cpu0.fetch.rateDist::total 108555069 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.237636 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.929723 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 26882807 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 63335776 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 15412280 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 1509994 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 1413858 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 1870073 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 145529 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 86268020 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 470270 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 1413858 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 27733992 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 6692590 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 45841615 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 16067408 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 10805241 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 82544618 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 2042 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 1112195 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 256310 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 8681649 # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands 84728075 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 381395863 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 92554269 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 5536 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 72228631 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 12499436 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 1563164 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 1465809 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 8810200 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 14722968 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 11667187 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 2112375 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 2825425 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 79486771 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1117550 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 76500149 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 87453 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 10367122 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 23085587 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 102592 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 108555069 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.704713 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.405532 # Number of insts issued each cycle
2013-01-07 19:05:52 +01:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-03-16 21:03:49 +01:00
system.cpu0.iq.issued_per_cycle::0 77869372 71.73% 71.73% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 10452853 9.63% 81.36% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 7709491 7.10% 88.46% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 6441479 5.93% 94.40% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 2337672 2.15% 96.55% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 1520744 1.40% 97.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 1474811 1.36% 99.31% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 488573 0.45% 99.76% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 260074 0.24% 100.00% # Number of insts issued each cycle
2013-01-07 19:05:52 +01:00
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2016-03-16 21:03:49 +01:00
system.cpu0.iq.issued_per_cycle::total 108555069 # Number of insts issued each cycle
2013-01-07 19:05:52 +01:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-03-16 21:03:49 +01:00
system.cpu0.iq.fu_full::IntAlu 112277 9.78% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 1 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 527304 45.92% 55.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 508852 44.31% 100.00% # attempts to use FU when none available
2013-01-07 19:05:52 +01:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2016-03-16 21:03:49 +01:00
system.cpu0.iq.FU_type_0::No_OpClass 223 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 50954579 66.61% 66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 56909 0.07% 66.68% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.68% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.68% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.68% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.68% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 66.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 4066 0.01% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 14340871 18.75% 85.43% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 11143495 14.57% 100.00% # Type of FU issued
2013-01-07 19:05:52 +01:00
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-03-16 21:03:49 +01:00
system.cpu0.iq.FU_type_0::total 76500149 # Type of FU issued
system.cpu0.iq.rate 0.684401 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 1148434 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.015012 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 262779006 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 91017673 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 74252791 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 12248 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 6548 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 5441 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 77641803 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 6557 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 356027 # Number of loads that had data forwarded from stores
2013-01-07 19:05:52 +01:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-03-16 21:03:49 +01:00
system.cpu0.iew.lsq.thread0.squashedLoads 1992322 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 2344 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 53958 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 1074198 # Number of stores squashed
2013-01-07 19:05:52 +01:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-03-16 21:03:49 +01:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 201819 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 121524 # Number of times an access to memory failed due to the cache being blocked
2013-01-07 19:05:52 +01:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-03-16 21:03:49 +01:00
system.cpu0.iew.iewSquashCycles 1413858 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 5274994 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 1203442 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 80734208 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 135083 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 14722968 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 11667187 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 571297 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 46146 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 1145124 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 53958 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 220662 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 202640 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 423302 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 75944815 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 14120955 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 498889 # Number of squashed instructions skipped in execute
2013-01-07 19:05:52 +01:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
2016-03-16 21:03:49 +01:00
system.cpu0.iew.exec_nop 129887 # number of nop insts executed
system.cpu0.iew.exec_refs 25162401 # number of memory reference insts executed
system.cpu0.iew.exec_branches 14058004 # Number of branches executed
system.cpu0.iew.exec_stores 11041446 # Number of stores executed
system.cpu0.iew.exec_rate 0.679432 # Inst execution rate
system.cpu0.iew.wb_sent 75389517 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 74258232 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 38914565 # num instructions producing a value
system.cpu0.iew.wb_consumers 68266536 # num instructions consuming a value
system.cpu0.iew.wb_rate 0.664344 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.570039 # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts 10404302 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 1014958 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 357219 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 106153750 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.662378 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.559927 # Number of insts commited each cycle
2013-01-07 19:05:52 +01:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-03-16 21:03:49 +01:00
system.cpu0.commit.committed_per_cycle::0 78810789 74.24% 74.24% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 12397271 11.68% 85.92% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 6093008 5.74% 91.66% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 2657069 2.50% 94.16% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 1361434 1.28% 95.45% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 829942 0.78% 96.23% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 1724502 1.62% 97.85% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 420914 0.40% 98.25% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1858821 1.75% 100.00% # Number of insts commited each cycle
2013-01-07 19:05:52 +01:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-03-16 21:03:49 +01:00
system.cpu0.commit.committed_per_cycle::total 106153750 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 57962859 # Number of instructions committed
system.cpu0.commit.committedOps 70313918 # Number of ops (including micro ops) committed
2013-01-07 19:05:52 +01:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
2016-03-16 21:03:49 +01:00
system.cpu0.commit.refs 23323635 # Number of memory references committed
system.cpu0.commit.loads 12730646 # Number of loads committed
system.cpu0.commit.membars 416255 # Number of memory barriers committed
system.cpu0.commit.branches 13367689 # Number of branches committed
system.cpu0.commit.fp_insts 5418 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 61732949 # Number of committed integer instructions.
system.cpu0.commit.function_calls 2627340 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2016-03-16 21:03:49 +01:00
system.cpu0.commit.op_class_0::IntAlu 46930865 66.74% 66.74% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 55353 0.08% 66.82% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.82% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.82% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.82% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.82% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.82% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.82% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.82% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.82% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.82% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.82% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.82% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.82% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.82% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.82% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.82% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.82% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.82% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.82% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.82% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.82% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.82% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.82% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.82% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 4065 0.01% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 12730646 18.11% 84.93% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 10592989 15.07% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-03-16 21:03:49 +01:00
system.cpu0.commit.op_class_0::total 70313918 # Class of committed instruction
system.cpu0.commit.bw_lim_events 1858821 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 172659175 # The number of ROB reads
system.cpu0.rob.rob_writes 163836244 # The number of ROB writes
system.cpu0.timesIdled 382209 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 3221783 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 2095451919 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 57886136 # Number of Instructions Simulated
system.cpu0.committedOps 70237195 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.930978 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.930978 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.517872 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.517872 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 82912613 # number of integer regfile reads
system.cpu0.int_regfile_writes 47294039 # number of integer regfile writes
system.cpu0.fp_regfile_reads 16301 # number of floating regfile reads
system.cpu0.fp_regfile_writes 13368 # number of floating regfile writes
system.cpu0.cc_regfile_reads 268256269 # number of cc regfile reads
system.cpu0.cc_regfile_writes 27711258 # number of cc regfile writes
system.cpu0.misc_regfile_reads 150058010 # number of misc regfile reads
system.cpu0.misc_regfile_writes 778660 # number of misc regfile writes
system.cpu0.dcache.tags.replacements 855157 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.968827 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 42356538 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 855669 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 49.501078 # Average number of references to valid blocks.
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.tags.warmup_cycle 186702500 # Cycle when the warmup percentage was hit.
2016-03-16 21:03:49 +01:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 253.928302 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 258.040525 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.495954 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.503985 # Average percentage of cache occupancy
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.tags.occ_percent::total 0.999939 # Average percentage of cache occupancy
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-03-16 21:03:49 +01:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id
2016-02-10 10:08:27 +01:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-03-16 21:03:49 +01:00
system.cpu0.dcache.tags.tag_accesses 189260797 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 189260797 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 12293541 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 12887736 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 25181277 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 7941758 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 7960833 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 15902591 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 184137 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 180149 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 364286 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 230149 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 215838 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 445987 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236565 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 222735 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 459300 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 20235299 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 20848569 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 41083868 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 20419436 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 21028718 # number of overall hits
system.cpu0.dcache.overall_hits::total 41448154 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 437058 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 404724 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 841782 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1876987 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 1816907 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 3693894 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 117439 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 66820 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 184259 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13653 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14173 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 27826 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 35 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 37 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 72 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 2314045 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 2221631 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 4535676 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 2431484 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 2288451 # number of overall misses
system.cpu0.dcache.overall_misses::total 4719935 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7271569000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 7418066000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 14689635000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 137750387419 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 114891760719 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 252642148138 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 219233500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 196798000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 416031500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 952000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 1111500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 2063500 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 145021956419 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 122309826719 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 267331783138 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 145021956419 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 122309826719 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 267331783138 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 12730599 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 13292460 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 26023059 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 9818745 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 9777740 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 19596485 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 301576 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 246969 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 548545 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 243802 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 230011 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 473813 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236600 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 222772 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 459372 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 22549344 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 23070200 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 45619544 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 22850920 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 23317169 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 46168089 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.034331 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.030448 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.032348 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.191164 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.185821 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.188498 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.389418 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.270560 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.335905 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056000 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.061619 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058728 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000148 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000166 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000157 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.102621 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.096299 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.099424 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.106406 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.098144 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.102234 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16637.537810 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18328.703017 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17450.640427 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 73389.100414 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 63234.805479 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 68394.531120 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16057.533143 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13885.415932 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14951.178754 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 27200 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 30040.540541 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28659.722222 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 62670.326817 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 55054.069159 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 58939.788278 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 59643.393261 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 53446.556959 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 56638.869632 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 1671211 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 344415 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 52563 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 3008 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 31.794437 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 114.499668 # average number of cycles each access was blocked
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
2016-03-16 21:03:49 +01:00
system.cpu0.dcache.writebacks::writebacks 705007 # number of writebacks
system.cpu0.dcache.writebacks::total 705007 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 227939 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 186956 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 414895 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1725394 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1668942 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 3394336 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 8922 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 9806 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18728 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1953333 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 1855898 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 3809231 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1953333 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 1855898 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 3809231 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 209119 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 217768 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 426887 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 151593 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 147965 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 299558 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 74139 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 48848 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 122987 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4731 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4367 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9098 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 35 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 37 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 72 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 360712 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 365733 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 726445 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 434851 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 414581 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 849432 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 14754 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16375 # number of ReadReq MSHR uncacheable
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31129 # number of ReadReq MSHR uncacheable
2016-03-16 21:03:49 +01:00
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15221 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 12367 # number of WriteReq MSHR uncacheable
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27588 # number of WriteReq MSHR uncacheable
2016-03-16 21:03:49 +01:00
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 29975 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 28742 # number of overall MSHR uncacheable misses
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58717 # number of overall MSHR uncacheable misses
2016-03-16 21:03:49 +01:00
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3334023500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 3388900000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6722923500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11210011376 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 9843148455 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 21053159831 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1112972000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 753142000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1866114000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 95513500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58899500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 154413000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 917000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 1074500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1991500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 14544034876 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 13232048455 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 27776083331 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15657006876 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 13985190455 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 29642197331 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2963154000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3337800500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6300954500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2591336924 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2492877452 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5084214376 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5554490924 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5830677952 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11385168876 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016426 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016383 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016404 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015439 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015133 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015286 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.245839 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.197790 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224206 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.019405 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.018986 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019202 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000148 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000166 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000157 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015997 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015853 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.015924 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019030 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017780 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.018399 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15943.187850 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15561.974211 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15748.719216 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 73948.080558 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 66523.491738 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70280.746403 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15011.964014 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15418.072388 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15173.262215 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 20188.860706 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13487.405542 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16972.191690 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26200 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 29040.540541 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27659.722222 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40320.352181 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 36179.531120 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38235.631508 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 36005.452157 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 33733.312561 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34896.492398 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200837.332249 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 203835.145038 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202414.292139 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170247.482031 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 201574.953667 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184290.792229 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 185304.117565 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 202862.638369 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193899.022021 # average overall mshr uncacheable latency
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-03-16 21:03:49 +01:00
system.cpu0.icache.tags.replacements 1936583 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.471659 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 38842661 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1937095 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 20.052017 # Average number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.cpu0.icache.tags.warmup_cycle 11154875500 # Cycle when the warmup percentage was hit.
2016-03-16 21:03:49 +01:00
system.cpu0.icache.tags.occ_blocks::cpu0.inst 205.032421 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 306.439238 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.400454 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.598514 # Average percentage of cache occupancy
2015-12-05 01:11:25 +01:00
system.cpu0.icache.tags.occ_percent::total 0.998968 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-02-10 10:08:27 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id
2016-03-16 21:03:49 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::1 230 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 142 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
2014-11-12 15:05:25 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-03-16 21:03:49 +01:00
system.cpu0.icache.tags.tag_accesses 42866235 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 42866235 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 19122912 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 19719749 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 38842661 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 19122912 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 19719749 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 38842661 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 19122912 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 19719749 # number of overall hits
system.cpu0.icache.overall_hits::total 38842661 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 1008426 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 1077981 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 2086407 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 1008426 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 1077981 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 2086407 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 1008426 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 1077981 # number of overall misses
system.cpu0.icache.overall_misses::total 2086407 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14309941480 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 15427311982 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 29737253462 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 14309941480 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 15427311982 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 29737253462 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 14309941480 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 15427311982 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 29737253462 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 20131338 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 20797730 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 40929068 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 20131338 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 20797730 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 40929068 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 20131338 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 20797730 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 40929068 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050092 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.051832 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.050976 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050092 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.051832 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.050976 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050092 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.051832 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.050976 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14190.373394 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14311.302316 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14252.853572 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14190.373394 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14311.302316 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14252.853572 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14190.373394 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14311.302316 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14252.853572 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 20675 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-03-16 21:03:49 +01:00
system.cpu0.icache.blocked::no_mshrs 822 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
2016-03-16 21:03:49 +01:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.152068 # average number of cycles each access was blocked
2014-11-12 15:05:25 +01:00
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
2016-03-16 21:03:49 +01:00
system.cpu0.icache.writebacks::writebacks 1936583 # number of writebacks
system.cpu0.icache.writebacks::total 1936583 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 71987 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 77252 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 149239 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 71987 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst 77252 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 149239 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 71987 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst 77252 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 149239 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 936439 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 1000729 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 1937168 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 936439 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 1000729 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 1937168 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 936439 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 1000729 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 1937168 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 668 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 668 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 668 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 668 # number of overall MSHR uncacheable misses
2016-03-16 21:03:49 +01:00
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12547401986 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 13499992487 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 26047394473 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12547401986 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 13499992487 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 26047394473 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12547401986 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 13499992487 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 26047394473 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 86506500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 86506500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 86506500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 86506500 # number of overall MSHR uncacheable cycles
2016-03-16 21:03:49 +01:00
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.046516 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.048117 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047330 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.046516 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.048117 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.047330 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.046516 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.048117 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.047330 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13399.059614 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13490.158162 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13446.120560 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13399.059614 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13490.158162 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13446.120560 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13399.059614 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13490.158162 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13446.120560 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 129500.748503 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 129500.748503 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 129500.748503 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 129500.748503 # average overall mshr uncacheable latency
2014-11-12 15:05:25 +01:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-03-16 21:03:49 +01:00
system.cpu1.branchPred.lookups 27851239 # Number of BP lookups
system.cpu1.branchPred.condPredicted 14560281 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 547901 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 17369720 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 13131935 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-03-16 21:03:49 +01:00
system.cpu1.branchPred.BTBHitPct 75.602456 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 6845775 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 28937 # Number of incorrect RAS predictions.
2014-12-23 15:31:20 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-03-16 21:03:49 +01:00
system.cpu1.dtb.walker.walks 58134 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 58134 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19184 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 13709 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 25241 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 32893 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 754.218223 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 5187.950869 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-16383 32437 98.61% 98.61% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-32767 325 0.99% 99.60% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-49151 66 0.20% 99.80% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::49152-65535 27 0.08% 99.88% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-81919 14 0.04% 99.93% # Table walker wait (enqueue to first request) latency
2016-02-10 10:08:27 +01:00
system.cpu1.dtb.walker.walkWaitTime::81920-98303 5 0.02% 99.94% # Table walker wait (enqueue to first request) latency
2016-03-16 21:03:49 +01:00
system.cpu1.dtb.walker.walkWaitTime::98304-114687 6 0.02% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::114688-131071 7 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-147455 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency
2015-11-06 09:26:50 +01:00
system.cpu1.dtb.walker.walkWaitTime::147456-163839 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency
2016-03-16 21:03:49 +01:00
system.cpu1.dtb.walker.walkWaitTime::total 32893 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 13323 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 14712.226976 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 12353.172902 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 8523.936722 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767 13006 97.62% 97.62% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535 308 2.31% 99.93% # Table walker service (enqueue to completion) latency
2016-02-10 10:08:27 +01:00
system.cpu1.dtb.walker.walkCompletionTime::65536-98303 7 0.05% 99.98% # Table walker service (enqueue to completion) latency
2016-03-16 21:03:49 +01:00
system.cpu1.dtb.walker.walkCompletionTime::131072-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
2016-03-16 21:03:49 +01:00
system.cpu1.dtb.walker.walkCompletionTime::total 13323 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 91468552244 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.754474 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.453530 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1 91381383244 99.90% 99.90% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3 60460000 0.07% 99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5 14228500 0.02% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7 4319000 0.00% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9 2420500 0.00% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11 1621000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13 756000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15 2345500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17 509500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::18-19 194000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::20-21 44500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::22-23 92500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::24-25 69000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::26-27 14000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::28-29 16500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::30-31 78500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 91468552244 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 3728 68.30% 68.30% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M 1730 31.70% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 5458 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 58134 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-03-16 21:03:49 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 58134 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5458 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-03-16 21:03:49 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5458 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 63592 # Table walker requests started/completed, data/inst
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
2016-03-16 21:03:49 +01:00
system.cpu1.dtb.read_hits 14422090 # DTB read hits
system.cpu1.dtb.read_misses 50182 # DTB read misses
system.cpu1.dtb.write_hits 10473943 # DTB write hits
system.cpu1.dtb.write_misses 7952 # DTB write misses
system.cpu1.dtb.flush_tlb 187 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 438 # Number of times TLB was flushed by MVA
2014-10-30 05:18:29 +01:00
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-03-16 21:03:49 +01:00
system.cpu1.dtb.flush_entries 3617 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 774 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 1261 # Number of TLB faults due to prefetch
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-03-16 21:03:49 +01:00
system.cpu1.dtb.perms_faults 668 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 14472272 # DTB read accesses
system.cpu1.dtb.write_accesses 10481895 # DTB write accesses
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
2016-03-16 21:03:49 +01:00
system.cpu1.dtb.hits 24896033 # DTB hits
system.cpu1.dtb.misses 58134 # DTB misses
system.cpu1.dtb.accesses 24954167 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-03-16 21:03:49 +01:00
system.cpu1.itb.walker.walks 8670 # Table walker walks requested
system.cpu1.itb.walker.walksShort 8670 # Table walker walks initiated with short descriptors
2016-02-10 10:08:27 +01:00
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2733 # Level at which table walker walks with short descriptors terminate
2016-03-16 21:03:49 +01:00
system.cpu1.itb.walker.walksShortTerminationLevel::Level2 5073 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore 864 # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples 7806 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean 1475.083269 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 5979.271301 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-8191 7339 94.02% 94.02% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::8192-16383 201 2.57% 96.59% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::16384-24575 162 2.08% 98.67% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::24576-32767 41 0.53% 99.19% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-40959 20 0.26% 99.45% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::40960-49151 18 0.23% 99.68% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::49152-57343 11 0.14% 99.82% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::57344-65535 7 0.09% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-73727 6 0.08% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::81920-90111 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 7806 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 3293 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 13788.642575 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 11489.093660 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 8040.901956 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-8191 943 28.64% 28.64% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-16383 1544 46.89% 75.52% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-24575 636 19.31% 94.84% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-32767 109 3.31% 98.15% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-40959 26 0.79% 98.94% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-49151 30 0.91% 99.85% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-57343 2 0.06% 99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.03% 99.94% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::81920-90111 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 3293 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 39929935692 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean 0.810654 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev 0.392199 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 7566087000 18.95% 18.95% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1 32359225692 81.04% 99.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2 3801500 0.01% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3 739500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4 82000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 39929935692 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 1840 75.75% 75.75% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M 589 24.25% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 2429 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-03-16 21:03:49 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 8670 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 8670 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-03-16 21:03:49 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2429 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2429 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 11099 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 20800432 # ITB inst hits
system.cpu1.itb.inst_misses 8670 # ITB inst misses
2013-01-07 19:05:52 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
2016-03-16 21:03:49 +01:00
system.cpu1.itb.flush_tlb 187 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 438 # Number of times TLB was flushed by MVA
2014-10-30 05:18:29 +01:00
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-03-16 21:03:49 +01:00
system.cpu1.itb.flush_entries 2396 # Number of entries that have been flushed from TLB
2013-01-07 19:05:52 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-03-16 21:03:49 +01:00
system.cpu1.itb.perms_faults 1452 # Number of TLB faults due to permissions restrictions
2013-01-07 19:05:52 +01:00
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
2016-03-16 21:03:49 +01:00
system.cpu1.itb.inst_accesses 20809102 # ITB inst accesses
system.cpu1.itb.hits 20800432 # DTB hits
system.cpu1.itb.misses 8670 # DTB misses
system.cpu1.itb.accesses 20809102 # DTB accesses
system.cpu1.numCycles 114311171 # number of cpu cycles simulated
2013-01-07 19:05:52 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-03-16 21:03:49 +01:00
system.cpu1.fetch.icacheStallCycles 41255732 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 107366172 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 27851239 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 19977710 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 67431456 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 3269763 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 132240 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 6802 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles 490 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles 244886 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 129624 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 516 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 20797736 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 380485 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 4341 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 110836590 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.165245 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.275623 # Number of instructions fetched each cycle (Total)
2013-01-07 19:05:52 +01:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-03-16 21:03:49 +01:00
system.cpu1.fetch.rateDist::0 81231588 73.29% 73.29% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 3970288 3.58% 76.87% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 2467097 2.23% 79.10% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 8234974 7.43% 86.53% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 1686085 1.52% 88.05% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 1118021 1.01% 89.06% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 6327387 5.71% 94.77% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 1165631 1.05% 95.82% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 4635519 4.18% 100.00% # Number of instructions fetched each cycle (Total)
2013-01-07 19:05:52 +01:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2016-03-16 21:03:49 +01:00
system.cpu1.fetch.rateDist::total 110836590 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.243644 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.939245 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 28312223 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 63485769 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 15857940 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 1699967 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 1480365 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 1967991 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 156560 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 89109002 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 506529 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 1480365 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 29245196 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 7030025 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 46679858 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 16613031 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 9787785 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 85253260 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 3942 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 1676107 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 305456 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 7062303 # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands 88411129 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 392062369 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 94760881 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 6288 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 74434583 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 13976546 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 1569925 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 1472475 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 9793304 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 15295862 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 11556895 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 2150664 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 2742502 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 82043962 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 1094941 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 78552222 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 91402 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 11492320 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 25159173 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 115830 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 110836590 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.708721 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.399471 # Number of insts issued each cycle
2013-01-07 19:05:52 +01:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-03-16 21:03:49 +01:00
system.cpu1.iq.issued_per_cycle::0 79260307 71.51% 71.51% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 10548653 9.52% 81.03% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 8143333 7.35% 88.38% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 6690324 6.04% 94.41% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 2458107 2.22% 96.63% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 1498250 1.35% 97.98% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 1549439 1.40% 99.38% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 479797 0.43% 99.81% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 208380 0.19% 100.00% # Number of insts issued each cycle
2013-01-07 19:05:52 +01:00
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2016-03-16 21:03:49 +01:00
system.cpu1.iq.issued_per_cycle::total 110836590 # Number of insts issued each cycle
2013-01-07 19:05:52 +01:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-03-16 21:03:49 +01:00
system.cpu1.iq.fu_full::IntAlu 101010 9.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 6 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 525539 46.85% 55.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 495241 44.15% 100.00% # attempts to use FU when none available
2013-01-07 19:05:52 +01:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2016-03-16 21:03:49 +01:00
system.cpu1.iq.FU_type_0::No_OpClass 2114 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 52641439 67.01% 67.02% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 59500 0.08% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 1 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 4515 0.01% 67.10% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 67.10% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 14821785 18.87% 85.97% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 11022863 14.03% 100.00% # Type of FU issued
2013-01-07 19:05:52 +01:00
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-03-16 21:03:49 +01:00
system.cpu1.iq.FU_type_0::total 78552222 # Type of FU issued
system.cpu1.iq.rate 0.687179 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 1121796 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.014281 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 269139975 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 94675085 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 76216531 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 14257 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 7438 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 6100 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 79664197 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 7707 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 356033 # Number of loads that had data forwarded from stores
2013-01-07 19:05:52 +01:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-03-16 21:03:49 +01:00
system.cpu1.iew.lsq.thread0.squashedLoads 2227814 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 2318 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 52493 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 1114040 # Number of stores squashed
2013-01-07 19:05:52 +01:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-03-16 21:03:49 +01:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 209025 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 78912 # Number of times an access to memory failed due to the cache being blocked
2013-01-07 19:05:52 +01:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-03-16 21:03:49 +01:00
system.cpu1.iew.iewSquashCycles 1480365 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 5648229 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 1078467 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 83272482 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 147374 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 15295862 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 11556895 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 563425 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 44942 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 1020454 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 52493 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 252230 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 220958 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 473188 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 77949376 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 14581691 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 544828 # Number of squashed instructions skipped in execute
2013-01-07 19:05:52 +01:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
2016-03-16 21:03:49 +01:00
system.cpu1.iew.exec_nop 133579 # number of nop insts executed
system.cpu1.iew.exec_refs 25499167 # number of memory reference insts executed
system.cpu1.iew.exec_branches 14792050 # Number of branches executed
system.cpu1.iew.exec_stores 10917476 # Number of stores executed
system.cpu1.iew.exec_rate 0.681905 # Inst execution rate
system.cpu1.iew.wb_sent 77406308 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 76222631 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 39922690 # num instructions producing a value
system.cpu1.iew.wb_consumers 69416540 # num instructions consuming a value
system.cpu1.iew.wb_rate 0.666799 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.575118 # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts 11468538 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 979111 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 393347 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 108253443 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.662563 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.545359 # Number of insts commited each cycle
2013-01-07 19:05:52 +01:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-03-16 21:03:49 +01:00
system.cpu1.commit.committed_per_cycle::0 80221800 74.11% 74.11% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 12496129 11.54% 85.65% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 6526093 6.03% 91.68% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 2656879 2.45% 94.13% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 1402571 1.30% 95.43% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 920713 0.85% 96.28% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 1916865 1.77% 98.05% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 408370 0.38% 98.43% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 1704023 1.57% 100.00% # Number of insts commited each cycle
2013-01-07 19:05:52 +01:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-03-16 21:03:49 +01:00
system.cpu1.commit.committed_per_cycle::total 108253443 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 59091533 # Number of instructions committed
system.cpu1.commit.committedOps 71724765 # Number of ops (including micro ops) committed
2013-01-07 19:05:52 +01:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
2016-03-16 21:03:49 +01:00
system.cpu1.commit.refs 23510903 # Number of memory references committed
system.cpu1.commit.loads 13068048 # Number of loads committed
system.cpu1.commit.membars 397789 # Number of memory barriers committed
system.cpu1.commit.branches 14004784 # Number of branches committed
system.cpu1.commit.fp_insts 6010 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 62686547 # Number of committed integer instructions.
system.cpu1.commit.function_calls 2707347 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2016-03-16 21:03:49 +01:00
system.cpu1.commit.op_class_0::IntAlu 48151619 67.13% 67.13% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 57729 0.08% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 4514 0.01% 67.22% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.22% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.22% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.22% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 13068048 18.22% 85.44% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 10442855 14.56% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-03-16 21:03:49 +01:00
system.cpu1.commit.op_class_0::total 71724765 # Class of committed instruction
system.cpu1.commit.bw_lim_events 1704023 # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads 176984123 # The number of ROB reads
system.cpu1.rob.rob_writes 168968777 # The number of ROB writes
system.cpu1.timesIdled 412637 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 3474581 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 3325416664 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 59013351 # Number of Instructions Simulated
system.cpu1.committedOps 71646583 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 1.937039 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.937039 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.516252 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.516252 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 84580836 # number of integer regfile reads
system.cpu1.int_regfile_writes 48527680 # number of integer regfile writes
system.cpu1.fp_regfile_reads 17118 # number of floating regfile reads
system.cpu1.fp_regfile_writes 13376 # number of floating regfile writes
system.cpu1.cc_regfile_reads 275597104 # number of cc regfile reads
system.cpu1.cc_regfile_writes 29295940 # number of cc regfile writes
system.cpu1.misc_regfile_reads 152598843 # number of misc regfile reads
system.cpu1.misc_regfile_writes 741284 # number of misc regfile writes
2015-11-06 09:26:50 +01:00
system.iobus.trans_dist::ReadReq 30172 # Transaction distribution
system.iobus.trans_dist::ReadResp 30172 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72894 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72894 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 178372 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321016 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321016 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480141 # Cumulative packet size per connected master and slave (bytes)
2016-03-16 21:03:49 +01:00
system.iobus.reqLayer0.occupancy 49503000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-03-16 21:03:49 +01:00
system.iobus.reqLayer2.occupancy 334000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2016-03-16 21:03:49 +01:00
system.iobus.reqLayer7.occupancy 84000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2016-03-16 21:03:49 +01:00
system.iobus.reqLayer8.occupancy 597500 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
2016-03-16 21:03:49 +01:00
system.iobus.reqLayer10.occupancy 18500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer16.occupancy 48000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer18.occupancy 8500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2016-03-16 21:03:49 +01:00
system.iobus.reqLayer23.occupancy 6438500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2016-03-16 21:03:49 +01:00
system.iobus.reqLayer24.occupancy 38189000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2016-03-16 21:03:49 +01:00
system.iobus.reqLayer25.occupancy 187123398 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iocache.tags.replacements 36413 # number of replacements
2016-03-16 21:03:49 +01:00
system.iocache.tags.tagsinuse 1.069613 # Cycle average of tags in use
2015-09-25 13:27:03 +02:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.iocache.tags.sampled_refs 36429 # Sample count of references to valid blocks.
2015-09-25 13:27:03 +02:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2016-03-16 21:03:49 +01:00
system.iocache.tags.warmup_cycle 236541086000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 1.069613 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.066851 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.066851 # Average percentage of cache occupancy
2014-10-30 05:18:29 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2015-11-06 09:26:50 +01:00
system.iocache.tags.tag_accesses 328023 # Number of tag accesses
system.iocache.tags.data_accesses 328023 # Number of data accesses
system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses
system.iocache.ReadReq_misses::total 223 # number of ReadReq misses
2015-09-25 13:27:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2015-11-06 09:26:50 +01:00
system.iocache.demand_misses::realview.ide 223 # number of demand (read+write) misses
system.iocache.demand_misses::total 223 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 223 # number of overall misses
system.iocache.overall_misses::total 223 # number of overall misses
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_miss_latency::realview.ide 28108377 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 28108377 # number of ReadReq miss cycles
2016-03-16 21:03:49 +01:00
system.iocache.WriteLineReq_miss_latency::realview.ide 4551692021 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4551692021 # number of WriteLineReq miss cycles
2015-12-05 01:11:25 +01:00
system.iocache.demand_miss_latency::realview.ide 28108377 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 28108377 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 28108377 # number of overall miss cycles
system.iocache.overall_miss_latency::total 28108377 # number of overall miss cycles
2015-11-06 09:26:50 +01:00
system.iocache.ReadReq_accesses::realview.ide 223 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 223 # number of ReadReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2015-11-06 09:26:50 +01:00
system.iocache.demand_accesses::realview.ide 223 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 223 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 223 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 223 # number of overall (read+write) accesses
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2015-09-25 13:27:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 126046.533632 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 126046.533632 # average ReadReq miss latency
2016-03-16 21:03:49 +01:00
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125654.042099 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125654.042099 # average WriteLineReq miss latency
2015-12-05 01:11:25 +01:00
system.iocache.demand_avg_miss_latency::realview.ide 126046.533632 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 126046.533632 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 126046.533632 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 126046.533632 # average overall miss latency
2016-02-10 10:08:27 +01:00
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2013-01-07 19:05:52 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-02-10 10:08:27 +01:00
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
2013-01-07 19:05:52 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2016-02-10 10:08:27 +01:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2013-01-07 19:05:52 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
2013-01-07 19:05:52 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
2015-09-25 13:27:03 +02:00
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
2015-11-06 09:26:50 +01:00
system.iocache.ReadReq_mshr_misses::realview.ide 223 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses
2015-09-25 13:27:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2015-11-06 09:26:50 +01:00
system.iocache.demand_mshr_misses::realview.ide 223 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 223 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 223 # number of overall MSHR misses
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_mshr_miss_latency::realview.ide 16958377 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 16958377 # number of ReadReq MSHR miss cycles
2016-03-16 21:03:49 +01:00
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2739094493 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2739094493 # number of WriteLineReq MSHR miss cycles
2015-12-05 01:11:25 +01:00
system.iocache.demand_mshr_miss_latency::realview.ide 16958377 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 16958377 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 16958377 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 16958377 # number of overall MSHR miss cycles
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2015-09-25 13:27:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76046.533632 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 76046.533632 # average ReadReq mshr miss latency
2016-03-16 21:03:49 +01:00
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75615.461931 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75615.461931 # average WriteLineReq mshr miss latency
2015-12-05 01:11:25 +01:00
system.iocache.demand_avg_mshr_miss_latency::realview.ide 76046.533632 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 76046.533632 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 76046.533632 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76046.533632 # average overall mshr miss latency
2013-01-07 19:05:52 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-03-16 21:03:49 +01:00
system.l2c.tags.replacements 104410 # number of replacements
system.l2c.tags.tagsinuse 65109.543238 # Cycle average of tags in use
system.l2c.tags.total_refs 5145971 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 169726 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 30.319285 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 74704682500 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 48981.216983 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 35.221338 # Average occupied blocks per requestor
2015-11-06 09:26:50 +01:00
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000314 # Average occupied blocks per requestor
2016-03-16 21:03:49 +01:00
system.l2c.tags.occ_blocks::cpu0.inst 4869.304478 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2909.290935 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 62.040813 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 5687.977666 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 2564.490710 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.747394 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000537 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
2016-03-16 21:03:49 +01:00
system.l2c.tags.occ_percent::cpu0.inst 0.074300 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.044392 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000947 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.086792 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.039131 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.993493 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 86 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 65230 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 86 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 3227 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 8986 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 52658 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.001312 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.995331 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 45480700 # Number of tag accesses
system.l2c.tags.data_accesses 45480700 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 34341 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 7550 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 36792 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 8227 # number of ReadReq hits
system.l2c.ReadReq_hits::total 86910 # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks 705007 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 705007 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 1896071 # number of WritebackClean hits
system.l2c.WritebackClean_hits::total 1896071 # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data 46 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 47 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 93 # number of UpgradeReq hits
2016-02-10 10:08:27 +01:00
system.l2c.SCUpgradeReq_hits::cpu0.data 28 # number of SCUpgradeReq hits
2016-03-16 21:03:49 +01:00
system.l2c.SCUpgradeReq_hits::cpu1.data 28 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 56 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 74731 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 81928 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 156659 # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 926609 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 989442 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 1916051 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 279682 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 263866 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 543548 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker 34341 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 7550 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 926609 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 354413 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 36792 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 8227 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 989442 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 345794 # number of demand (read+write) hits
system.l2c.demand_hits::total 2703168 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 34341 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 7550 # number of overall hits
system.l2c.overall_hits::cpu0.inst 926609 # number of overall hits
system.l2c.overall_hits::cpu0.data 354413 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 36792 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 8227 # number of overall hits
system.l2c.overall_hits::cpu1.inst 989442 # number of overall hits
system.l2c.overall_hits::cpu1.data 345794 # number of overall hits
system.l2c.overall_hits::total 2703168 # number of overall hits
2015-12-05 01:11:25 +01:00
system.l2c.ReadReq_misses::cpu0.dtb.walker 57 # number of ReadReq misses
2014-11-12 15:05:25 +01:00
system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
2016-03-16 21:03:49 +01:00
system.l2c.ReadReq_misses::cpu1.dtb.walker 83 # number of ReadReq misses
system.l2c.ReadReq_misses::total 141 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 1422 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1314 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2736 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 7 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 9 # number of SCUpgradeReq misses
2015-12-05 01:11:25 +01:00
system.l2c.SCUpgradeReq_misses::total 16 # number of SCUpgradeReq misses
2016-03-16 21:03:49 +01:00
system.l2c.ReadExReq_misses::cpu0.data 75412 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 64693 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 140105 # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst 9686 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst 11136 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total 20822 # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 8289 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 7100 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 15389 # number of ReadSharedReq misses
2015-12-05 01:11:25 +01:00
system.l2c.demand_misses::cpu0.dtb.walker 57 # number of demand (read+write) misses
2014-11-12 15:05:25 +01:00
system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
2016-03-16 21:03:49 +01:00
system.l2c.demand_misses::cpu0.inst 9686 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 83701 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 83 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 11136 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 71793 # number of demand (read+write) misses
system.l2c.demand_misses::total 176457 # number of demand (read+write) misses
2015-12-05 01:11:25 +01:00
system.l2c.overall_misses::cpu0.dtb.walker 57 # number of overall misses
2014-11-12 15:05:25 +01:00
system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
2016-03-16 21:03:49 +01:00
system.l2c.overall_misses::cpu0.inst 9686 # number of overall misses
system.l2c.overall_misses::cpu0.data 83701 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 83 # number of overall misses
system.l2c.overall_misses::cpu1.inst 11136 # number of overall misses
system.l2c.overall_misses::cpu1.data 71793 # number of overall misses
system.l2c.overall_misses::total 176457 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 7938500 # number of ReadReq miss cycles
2015-09-25 13:27:03 +02:00
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 132500 # number of ReadReq miss cycles
2016-03-16 21:03:49 +01:00
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 11650000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 19721000 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 1633500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 1873000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 3506500 # number of UpgradeReq miss cycles
2016-02-10 10:08:27 +01:00
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 237500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 627500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 865000 # number of SCUpgradeReq miss cycles
2016-03-16 21:03:49 +01:00
system.l2c.ReadExReq_miss_latency::cpu0.data 10074179000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 8644628500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 18718807500 # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1292910000 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 1482150999 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total 2775060999 # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 1120032000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 977768000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 2097800000 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 7938500 # number of demand (read+write) miss cycles
2015-09-25 13:27:03 +02:00
system.l2c.demand_miss_latency::cpu0.itb.walker 132500 # number of demand (read+write) miss cycles
2016-03-16 21:03:49 +01:00
system.l2c.demand_miss_latency::cpu0.inst 1292910000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 11194211000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 11650000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 1482150999 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 9622396500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 23611389499 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 7938500 # number of overall miss cycles
2015-09-25 13:27:03 +02:00
system.l2c.overall_miss_latency::cpu0.itb.walker 132500 # number of overall miss cycles
2016-03-16 21:03:49 +01:00
system.l2c.overall_miss_latency::cpu0.inst 1292910000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 11194211000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 11650000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 1482150999 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 9622396500 # number of overall miss cycles
system.l2c.overall_miss_latency::total 23611389499 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 34398 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 7551 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 36875 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 8227 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 87051 # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks 705007 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 705007 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks 1896071 # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total 1896071 # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 1468 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1361 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 2829 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 35 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 37 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 72 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 150143 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 146621 # number of ReadExReq accesses(hits+misses)
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2015-09-25 13:27:03 +02:00
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2016-03-16 21:03:49 +01:00
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2016-02-10 10:08:27 +01:00
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2016-03-16 21:03:49 +01:00
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2016-03-16 21:03:49 +01:00
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2014-11-12 15:05:25 +01:00
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2016-03-16 21:03:49 +01:00
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2016-03-16 21:03:49 +01:00
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2015-11-06 09:26:50 +01:00
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2016-03-16 21:03:49 +01:00
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2016-03-16 21:03:49 +01:00
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2016-03-16 21:03:49 +01:00
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2016-03-16 21:03:49 +01:00
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2016-03-16 21:03:49 +01:00
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2015-09-25 13:27:03 +02:00
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2016-03-16 21:03:49 +01:00
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2015-09-25 13:27:03 +02:00
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2016-03-16 21:03:49 +01:00
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system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000132 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.002251 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.001620 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.968665 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.965467 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.967126 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.200000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.243243 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.222222 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.502268 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.441226 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.472109 # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.010336 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011126 # mshr miss rate for ReadCleanReq accesses
2016-02-10 10:08:27 +01:00
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010744 # mshr miss rate for ReadCleanReq accesses
2016-03-16 21:03:49 +01:00
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.028562 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.025907 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.027275 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001657 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000132 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010336 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.190902 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.002251 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011126 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.171732 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.061224 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001657 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000132 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010336 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.190902 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.002251 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011126 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.171732 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.061224 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 129271.929825 # average ReadReq mshr miss latency
2015-09-25 13:27:03 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 122500 # average ReadReq mshr miss latency
2016-03-16 21:03:49 +01:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 130361.445783 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 129865.248227 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68022.503516 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68022.831050 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68022.660819 # average UpgradeReq mshr miss latency
2016-02-10 10:08:27 +01:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68500 # average SCUpgradeReq mshr miss latency
2016-03-16 21:03:49 +01:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68444.444444 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68468.750000 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 123588.533668 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123625.407695 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 123605.560123 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123537.508060 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 123103.934783 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123305.574483 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 125187.234772 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 127916.809402 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126444.146146 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 129271.929825 # average overall mshr miss latency
2015-09-25 13:27:03 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 122500 # average overall mshr miss latency
2016-03-16 21:03:49 +01:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123537.508060 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123745.752562 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130361.445783 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123103.934783 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124045.493871 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 123820.613689 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 129271.929825 # average overall mshr miss latency
2015-09-25 13:27:03 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 122500 # average overall mshr miss latency
2016-03-16 21:03:49 +01:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123537.508060 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123745.752562 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130361.445783 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123103.934783 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124045.493871 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 123820.613689 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113784.426647 # average ReadReq mshr uncacheable latency
2016-03-16 21:03:49 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188336.146130 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191333.801527 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 188313.693021 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158608.534262 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 190068.852592 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172711.396259 # average WriteReq mshr uncacheable latency
2015-11-06 09:26:50 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113784.426647 # average overall mshr uncacheable latency
2016-03-16 21:03:49 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173240.767306 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 190789.524041 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 181065.462608 # average overall mshr uncacheable latency
2014-11-12 15:05:25 +01:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::ReadReq 31797 # Transaction distribution
2016-03-16 21:03:49 +01:00
system.membus.trans_dist::ReadResp 68215 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::WriteReq 27588 # Transaction distribution
system.membus.trans_dist::WriteResp 27588 # Transaction distribution
2016-03-16 21:03:49 +01:00
system.membus.trans_dist::WritebackDirty 131889 # Transaction distribution
system.membus.trans_dist::CleanEvict 8934 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4627 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.membus.trans_dist::SCUpgradeReq 16 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
2016-03-16 21:03:49 +01:00
system.membus.trans_dist::ReadExReq 138214 # Transaction distribution
system.membus.trans_dist::ReadExResp 138214 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 36419 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2082 # Packet count per connected master and slave (bytes)
2016-03-16 21:03:49 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 468775 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 576357 # Packet count per connected master and slave (bytes)
2016-02-10 10:08:27 +01:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72875 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72875 # Packet count per connected master and slave (bytes)
2016-03-16 21:03:49 +01:00
system.membus.pkt_count::total 649232 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4164 # Cumulative packet size per connected master and slave (bytes)
2016-03-16 21:03:49 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17330524 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 17494517 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
2016-03-16 21:03:49 +01:00
system.membus.pkt_size::total 19811637 # Cumulative packet size per connected master and slave (bytes)
2016-02-10 10:08:27 +01:00
system.membus.snoops 495 # Total snoops (count)
2016-03-16 21:03:49 +01:00
system.membus.snoop_fanout::samples 415722 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2016-03-16 21:03:49 +01:00
system.membus.snoop_fanout::1 415722 100.00% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2016-03-16 21:03:49 +01:00
system.membus.snoop_fanout::total 415722 # Request fanout histogram
system.membus.reqLayer0.occupancy 95416500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-07-03 16:15:03 +02:00
system.membus.reqLayer1.occupancy 17812 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-03-16 21:03:49 +01:00
system.membus.reqLayer2.occupancy 1712500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-03-16 21:03:49 +01:00
system.membus.reqLayer5.occupancy 923381363 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2016-03-16 21:03:49 +01:00
system.membus.respLayer2.occupancy 1008957748 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.membus.respLayer3.occupancy 1182123 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2014-11-12 15:05:25 +01:00
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2016-03-16 21:03:49 +01:00
system.toL2Bus.snoop_filter.tot_requests 5624778 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 2831936 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 48182 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 419 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 419 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-03-16 21:03:49 +01:00
system.toL2Bus.trans_dist::ReadReq 148456 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2644699 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.toL2Bus.trans_dist::WriteReq 27588 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 27588 # Transaction distribution
2016-03-16 21:03:49 +01:00
system.toL2Bus.trans_dist::WritebackDirty 836907 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 1936583 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 159084 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 2829 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 72 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 2901 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 296764 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 296764 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 1937168 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 559160 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
2016-03-16 21:03:49 +01:00
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5811959 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2689934 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41086 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 162624 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 8705603 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 247943872 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 100077301 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 63112 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 285092 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 348369377 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 207323 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 3149099 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.027296 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.162945 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-03-16 21:03:49 +01:00
system.toL2Bus.snoop_fanout::0 3063141 97.27% 97.27% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 85958 2.73% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2016-03-16 21:03:49 +01:00
system.toL2Bus.snoop_fanout::total 3149099 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 5537165495 # Layer occupancy (ticks)
2015-11-06 09:26:50 +01:00
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.toL2Bus.snoopLayer0.occupancy 269377 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-03-16 21:03:49 +01:00
system.toL2Bus.respLayer0.occupancy 2908738015 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2016-03-16 21:03:49 +01:00
system.toL2Bus.respLayer1.occupancy 1330413513 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-03-16 21:03:49 +01:00
system.toL2Bus.respLayer2.occupancy 25349416 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-03-16 21:03:49 +01:00
system.toL2Bus.respLayer3.occupancy 91789111 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2013-01-07 19:05:52 +01:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
2015-09-25 13:27:03 +02:00
system.cpu0.kern.inst.quiesce 3037 # number of quiesce instructions executed
2013-01-07 19:05:52 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
