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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt

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tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
---------- Begin Simulation Statistics ----------
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
sim_seconds 2.804327 # Number of seconds simulated
sim_ticks 2804326619500 # Number of ticks simulated
final_tick 2804326619500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
host_inst_rate 119116 # Simulator instruction rate (inst/s)
host_op_rate 144575 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2855979889 # Simulator tick rate (ticks/s)
host_mem_usage 563896 # Number of bytes of host memory used
host_seconds 981.91 # Real time elapsed on the host
sim_insts 116961561 # Number of instructions simulated
sim_ops 141959724 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.realview.nvmem.bytes_read::cpu0.inst 640 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 640 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 640 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 640 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 10 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 10 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 228 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 228 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 228 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 228 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 228 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 228 # Total bandwidth to/from this memory (bytes/s)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.bytes_read::cpu0.dtb.walker 4352 # Number of bytes read from this memory
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.bytes_read::cpu0.inst 740544 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 5179680 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 4416 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 636864 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 4641732 # Number of bytes read from this memory
system.physmem.bytes_read::total 11208612 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 740544 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 636864 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1377408 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 6113984 # Number of bytes written to this memory
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.bytes_written::total 8449844 # Number of bytes written to this memory
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.num_reads::cpu0.dtb.walker 68 # Number of read requests responded to by this memory
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.num_reads::cpu0.inst 11571 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 81451 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 69 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 9951 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 72528 # Number of read requests responded to by this memory
system.physmem.num_reads::total 175654 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 95531 # Number of write requests responded to by this memory
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.num_writes::total 136136 # Number of write requests responded to by this memory
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.bw_read::cpu0.dtb.walker 1552 # Total read bandwidth from this memory (bytes/s)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.bw_read::cpu0.inst 264072 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1847032 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 1575 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 227101 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1655204 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3996900 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 264072 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 227101 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 491172 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2180197 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::realview.ide 826700 # Write bandwidth from this memory (bytes/s)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.bw_write::cpu0.data 6246 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.bw_write::total 3013145 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2180197 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 827042 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 1552 # Total bandwidth to/from this memory (bytes/s)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.bw_total::cpu0.inst 264072 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1853278 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 1575 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 227101 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 1655207 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7010045 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 175655 # Number of read requests accepted
system.physmem.writeReqs 136136 # Number of write requests accepted
system.physmem.readBursts 175655 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 136136 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 11233984 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 7936 # Total number of bytes read from write queue
system.physmem.bytesWritten 8463616 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 11208676 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 8449844 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 124 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3872 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 4658 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 11108 # Per bank write bursts
system.physmem.perBankRdBursts::1 11142 # Per bank write bursts
system.physmem.perBankRdBursts::2 11724 # Per bank write bursts
system.physmem.perBankRdBursts::3 11223 # Per bank write bursts
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.perBankRdBursts::4 11369 # Per bank write bursts
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.perBankRdBursts::5 11393 # Per bank write bursts
system.physmem.perBankRdBursts::6 11953 # Per bank write bursts
system.physmem.perBankRdBursts::7 11818 # Per bank write bursts
system.physmem.perBankRdBursts::8 10217 # Per bank write bursts
system.physmem.perBankRdBursts::9 10450 # Per bank write bursts
system.physmem.perBankRdBursts::10 10599 # Per bank write bursts
system.physmem.perBankRdBursts::11 9773 # Per bank write bursts
system.physmem.perBankRdBursts::12 10412 # Per bank write bursts
system.physmem.perBankRdBursts::13 11414 # Per bank write bursts
system.physmem.perBankRdBursts::14 10639 # Per bank write bursts
system.physmem.perBankRdBursts::15 10297 # Per bank write bursts
system.physmem.perBankWrBursts::0 8312 # Per bank write bursts
system.physmem.perBankWrBursts::1 8440 # Per bank write bursts
system.physmem.perBankWrBursts::2 9043 # Per bank write bursts
system.physmem.perBankWrBursts::3 8548 # Per bank write bursts
system.physmem.perBankWrBursts::4 8346 # Per bank write bursts
system.physmem.perBankWrBursts::5 8542 # Per bank write bursts
system.physmem.perBankWrBursts::6 8974 # Per bank write bursts
system.physmem.perBankWrBursts::7 8818 # Per bank write bursts
system.physmem.perBankWrBursts::8 7763 # Per bank write bursts
system.physmem.perBankWrBursts::9 7812 # Per bank write bursts
system.physmem.perBankWrBursts::10 7942 # Per bank write bursts
system.physmem.perBankWrBursts::11 7398 # Per bank write bursts
system.physmem.perBankWrBursts::12 7887 # Per bank write bursts
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.perBankWrBursts::13 8744 # Per bank write bursts
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.perBankWrBursts::14 8046 # Per bank write bursts
system.physmem.perBankWrBursts::15 7629 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.numWrRetry 14 # Number of times write queue was full causing retry
system.physmem.totGap 2804326433500 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.readPktSize::2 541 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.readPktSize::6 175100 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.writePktSize::6 131755 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 104424 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 61078 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 8506 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1503 # What read queue length does an incoming req see
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.wrQLenPdf::0 106 # What write queue length does an incoming req see
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 93 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 93 # What write queue length does an incoming req see
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.wrQLenPdf::4 90 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 89 # What write queue length does an incoming req see
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.wrQLenPdf::6 93 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 93 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 93 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 90 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 92 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 92 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 92 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 86 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 88 # What write queue length does an incoming req see
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.wrQLenPdf::15 2034 # What write queue length does an incoming req see
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.wrQLenPdf::16 2586 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4529 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6433 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6799 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 7535 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 7769 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 8333 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 8830 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 9585 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 9109 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 8670 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 8281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 8757 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7217 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7138 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7317 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 6805 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 229 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 205 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 196 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 176 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 184 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 179 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 195 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 174 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 161 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 150 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 143 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 151 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 144 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 120 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 115 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 91 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 83 # What write queue length does an incoming req see
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.wrQLenPdf::51 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 29 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 21 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 26 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 32 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 22 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 31 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 64866 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 303.665033 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 178.572173 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 327.227913 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 24436 37.67% 37.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 15780 24.33% 62.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6593 10.16% 72.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3751 5.78% 77.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2794 4.31% 82.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1520 2.34% 84.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1090 1.68% 86.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1132 1.75% 88.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7770 11.98% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 64866 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6698 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 26.205584 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 477.627003 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 6695 99.96% 99.96% # Reads before turning the bus around for writes
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-8191 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::36864-38911 1 0.01% 100.00% # Reads before turning the bus around for writes
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.rdPerTurnAround::total 6698 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6698 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 19.743804 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.225845 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 11.527754 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 13 0.19% 0.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 9 0.13% 0.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11 4 0.06% 0.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15 9 0.13% 0.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 5778 86.26% 86.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 106 1.58% 88.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 43 0.64% 89.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 223 3.33% 92.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 204 3.05% 95.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 17 0.25% 95.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 22 0.33% 95.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 15 0.22% 96.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 32 0.48% 96.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 10 0.15% 96.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 8 0.12% 96.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 5 0.07% 97.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 143 2.13% 99.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 6 0.09% 99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 3 0.04% 99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 6 0.09% 99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 10 0.15% 99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 1 0.01% 99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 5 0.07% 99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 4 0.06% 99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 1 0.01% 99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 3 0.04% 99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 3 0.04% 99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 3 0.04% 99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.01% 99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 8 0.12% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 2 0.03% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 1 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6698 # Writes before turning the bus around for reads
system.physmem.totQLat 2733630250 # Total ticks spent queuing
system.physmem.totMemAccLat 6024836500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 877655000 # Total ticks spent in databus transfers
system.physmem.avgQLat 15573.49 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.avgMemAccLat 34323.49 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.01 # Average DRAM read bandwidth in MiByte/s
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 4.00 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 3.01 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.avgRdQLen 1.63 # Average read queue length when enqueuing
system.physmem.avgWrQLen 10.73 # Average write queue length when enqueuing
system.physmem.readRowHits 145110 # Number of row buffer hits during reads
system.physmem.writeRowHits 97798 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.67 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 73.94 # Row buffer hit rate for writes
system.physmem.avgGap 8994250.74 # Average gap between requests
system.physmem.pageHitRate 78.92 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 2678438745750 # Time in different power states
system.physmem.memoryStateTime::REF 93642380000 # Time in different power states
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.memoryStateTime::ACT 32245482750 # Time in different power states
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.actEnergy::0 259141680 # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1 231245280 # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0 141396750 # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1 126175500 # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0 715486200 # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1 653647800 # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0 447269040 # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1 409672080 # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0 183164495280 # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1 183164495280 # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0 77839312860 # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1 76923425745 # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0 1614311544000 # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1 1615114953750 # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0 1876878645810 # Total energy per rank (pJ)
system.physmem.totalEnergy::1 1876623615435 # Total energy per rank (pJ)
system.physmem.averagePower::0 669.281339 # Core power per rank (mW)
system.physmem.averagePower::1 669.190397 # Core power per rank (mW)
system.membus.trans_dist::ReadReq 68041 # Transaction distribution
system.membus.trans_dist::ReadResp 68040 # Transaction distribution
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.membus.trans_dist::WriteReq 27608 # Transaction distribution
system.membus.trans_dist::WriteResp 27608 # Transaction distribution
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.membus.trans_dist::Writeback 95531 # Transaction distribution
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.membus.trans_dist::UpgradeReq 4632 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 26 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4658 # Transaction distribution
system.membus.trans_dist::ReadExReq 138441 # Transaction distribution
system.membus.trans_dist::ReadExResp 138441 # Transaction distribution
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 20 # Packet count per connected master and slave (bytes)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 464888 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 572528 # Packet count per connected master and slave (bytes)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72712 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72712 # Packet count per connected master and slave (bytes)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.membus.pkt_count::total 645240 # Packet count per connected master and slave (bytes)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 640 # Cumulative packet size per connected master and slave (bytes)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17339160 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 17503137 # Cumulative packet size per connected master and slave (bytes)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.membus.pkt_size::total 19822433 # Cumulative packet size per connected master and slave (bytes)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.membus.snoops 234 # Total snoops (count)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.membus.snoop_fanout::samples 311110 # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.membus.snoop_fanout::1 311110 100.00% 100.00% # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.membus.snoop_fanout::total 311110 # Request fanout histogram
system.membus.reqLayer0.occupancy 81518499 # Layer occupancy (ticks)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.membus.reqLayer1.occupancy 15812 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.membus.reqLayer2.occupancy 1693000 # Layer occupancy (ticks)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.membus.reqLayer5.occupancy 1434327498 # Layer occupancy (ticks)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.membus.respLayer2.occupancy 1730433594 # Layer occupancy (ticks)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.membus.respLayer3.occupancy 38513958 # Layer occupancy (ticks)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.tags.replacements 104268 # number of replacements
system.l2c.tags.tagsinuse 65131.307742 # Cycle average of tags in use
system.l2c.tags.total_refs 3106944 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 169509 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 18.329080 # Average number of references to valid blocks.
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.tags.occ_blocks::writebacks 48616.163532 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 48.311212 # Average occupied blocks per requestor
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000235 # Average occupied blocks per requestor
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.tags.occ_blocks::cpu0.inst 5571.967356 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2874.440506 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 44.347195 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 4984.192297 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 2991.885408 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.741824 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000737 # Average percentage of cache occupancy
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.tags.occ_percent::cpu0.inst 0.085021 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.043860 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000677 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.076053 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.045653 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.993825 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 63 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 65178 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 63 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 332 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 3243 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 8995 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 52594 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.000961 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.994537 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 29221748 # Number of tag accesses
system.l2c.tags.data_accesses 29221748 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 36519 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 8855 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 959908 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 271615 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 36602 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 7424 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 964068 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 269451 # number of ReadReq hits
system.l2c.ReadReq_hits::total 2554442 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 703423 # number of Writeback hits
system.l2c.Writeback_hits::total 703423 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 37 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 59 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 96 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 21 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 32 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 53 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 77798 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 78748 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 156546 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 36519 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 8855 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 959908 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 349413 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 36602 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 7424 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 964068 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 348199 # number of demand (read+write) hits
system.l2c.demand_hits::total 2710988 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 36519 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 8855 # number of overall hits
system.l2c.overall_hits::cpu0.inst 959908 # number of overall hits
system.l2c.overall_hits::cpu0.data 349413 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 36602 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 7424 # number of overall hits
system.l2c.overall_hits::cpu1.inst 964068 # number of overall hits
system.l2c.overall_hits::cpu1.data 348199 # number of overall hits
system.l2c.overall_hits::total 2710988 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 68 # number of ReadReq misses
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.ReadReq_misses::cpu0.inst 10928 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 7151 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 69 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 9955 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 7971 # number of ReadReq misses
system.l2c.ReadReq_misses::total 36143 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 1299 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1443 # number of UpgradeReq misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.l2c.UpgradeReq_misses::total 2742 # number of UpgradeReq misses
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.SCUpgradeReq_misses::cpu0.data 8 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 18 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 26 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 74760 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 65571 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 140331 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 68 # number of demand (read+write) misses
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.demand_misses::cpu0.inst 10928 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 81911 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 69 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 9955 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 73542 # number of demand (read+write) misses
system.l2c.demand_misses::total 176474 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 68 # number of overall misses
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.overall_misses::cpu0.inst 10928 # number of overall misses
system.l2c.overall_misses::cpu0.data 81911 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 69 # number of overall misses
system.l2c.overall_misses::cpu1.inst 9955 # number of overall misses
system.l2c.overall_misses::cpu1.data 73542 # number of overall misses
system.l2c.overall_misses::total 176474 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 5396500 # number of ReadReq miss cycles
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 74500 # number of ReadReq miss cycles
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.ReadReq_miss_latency::cpu0.inst 829990750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 573729742 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 5378000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 749581500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 653390493 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 2817541485 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 304487 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 465980 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 770467 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 116995 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 162993 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 279988 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 5741255809 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 5109104302 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 10850360111 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 5396500 # number of demand (read+write) miss cycles
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.l2c.demand_miss_latency::cpu0.itb.walker 74500 # number of demand (read+write) miss cycles
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.demand_miss_latency::cpu0.inst 829990750 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 6314985551 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 5378000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 749581500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 5762494795 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 13667901596 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 5396500 # number of overall miss cycles
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.l2c.overall_miss_latency::cpu0.itb.walker 74500 # number of overall miss cycles
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.overall_miss_latency::cpu0.inst 829990750 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 6314985551 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 5378000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 749581500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 5762494795 # number of overall miss cycles
system.l2c.overall_miss_latency::total 13667901596 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 36587 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 8856 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 970836 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 278766 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 36671 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 7424 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 974023 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 277422 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2590585 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 703423 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 703423 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 1336 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1502 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 2838 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 29 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 50 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 79 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 152558 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 144319 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 296877 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 36587 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 8856 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 970836 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 431324 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 36671 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 7424 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 974023 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 421741 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2887462 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 36587 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 8856 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 970836 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 431324 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 36671 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 7424 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 974023 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 421741 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2887462 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001859 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000113 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.011256 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.025652 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001882 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.010220 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.028732 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.013952 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.972305 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.960719 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.966173 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.275862 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.360000 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.329114 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.490043 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.454348 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.472691 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001859 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000113 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.011256 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.189906 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.001882 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.010220 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.174377 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.061117 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001859 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000113 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.011256 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.189906 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.001882 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.010220 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.174377 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.061117 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79360.294118 # average ReadReq miss latency
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74500 # average ReadReq miss latency
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 75950.837299 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 80230.700881 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 77942.028986 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75296.986439 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 81970.956342 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 77955.385137 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 234.401078 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 322.924463 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 280.987236 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14624.375000 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9055.166667 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 10768.769231 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76795.824090 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77917.132604 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 77319.766203 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79360.294118 # average overall miss latency
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74500 # average overall miss latency
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.demand_avg_miss_latency::cpu0.inst 75950.837299 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 77095.695950 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 77942.028986 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 75296.986439 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 78356.514577 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 77449.945012 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79360.294118 # average overall miss latency
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74500 # average overall miss latency
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.overall_avg_miss_latency::cpu0.inst 75950.837299 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 77095.695950 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 77942.028986 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 75296.986439 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 78356.514577 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 77449.945012 # average overall miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.writebacks::writebacks 95531 # number of writebacks
system.l2c.writebacks::total 95531 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst 7 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data 73 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst 4 # number of ReadReq MSHR hits
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.l2c.ReadReq_mshr_hits::cpu1.data 66 # number of ReadReq MSHR hits
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.ReadReq_mshr_hits::total 150 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data 73 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.l2c.demand_mshr_hits::cpu1.data 66 # number of demand (read+write) MSHR hits
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.demand_mshr_hits::total 150 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data 73 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.l2c.overall_mshr_hits::cpu1.data 66 # number of overall MSHR hits
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.overall_mshr_hits::total 150 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 68 # number of ReadReq MSHR misses
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.ReadReq_mshr_misses::cpu0.inst 10921 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 7078 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 69 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 9951 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 7905 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 35993 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 1299 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1443 # number of UpgradeReq MSHR misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.l2c.UpgradeReq_mshr_misses::total 2742 # number of UpgradeReq MSHR misses
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 8 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 18 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 26 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 74760 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 65571 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 140331 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 68 # number of demand (read+write) MSHR misses
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.demand_mshr_misses::cpu0.inst 10921 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 81838 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 69 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 9951 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 73476 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 176324 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 68 # number of overall MSHR misses
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.overall_mshr_misses::cpu0.inst 10921 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 81838 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 69 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 9951 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 73476 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 176324 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4553000 # number of ReadReq MSHR miss cycles
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 692294000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 481153492 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4523000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 624075250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 550752493 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 2357413735 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 12992798 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14497943 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 27490741 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 80008 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 180018 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 260026 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4808098691 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4293415698 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 9101514389 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 4553000 # number of demand (read+write) MSHR miss cycles
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.demand_mshr_miss_latency::cpu0.inst 692294000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 5289252183 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 4523000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 624075250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 4844168191 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 11458928124 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 4553000 # number of overall MSHR miss cycles
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.overall_mshr_miss_latency::cpu0.inst 692294000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 5289252183 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 4523000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 624075250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 4844168191 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 11458928124 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 35706500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2951899000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2427344000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 5414949500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2228650000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1873529499 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 4102179499 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 35706500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5180549000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4300873499 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 9517128999 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001859 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000113 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.011249 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.025390 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001882 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010216 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.028494 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.013894 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.972305 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.960719 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.966173 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.275862 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.360000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.329114 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.490043 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.454348 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.472691 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001859 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000113 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.011249 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.189737 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001882 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010216 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.174221 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.061065 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001859 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000113 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.011249 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.189737 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001882 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010216 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.174221 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.061065 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66955.882353 # average ReadReq mshr miss latency
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63391.081403 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67978.735801 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65550.724638 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62714.827656 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 69671.409614 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 65496.450282 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10002.153965 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10047.084546 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10025.799052 # average UpgradeReq mshr miss latency
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 64313.786664 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65477.355813 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 64857.475462 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66955.882353 # average overall mshr miss latency
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63391.081403 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64630.760564 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65550.724638 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62714.827656 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65928.577917 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 64987.909326 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66955.882353 # average overall mshr miss latency
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63391.081403 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64630.760564 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65550.724638 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62714.827656 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65928.577917 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 64987.909326 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.toL2Bus.trans_dist::ReadReq 2655325 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2655239 # Transaction distribution
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.toL2Bus.trans_dist::Writeback 703423 # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq 36238 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 2838 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 79 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 2917 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 296877 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 296877 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3891298 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2533043 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42437 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 169072 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 6635850 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124513216 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99808865 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 65120 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 293032 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 224680233 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 69343 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 3662983 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 5.009961 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.099307 # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.toL2Bus.snoop_fanout::5 3626496 99.00% 99.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::6 36487 1.00% 100.00% # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.toL2Bus.snoop_fanout::total 3662983 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 4670881246 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.toL2Bus.snoopLayer0.occupancy 738000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.toL2Bus.respLayer0.occupancy 8762800197 # Layer occupancy (ticks)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.toL2Bus.respLayer1.occupancy 3909656420 # Layer occupancy (ticks)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.toL2Bus.respLayer2.occupancy 26229350 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.toL2Bus.respLayer3.occupancy 96621860 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iobus.trans_dist::ReadReq 30210 # Transaction distribution
system.iobus.trans_dist::ReadResp 30210 # Transaction distribution
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.iobus.trans_dist::WriteReq 59030 # Transaction distribution
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.iobus.trans_dist::WriteInvalidateReq 8 # Transaction distribution
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 178496 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480421 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.iobus.reqLayer27.occupancy 326627644 # Layer occupancy (ticks)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.iobus.respLayer3.occupancy 36841042 # Layer occupancy (ticks)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.branchPred.lookups 27349422 # Number of BP lookups
system.cpu0.branchPred.condPredicted 14250256 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 549515 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 17066610 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 12886962 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.branchPred.BTBHitPct 75.509794 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 6758521 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 30298 # Number of incorrect RAS predictions.
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.dtb.read_hits 14278108 # DTB read hits
system.cpu0.dtb.read_misses 49273 # DTB read misses
system.cpu0.dtb.write_hits 10337716 # DTB write hits
system.cpu0.dtb.write_misses 7471 # DTB write misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dtb.flush_tlb 178 # Number of times complete TLB was flushed
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.dtb.flush_tlb_mva 473 # Number of times TLB was flushed by MVA
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.dtb.flush_entries 3414 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 948 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 1297 # Number of TLB faults due to prefetch
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.dtb.perms_faults 559 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 14327381 # DTB read accesses
system.cpu0.dtb.write_accesses 10345187 # DTB write accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.dtb.hits 24615824 # DTB hits
system.cpu0.dtb.misses 56744 # DTB misses
system.cpu0.dtb.accesses 24672568 # DTB accesses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.itb.inst_hits 20514368 # ITB inst hits
system.cpu0.itb.inst_misses 8789 # ITB inst misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.itb.flush_tlb 178 # Number of times complete TLB was flushed
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.itb.flush_tlb_mva 473 # Number of times TLB was flushed by MVA
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.itb.flush_entries 2304 # Number of entries that have been flushed from TLB
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.itb.perms_faults 1449 # Number of TLB faults due to permissions restrictions
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.itb.inst_accesses 20523157 # ITB inst accesses
system.cpu0.itb.hits 20514368 # DTB hits
system.cpu0.itb.misses 8789 # DTB misses
system.cpu0.itb.accesses 20523157 # DTB accesses
system.cpu0.numCycles 107867607 # number of cpu cycles simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.fetch.icacheStallCycles 40554205 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 105662539 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 27349422 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 19645483 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 61985766 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 3245353 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 132544 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 7121 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles 440 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles 622961 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 144030 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 269 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 20513111 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 376873 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 3476 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 105069976 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 1.208080 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.305286 # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.fetch.rateDist::0 75961238 72.30% 72.30% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 3886755 3.70% 76.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 2398368 2.28% 78.28% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 8188948 7.79% 86.07% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 1668369 1.59% 87.66% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 1057044 1.01% 88.67% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 6240721 5.94% 94.60% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 1068642 1.02% 95.62% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 4599891 4.38% 100.00% # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.fetch.rateDist::total 105069976 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.253546 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.979558 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 28001193 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 58307153 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 15793340 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 1494905 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 1473111 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 1905219 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 151604 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 87425197 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 489487 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 1473111 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 28862922 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 7852670 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 44540857 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 16413726 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 5926414 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 83594857 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 2128 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 1233256 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 243031 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 3726809 # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands 86235184 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 384969647 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 93192750 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 5702 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 72438827 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 13796341 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 1547496 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 1453336 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 8912532 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 15029778 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 11466004 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1956224 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 2714292 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 80433839 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1054374 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 77107853 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 91926 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 10053145 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 24795847 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 115089 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 105069976 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.733871 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.427930 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.iq.issued_per_cycle::0 74334112 70.75% 70.75% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 10187384 9.70% 80.44% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 7871575 7.49% 87.93% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 6574512 6.26% 94.19% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 2321319 2.21% 96.40% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 1487177 1.42% 97.82% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 1563743 1.49% 99.31% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 491068 0.47% 99.77% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 239086 0.23% 100.00% # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.iq.issued_per_cycle::total 105069976 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.iq.fu_full::IntAlu 112390 9.87% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 3 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.87% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 534190 46.93% 56.80% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 491756 43.20% 100.00% # attempts to use FU when none available
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.iq.FU_type_0::No_OpClass 2199 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 51438430 66.71% 66.71% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 57761 0.07% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 1 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 4468 0.01% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 14680887 19.04% 85.83% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 10924099 14.17% 100.00% # Type of FU issued
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.iq.FU_type_0::total 77107853 # Type of FU issued
system.cpu0.iq.rate 0.714838 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 1138339 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.014763 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 260503389 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 91586031 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 74660496 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 12558 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 6677 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 5497 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 78237256 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 6737 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 345558 # Number of loads that had data forwarded from stores
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.iew.lsq.thread0.squashedLoads 2209259 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 2417 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 52309 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 1126312 # Number of stores squashed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 207644 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 205299 # Number of times an access to memory failed due to the cache being blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.iew.iewSquashCycles 1473111 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 5378277 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 2195764 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 81614966 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 130944 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 15029778 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 11466004 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 550994 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 44204 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 2139047 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 52309 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 254090 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 219689 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 473779 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 76503781 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 14445333 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 547436 # Number of squashed instructions skipped in execute
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.iew.exec_nop 126753 # number of nop insts executed
system.cpu0.iew.exec_refs 25264055 # number of memory reference insts executed
system.cpu0.iew.exec_branches 14430009 # Number of branches executed
system.cpu0.iew.exec_stores 10818722 # Number of stores executed
system.cpu0.iew.exec_rate 0.709238 # Inst execution rate
system.cpu0.iew.wb_sent 75844960 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 74665993 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 39001048 # num instructions producing a value
system.cpu0.iew.wb_consumers 67639279 # num instructions consuming a value
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.iew.wb_rate 0.692200 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.576604 # average fanout of values written-back
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.commit.commitSquashedInsts 11323076 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 939285 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 399913 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 102514186 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.684864 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.574695 # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.commit.committed_per_cycle::0 75189561 73.35% 73.35% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 12242134 11.94% 85.29% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 6265138 6.11% 91.40% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 2642512 2.58% 93.98% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 1297372 1.27% 95.24% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 836423 0.82% 96.06% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 1889134 1.84% 97.90% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 413413 0.40% 98.30% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1738499 1.70% 100.00% # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.commit.committed_per_cycle::total 102514186 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 57883100 # Number of instructions committed
system.cpu0.commit.committedOps 70208236 # Number of ops (including micro ops) committed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.commit.refs 23160211 # Number of memory references committed
system.cpu0.commit.loads 12820519 # Number of loads committed
system.cpu0.commit.membars 372556 # Number of memory barriers committed
system.cpu0.commit.branches 13646736 # Number of branches committed
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.commit.fp_insts 5463 # Number of committed floating point instructions.
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.commit.int_insts 61470931 # Number of committed integer instructions.
system.cpu0.commit.function_calls 2656843 # Number of function calls committed.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.commit.op_class_0::IntAlu 46987548 66.93% 66.93% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 56009 0.08% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 4468 0.01% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 12820519 18.26% 85.27% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 10339692 14.73% 100.00% # Class of committed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.commit.op_class_0::total 70208236 # Class of committed instruction
system.cpu0.commit.bw_lim_events 1738499 # number cycles where commit BW limit reached
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.rob.rob_reads 169645518 # The number of ROB reads
system.cpu0.rob.rob_writes 165622521 # The number of ROB writes
system.cpu0.timesIdled 399235 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 2797631 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 2442097834 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 57811199 # Number of Instructions Simulated
system.cpu0.committedOps 70136335 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.865860 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.865860 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.535946 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.535946 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 83226933 # number of integer regfile reads
system.cpu0.int_regfile_writes 47573974 # number of integer regfile writes
system.cpu0.fp_regfile_reads 16207 # number of floating regfile reads
system.cpu0.fp_regfile_writes 13000 # number of floating regfile writes
system.cpu0.cc_regfile_reads 270444340 # number of cc regfile reads
system.cpu0.cc_regfile_writes 28203341 # number of cc regfile writes
system.cpu0.misc_regfile_reads 191459430 # number of misc regfile reads
system.cpu0.misc_regfile_writes 720407 # number of misc regfile writes
system.cpu0.icache.tags.replacements 1944509 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.580286 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 39079293 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1945021 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 20.091965 # Average number of references to valid blocks.
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.icache.tags.warmup_cycle 9481344250 # Cycle when the warmup percentage was hit.
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.icache.tags.occ_blocks::cpu0.inst 277.092053 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 234.488233 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.541195 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.457985 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999180 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 154 # Occupied blocks per task id
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.icache.tags.tag_accesses 43109447 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 43109447 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 19472177 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 19607116 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 39079293 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 19472177 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 19607116 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 39079293 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 19472177 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 19607116 # number of overall hits
system.cpu0.icache.overall_hits::total 39079293 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 1040272 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 1044765 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 2085037 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 1040272 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 1044765 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 2085037 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 1040272 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 1044765 # number of overall misses
system.cpu0.icache.overall_misses::total 2085037 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14234369484 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14196293397 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 28430662881 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 14234369484 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 14196293397 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 28430662881 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 14234369484 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 14196293397 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 28430662881 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 20512449 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 20651881 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 41164330 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 20512449 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 20651881 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 41164330 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 20512449 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 20651881 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 41164330 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050714 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.050589 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.050652 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050714 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.050589 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.050652 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050714 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.050589 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.050652 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13683.315021 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13588.025438 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13635.567561 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13683.315021 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13588.025438 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13635.567561 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13683.315021 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13588.025438 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13635.567561 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 8976 # number of cycles access was blocked
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.icache.blocked::no_mshrs 503 # number of cycles access was blocked
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.844930 # average number of cycles each access was blocked
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 69341 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 70578 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 139919 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 69341 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst 70578 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 139919 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 69341 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst 70578 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 139919 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 970931 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 974187 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 1945118 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 970931 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 974187 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 1945118 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 970931 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 974187 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 1945118 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11624310724 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11588912543 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 23213223267 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11624310724 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11588912543 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 23213223267 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11624310724 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11588912543 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 23213223267 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 49455500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 49455500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 49455500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 49455500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.047334 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.047172 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047253 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.047334 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.047172 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.047253 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.047334 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.047172 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.047253 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11972.334516 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11895.983567 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11934.095138 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11972.334516 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11895.983567 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11934.095138 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11972.334516 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11895.983567 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11934.095138 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.dcache.tags.replacements 852532 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.984435 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 42510984 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 853044 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 49.834456 # Average number of references to valid blocks.
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.tags.warmup_cycle 91705250 # Cycle when the warmup percentage was hit.
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 328.580964 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 183.403471 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.641760 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.358210 # Average percentage of cache occupancy
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.dcache.tags.tag_accesses 189858417 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 189858417 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 12600621 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 12736293 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 25336914 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 7729736 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 8172690 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 15902426 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 180938 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 181427 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 362365 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 207885 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 238844 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 446729 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 213819 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 245596 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 459415 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 20330357 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 20908983 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 41239340 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 20511295 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 21090410 # number of overall hits
system.cpu0.dcache.overall_hits::total 41601705 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 423569 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 406804 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 830373 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1914715 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 1788827 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 3703542 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 96924 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 84951 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 181875 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13440 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14180 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 27620 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 29 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 50 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 79 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 2338284 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 2195631 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 4533915 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 2435208 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 2280582 # number of overall misses
system.cpu0.dcache.overall_misses::total 4715790 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7009049435 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6678797631 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 13687847066 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 84691128349 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 74764779722 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 159455908071 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 183084493 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 209418995 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 392503488 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 480508 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 880018 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 1360526 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 91700177784 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 81443577353 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 173143755137 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 91700177784 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 81443577353 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 173143755137 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 13024190 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 13143097 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 26167287 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 9644451 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 9961517 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 19605968 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 277862 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 266378 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 544240 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 221325 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 253024 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 474349 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 213848 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 245646 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 459494 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 22668641 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 23104614 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 45773255 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 22946503 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 23370992 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 46317495 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032522 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.030952 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.031733 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.198530 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.179574 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.188899 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.348821 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.318911 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.334182 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060725 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056042 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058227 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000136 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000204 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000172 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.103151 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.095030 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.099052 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.106125 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.097582 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.101814 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16547.597759 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16417.728515 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 16483.974149 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44231.715085 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41795.422208 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 43054.974959 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13622.358110 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14768.617419 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14210.843157 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16569.241379 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 17600.360000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 17221.848101 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39216.869202 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 37093.472151 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 38188.575467 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37655.993978 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35711.751366 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 36715.747550 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 1113759 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 155988 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 70298 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 2399 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.843395 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 65.022093 # average number of cycles each access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.dcache.writebacks::writebacks 703423 # number of writebacks
system.cpu0.dcache.writebacks::total 703423 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 211999 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 192913 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 404912 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1760835 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1643027 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 3403862 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 9519 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8988 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18507 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1972834 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 1835940 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 3808774 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1972834 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 1835940 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 3808774 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 211570 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 213891 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 425461 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 153880 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 145800 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 299680 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 63289 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 58360 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 121649 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 3921 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5192 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9113 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 29 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 50 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 79 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 365450 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 359691 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 725141 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 428739 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 418051 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 846790 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2855948132 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2928153928 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5784102060 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6788973337 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6163703908 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12952677245 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 974890008 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 904686758 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1879576766 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 46893501 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 79693003 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 126586504 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 422492 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 779982 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1202474 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9644921469 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9091857836 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 18736779305 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10619811477 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9996544594 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 20616356071 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3173945001 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2610547002 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5784492003 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2430732877 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2005306500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4436039377 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5604677878 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4615853502 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10220531380 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016244 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016274 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016259 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015955 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014636 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015285 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.227771 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.219087 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223521 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017716 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020520 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019212 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000136 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000204 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000172 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016121 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015568 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.015842 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018684 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017888 # mshr miss rate for overall accesses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.overall_mshr_miss_rate::total 0.018282 # mshr miss rate for overall accesses
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13498.833162 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13689.935191 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13594.905432 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44118.620594 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42275.061097 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43221.693957 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15403.782774 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15501.829301 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15450.819703 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11959.576894 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15349.191641 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13890.760891 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14568.689655 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15599.640000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15221.189873 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26391.904416 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25276.856624 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25838.808321 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24769.875092 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23912.260930 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24346.480321 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.branchPred.lookups 27353552 # Number of BP lookups
system.cpu1.branchPred.condPredicted 14236577 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 553412 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 17312116 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 12843593 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.branchPred.BTBHitPct 74.188464 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 6764103 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 29805 # Number of incorrect RAS predictions.
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.dtb.read_hits 14379922 # DTB read hits
system.cpu1.dtb.read_misses 49648 # DTB read misses
system.cpu1.dtb.write_hits 10687800 # DTB write hits
system.cpu1.dtb.write_misses 9435 # DTB write misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu1.dtb.flush_tlb 178 # Number of times complete TLB was flushed
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.dtb.flush_tlb_mva 444 # Number of times TLB was flushed by MVA
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 765 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 1285 # Number of TLB faults due to prefetch
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.dtb.perms_faults 532 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 14429570 # DTB read accesses
system.cpu1.dtb.write_accesses 10697235 # DTB write accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.dtb.hits 25067722 # DTB hits
system.cpu1.dtb.misses 59083 # DTB misses
system.cpu1.dtb.accesses 25126805 # DTB accesses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.itb.inst_hits 20653653 # ITB inst hits
system.cpu1.itb.inst_misses 7569 # ITB inst misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu1.itb.flush_tlb 178 # Number of times complete TLB was flushed
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.itb.flush_tlb_mva 444 # Number of times TLB was flushed by MVA
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.itb.flush_entries 2278 # Number of entries that have been flushed from TLB
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.itb.perms_faults 1323 # Number of TLB faults due to permissions restrictions
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.itb.inst_accesses 20661222 # ITB inst accesses
system.cpu1.itb.hits 20653653 # DTB hits
system.cpu1.itb.misses 7569 # DTB misses
system.cpu1.itb.accesses 20661222 # DTB accesses
system.cpu1.numCycles 107242523 # number of cpu cycles simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.fetch.icacheStallCycles 40712684 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 106782026 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 27353552 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 19607696 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 61803081 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 3231443 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 109598 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 4239 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles 431 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles 249521 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 135474 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 174 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 20651884 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 381778 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 3230 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 104630887 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.228118 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.325936 # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.fetch.rateDist::0 75276432 71.94% 71.94% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 3916697 3.74% 75.69% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 2503204 2.39% 78.08% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 8106458 7.75% 85.83% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 1592842 1.52% 87.35% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 1179592 1.13% 88.48% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 6154126 5.88% 94.36% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 1149786 1.10% 95.46% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 4751750 4.54% 100.00% # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.fetch.rateDist::total 104630887 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.255063 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.995706 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 27864157 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 57830739 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 15747454 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 1722658 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 1465635 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 1976909 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 152146 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 89229365 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 493204 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 1465635 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 28812184 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 6716141 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 45339545 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 16513270 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 5783839 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 85351560 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 2174 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 1570337 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 239520 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 3169707 # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands 88205068 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 393510505 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 95333289 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 6152 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 74299663 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 13905405 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 1590806 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 1489461 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 10064978 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 15196570 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 11856807 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 2179914 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 2787279 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 82067057 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 1161463 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 78685046 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 94868 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 10122036 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 25487135 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 106552 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 104630887 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.752025 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.430826 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.iq.issued_per_cycle::0 72948465 69.72% 69.72% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 10708543 10.23% 79.95% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 8057357 7.70% 87.66% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 6681907 6.39% 94.04% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 2500436 2.39% 96.43% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 1544614 1.48% 97.91% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 1464658 1.40% 99.31% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 495950 0.47% 99.78% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 228957 0.22% 100.00% # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.iq.issued_per_cycle::total 104630887 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.iq.fu_full::IntAlu 103296 8.95% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 5 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 535211 46.35% 55.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 516097 44.70% 100.00% # attempts to use FU when none available
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.iq.FU_type_0::No_OpClass 138 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 52538123 66.77% 66.77% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 58820 0.07% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 1 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 4114 0.01% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 14784683 18.79% 85.64% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 11299162 14.36% 100.00% # Type of FU issued
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.iq.FU_type_0::total 78685046 # Type of FU issued
system.cpu1.iq.rate 0.733711 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 1154609 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.014674 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 263236691 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 93395575 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 76291766 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 13765 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 7276 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 6039 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 79832108 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 7409 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 367192 # Number of loads that had data forwarded from stores
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.iew.lsq.thread0.squashedLoads 2204039 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 2671 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 53511 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 1150974 # Number of stores squashed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 193750 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 155367 # Number of times an access to memory failed due to the cache being blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.iew.iewSquashCycles 1465635 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 4317272 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 2160865 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 83369977 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 136369 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 15196570 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 11856807 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 585220 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 46964 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 2101356 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 53511 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 256264 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 221755 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 478019 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 78073190 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 14542904 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 552934 # Number of squashed instructions skipped in execute
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.iew.exec_nop 141457 # number of nop insts executed
system.cpu1.iew.exec_refs 25733696 # number of memory reference insts executed
system.cpu1.iew.exec_branches 14521478 # Number of branches executed
system.cpu1.iew.exec_stores 11190792 # Number of stores executed
system.cpu1.iew.exec_rate 0.728006 # Inst execution rate
system.cpu1.iew.wb_sent 77444186 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 76297805 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 39935797 # num instructions producing a value
system.cpu1.iew.wb_consumers 69997959 # num instructions consuming a value
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.iew.wb_rate 0.711451 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.570528 # average fanout of values written-back
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.commit.commitSquashedInsts 11451015 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 1054911 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 403289 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 102066180 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.704508 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.588054 # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.commit.committed_per_cycle::0 73979517 72.48% 72.48% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 12597540 12.34% 84.82% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 6450417 6.32% 91.14% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 2677104 2.62% 93.77% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 1410201 1.38% 95.15% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 931945 0.91% 96.06% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 1826334 1.79% 97.85% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 426802 0.42% 98.27% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 1766320 1.73% 100.00% # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.commit.committed_per_cycle::total 102066180 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 59233366 # Number of instructions committed
system.cpu1.commit.committedOps 71906393 # Number of ops (including micro ops) committed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.commit.refs 23698364 # Number of memory references committed
system.cpu1.commit.loads 12992531 # Number of loads committed
system.cpu1.commit.membars 441834 # Number of memory barriers committed
system.cpu1.commit.branches 13745002 # Number of branches committed
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu1.commit.fp_insts 5965 # Number of committed floating point instructions.
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.commit.int_insts 63017798 # Number of committed integer instructions.
system.cpu1.commit.function_calls 2684230 # Number of function calls committed.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.commit.op_class_0::IntAlu 48146836 66.96% 66.96% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 57080 0.08% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 4113 0.01% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 12992531 18.07% 85.11% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 10705833 14.89% 100.00% # Class of committed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.commit.op_class_0::total 71906393 # Class of committed instruction
system.cpu1.commit.bw_lim_events 1766320 # number cycles where commit BW limit reached
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.cpu1.rob.rob_reads 171177235 # The number of ROB reads
system.cpu1.rob.rob_writes 169283950 # The number of ROB writes
system.cpu1.timesIdled 392418 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 2611636 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 2951410112 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 59150362 # Number of Instructions Simulated
system.cpu1.committedOps 71823389 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 1.813049 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.813049 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.551557 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.551557 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 84951910 # number of integer regfile reads
system.cpu1.int_regfile_writes 48574213 # number of integer regfile writes
system.cpu1.fp_regfile_reads 16611 # number of floating regfile reads
system.cpu1.fp_regfile_writes 13102 # number of floating regfile writes
system.cpu1.cc_regfile_reads 275725718 # number of cc regfile reads
system.cpu1.cc_regfile_writes 28996859 # number of cc regfile writes
system.cpu1.misc_regfile_reads 192674093 # number of misc regfile reads
system.cpu1.misc_regfile_writes 799402 # number of misc regfile writes
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.tags.replacements 36423 # number of replacements
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.iocache.tags.tagsinuse 0.982061 # Cycle average of tags in use
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.tags.total_refs 16 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000439 # Average number of references to valid blocks.
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.iocache.tags.warmup_cycle 234012764000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 0.982061 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.061379 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.061379 # Average percentage of cache occupancy
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.iocache.tags.tag_accesses 328305 # Number of tag accesses
system.iocache.tags.data_accesses 328305 # Number of data accesses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses
system.iocache.ReadReq_misses::total 249 # number of ReadReq misses
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.iocache.WriteInvalidateReq_misses::realview.ide 8 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 8 # number of WriteInvalidateReq misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses
system.iocache.demand_misses::total 249 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 249 # number of overall misses
system.iocache.overall_misses::total 249 # number of overall misses
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.iocache.ReadReq_miss_latency::realview.ide 29662377 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 29662377 # number of ReadReq miss cycles
system.iocache.demand_miss_latency::realview.ide 29662377 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 29662377 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 29662377 # number of overall miss cycles
system.iocache.overall_miss_latency::total 29662377 # number of overall miss cycles
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.iocache.WriteInvalidateReq_accesses::realview.ide 36232 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 36232 # number of WriteInvalidateReq accesses(hits+misses)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000221 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 0.000221 # miss rate for WriteInvalidateReq accesses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 119126.012048 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 119126.012048 # average ReadReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 119126.012048 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 119126.012048 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 119126.012048 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 119126.012048 # average overall miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.fast_writes 36224 # number of fast writes performed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_mshr_misses::realview.ide 249 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 249 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.iocache.ReadReq_mshr_miss_latency::realview.ide 16713377 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 16713377 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2228741309 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2228741309 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 16713377 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 16713377 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 16713377 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 16713377 # number of overall MSHR miss cycles
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67121.995984 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 67121.995984 # average ReadReq mshr miss latency
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.iocache.demand_avg_mshr_miss_latency::realview.ide 67121.995984 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 67121.995984 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 67121.995984 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 67121.995984 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.kern.inst.quiesce 3039 # number of quiesce instructions executed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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