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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt

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tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
sim_seconds 2.548515 # Number of seconds simulated
sim_ticks 2548515380000 # Number of ticks simulated
final_tick 2548515380000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
host_inst_rate 61977 # Simulator instruction rate (inst/s)
host_op_rate 79748 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2618667230 # Simulator tick rate (ticks/s)
host_mem_usage 403588 # Number of bytes of host memory used
host_seconds 973.21 # Real time elapsed on the host
sim_insts 60316341 # Number of instructions simulated
sim_ops 77611368 # Number of ops (including micro ops) simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bytes_read::cpu0.dtb.walker 1216 # Number of bytes read from this memory
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bytes_read::cpu0.inst 440128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 4850064 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 360448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 4242200 # Number of bytes read from this memory
system.physmem.bytes_read::total 131005928 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 440128 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 360448 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 800576 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3785088 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 1679112 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 1336988 # Number of bytes written to this memory
system.physmem.bytes_written::total 6801188 # Number of bytes written to this memory
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.num_reads::cpu0.dtb.walker 19 # Number of read requests responded to by this memory
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.num_reads::cpu0.inst 6877 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 75816 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 5632 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 66290 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15293471 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 59142 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 419778 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 334247 # Number of write requests responded to by this memory
system.physmem.num_writes::total 813167 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47521992 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 477 # Total read bandwidth from this memory (bytes/s)
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bw_read::cpu0.inst 172700 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1903094 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 477 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 141435 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1664577 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51404802 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 172700 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 141435 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 314134 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1485213 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 658859 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 524614 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2668686 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1485213 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47521992 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 477 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bw_total::cpu0.inst 172700 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 2561953 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 477 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 141435 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 2189191 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54073488 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15293471 # Total number of read requests seen
system.physmem.writeReqs 813167 # Total number of write requests seen
system.physmem.cpureqs 218464 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 978782144 # Total number of bytes read from memory
system.physmem.bytesWritten 52042688 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 131005928 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 6801188 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 4709 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 955865 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 955532 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 955688 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 955892 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 955763 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 955998 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 955883 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 955786 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 956235 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 955940 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 955511 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 955116 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 956216 # Track reads on a per bank basis
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.perBankRdReqs::13 955973 # Track reads on a per bank basis
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.perBankRdReqs::14 956077 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 955981 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 49128 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 48906 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 50979 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 51091 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 51008 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 51270 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 51265 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 51204 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 51310 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 51097 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 50763 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 50416 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 51359 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 50976 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 51272 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 51123 # Track writes on a per bank basis
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.numWrRetry 32396 # Number of times wr buffer was full causing retry
system.physmem.totGap 2548513467000 # Total gap between requests
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.readPktSize::2 42 # Categorize read packet sizes
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.readPktSize::3 15138816 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.readPktSize::6 154613 # Categorize read packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.writePktSize::2 754025 # Categorize write packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.writePktSize::6 59142 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 1060849 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 987246 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 977477 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3738495 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2806386 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2806166 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2776833 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 15211 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 14905 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 28917 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 42926 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 28925 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 2287 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 2286 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 2959 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1551 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 20 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.wrQLenPdf::0 2759 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 2878 # What write queue length does an incoming req see
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.wrQLenPdf::2 2926 # What write queue length does an incoming req see
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.wrQLenPdf::3 2969 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 2964 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 2963 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 2962 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 2967 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 2971 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 35376 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 35363 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 35349 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 35330 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 35323 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 35316 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 35302 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 35293 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 35264 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 35252 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 35238 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 35229 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 35218 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 32746 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 32612 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 32550 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 32491 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 32482 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 32473 # What write queue length does an incoming req see
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.wrQLenPdf::29 32457 # What write queue length does an incoming req see
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.wrQLenPdf::30 32442 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 32421 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 40074 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 25722.964516 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 2062.503898 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 32877.713086 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-95 7020 17.52% 17.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-159 3450 8.61% 26.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-223 2302 5.74% 31.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-287 1762 4.40% 36.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-351 1221 3.05% 39.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-415 1083 2.70% 42.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-479 782 1.95% 43.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-543 826 2.06% 46.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-607 552 1.38% 47.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-671 527 1.32% 48.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-735 441 1.10% 49.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-799 399 1.00% 50.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-863 278 0.69% 51.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-927 274 0.68% 52.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-991 181 0.45% 52.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1055 260 0.65% 53.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1119 121 0.30% 53.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1183 146 0.36% 53.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1247 103 0.26% 54.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1311 108 0.27% 54.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1375 77 0.19% 54.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1439 372 0.93% 55.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1503 611 1.52% 57.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1567 461 1.15% 58.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1631 86 0.21% 58.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1695 174 0.43% 58.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1759 54 0.13% 59.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1823 96 0.24% 59.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1887 48 0.12% 59.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1951 68 0.17% 59.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-2015 31 0.08% 59.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2079 67 0.17% 59.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2143 19 0.05% 59.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2207 52 0.13% 60.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2271 17 0.04% 60.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2335 39 0.10% 60.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2399 17 0.04% 60.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2463 35 0.09% 60.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2527 6 0.01% 60.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2591 20 0.05% 60.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2655 5 0.01% 60.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2719 15 0.04% 60.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2783 12 0.03% 60.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2847 19 0.05% 60.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2911 10 0.02% 60.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2975 19 0.05% 60.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3039 6 0.01% 60.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3103 14 0.03% 60.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3167 5 0.01% 60.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3231 6 0.01% 60.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3295 5 0.01% 60.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3359 9 0.02% 60.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3423 3 0.01% 60.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3487 12 0.03% 60.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3551 4 0.01% 60.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3615 10 0.02% 60.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3679 3 0.01% 60.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3743 8 0.02% 60.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3807 7 0.02% 60.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3871 6 0.01% 60.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3935 1 0.00% 60.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3999 7 0.02% 60.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4063 5 0.01% 60.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4127 35 0.09% 60.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4191 5 0.01% 60.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4255 2 0.00% 60.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4319 3 0.01% 60.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4383 7 0.02% 60.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4447 4 0.01% 60.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4511 5 0.01% 60.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4575 1 0.00% 60.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4639 7 0.02% 61.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4703 1 0.00% 61.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4767 7 0.02% 61.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4895 3 0.01% 61.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4959 3 0.01% 61.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-5023 5 0.01% 61.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5151 4 0.01% 61.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5215 2 0.00% 61.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5279 2 0.00% 61.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5343 1 0.00% 61.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5407 5 0.01% 61.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5471 4 0.01% 61.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5535 5 0.01% 61.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5919 3 0.01% 61.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5983 1 0.00% 61.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6047 1 0.00% 61.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6111 2 0.00% 61.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6175 4 0.01% 61.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6303 3 0.01% 61.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6367 2 0.00% 61.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6495 5 0.01% 61.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6559 3 0.01% 61.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6623 4 0.01% 61.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6751 1 0.00% 61.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6815 21 0.05% 61.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6879 2 0.00% 61.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7071 4 0.01% 61.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7135 2 0.00% 61.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7199 3 0.01% 61.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7327 5 0.01% 61.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7391 2 0.00% 61.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7583 3 0.01% 61.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7647 1 0.00% 61.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7711 6 0.01% 61.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7775 1 0.00% 61.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7839 7 0.02% 61.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7903 3 0.01% 61.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7967 7 0.02% 61.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8031 1 0.00% 61.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8095 9 0.02% 61.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8159 3 0.01% 61.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8223 305 0.76% 62.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10112-10143 1 0.00% 62.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10271 17 0.04% 62.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13343 1 0.00% 62.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14111 1 0.00% 62.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14239 1 0.00% 62.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16704-16735 1 0.00% 62.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18432-18463 1 0.00% 62.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20992-21023 1 0.00% 62.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24768-24799 1 0.00% 62.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26112-26143 1 0.00% 62.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26624-26655 1 0.00% 62.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27904-27935 2 0.00% 62.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29440-29471 1 0.00% 62.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30208-30239 1 0.00% 62.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30400-30431 1 0.00% 62.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33823 5 0.01% 62.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34816-34847 1 0.00% 62.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35136-35167 1 0.00% 62.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37632-37663 1 0.00% 62.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39424-39455 1 0.00% 62.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43136-43167 1 0.00% 62.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45632-45663 1 0.00% 62.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51456-51487 1 0.00% 62.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::56832-56863 1 0.00% 62.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::58368-58399 1 0.00% 62.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::60864-60895 1 0.00% 62.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65536-65567 14763 36.84% 99.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::126336-126367 1 0.00% 99.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::130496-130527 1 0.00% 99.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::131008-131039 1 0.00% 99.10% # Bytes accessed per row activation
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytesPerActivate::131072-131103 346 0.86% 99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::132096-132127 4 0.01% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.98% # Bytes accessed per row activation
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bytesPerActivate::161792-161823 1 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::168960-168991 1 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::196352-196383 1 0.00% 99.99% # Bytes accessed per row activation
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytesPerActivate::196608-196639 4 0.01% 100.00% # Bytes accessed per row activation
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bytesPerActivate::total 40074 # Bytes accessed per row activation
system.physmem.totQLat 305431681500 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 397314004000 # Sum of mem lat for all requests
system.physmem.totBusLat 76467280000 # Total cycles spent in databus access
system.physmem.totBankLat 15415042500 # Total cycles spent in bank access
system.physmem.avgQLat 19971.40 # Average queueing delay per request
system.physmem.avgBankLat 1007.95 # Average bank access latency per request
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per request
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.avgMemAccLat 25979.35 # Average memory access latency
system.physmem.avgRdBW 384.06 # Average achieved read bandwidth in MB/s
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.avgWrBW 20.42 # Average achieved write bandwidth in MB/s
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.avgConsumedRdBW 51.40 # Average consumed read bandwidth in MB/s
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.avgConsumedWrBW 2.67 # Average consumed write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.busUtil 3.16 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.16 # Average read queue length over time
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.avgWrQLen 1.11 # Average write queue length over time
system.physmem.readRowHits 15267858 # Number of row buffer hits during reads
system.physmem.writeRowHits 798688 # Number of row buffer hits during writes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 98.22 # Row buffer hit rate for writes
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.avgGap 158227.53 # Average gap between requests
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.throughput 55014417 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 16346104 # Transaction distribution
system.membus.trans_dist::ReadResp 16346107 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.trans_dist::WriteReq 763348 # Transaction distribution
system.membus.trans_dist::WriteResp 763348 # Transaction distribution
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.trans_dist::Writeback 59142 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4707 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.trans_dist::UpgradeResp 4709 # Transaction distribution
system.membus.trans_dist::ReadExReq 131412 # Transaction distribution
system.membus.trans_dist::ReadExResp 131412 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution
system.membus.trans_dist::StoreCondReq 3 # Transaction distribution
system.membus.trans_dist::StoreCondResp 3 # Transaction distribution
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382954 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885920 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.pkt_count_system.l2c.mem_side::total 4272668 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.pkt_count::system.bridge.slave 2382954 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.pkt_count::system.physmem.port 32163552 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.pkt_count::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.pkt_count::total 34550300 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390325 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16696588 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.tot_pkt_size_system.l2c.mem_side::total 19094561 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.tot_pkt_size::system.bridge.slave 2390325 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.tot_pkt_size::system.physmem.port 137807116 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.tot_pkt_size::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.tot_pkt_size::total 140205089 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 140205089 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.reqLayer0.occupancy 1476111500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.reqLayer2.occupancy 17555240750 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer2.utilization 0.7 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.reqLayer3.occupancy 3581500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.respLayer1.occupancy 4707147287 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.respLayer2.occupancy 34172276993 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.tags.replacements 64386 # number of replacements
system.l2c.tags.tagsinuse 51442.070809 # Cycle average of tags in use
system.l2c.tags.total_refs 1905390 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 129776 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 14.682145 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 2511428822500 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 36972.715861 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 12.496871 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000368 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4611.296465 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 3332.598424 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 12.513991 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 3606.043873 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 2894.404957 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.564159 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000191 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.070363 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.050851 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000191 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.055024 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.044165 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.784944 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 33100 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 6967 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 497324 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 183110 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 30320 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 6628 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 474382 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 204508 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1436339 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 608377 # number of Writeback hits
system.l2c.Writeback_hits::total 608377 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 25 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 20 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 45 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 58192 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 54720 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 112912 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 33100 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 6967 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 497324 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 241302 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 30320 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 6628 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 474382 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 259228 # number of demand (read+write) hits
system.l2c.demand_hits::total 1549251 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 33100 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 6967 # number of overall hits
system.l2c.overall_hits::cpu0.inst 497324 # number of overall hits
system.l2c.overall_hits::cpu0.data 241302 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 30320 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 6628 # number of overall hits
system.l2c.overall_hits::cpu1.inst 474382 # number of overall hits
system.l2c.overall_hits::cpu1.data 259228 # number of overall hits
system.l2c.overall_hits::total 1549251 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 19 # number of ReadReq misses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_misses::cpu0.inst 6768 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 6113 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 19 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 5640 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 4604 # number of ReadReq misses
system.l2c.ReadReq_misses::total 23165 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 1534 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1392 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2926 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadExReq_misses::cpu0.data 70693 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 62500 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 133193 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 19 # number of demand (read+write) misses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_misses::cpu0.inst 6768 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 76806 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 19 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 5640 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 67104 # number of demand (read+write) misses
system.l2c.demand_misses::total 156358 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 19 # number of overall misses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_misses::cpu0.inst 6768 # number of overall misses
system.l2c.overall_misses::cpu0.data 76806 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 19 # number of overall misses
system.l2c.overall_misses::cpu1.inst 5640 # number of overall misses
system.l2c.overall_misses::cpu1.data 67104 # number of overall misses
system.l2c.overall_misses::total 156358 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2128750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 130250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 500312250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 448378498 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 2066250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 418450000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 353541000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1725006998 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 186492 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 256989 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 443481 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 22999 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 22999 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 4862001015 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 4300719454 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 9162720469 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 2128750 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 130250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 500312250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 5310379513 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 2066250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 418450000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 4654260454 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 10887727467 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 2128750 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 130250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 500312250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 5310379513 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 2066250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 418450000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 4654260454 # number of overall miss cycles
system.l2c.overall_miss_latency::total 10887727467 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 33119 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 6969 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 504092 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 189223 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 30339 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 6628 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 480022 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 209112 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1459504 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 608377 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 608377 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 1559 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1412 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 2971 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 7 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 6 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 128885 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 117220 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 246105 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 33119 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 6969 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 504092 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 318108 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 30339 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 6628 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 480022 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 326332 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1705609 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 33119 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 6969 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 504092 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 318108 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 30339 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 6628 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 480022 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 326332 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1705609 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000574 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000287 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.013426 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.032306 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000626 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.011749 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.022017 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.015872 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.983964 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.985836 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.984854 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.285714 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.153846 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.548497 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.533185 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.541204 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000574 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000287 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.013426 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.241446 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000626 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.011749 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.205631 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.091673 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000574 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000287 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.013426 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.241446 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000626 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.011749 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.205631 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.091673 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 112039.473684 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 65125 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73923.204787 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 73348.355636 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 108750 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74193.262411 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 76789.965248 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 74466.090999 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 121.572360 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 184.618534 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 151.565619 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 11499.500000 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 11499.500000 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68776.272262 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68811.511264 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 68792.807948 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 112039.473684 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 65125 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 73923.204787 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 69140.165000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 108750 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 74193.262411 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 69358.912345 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 69633.325234 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 112039.473684 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 65125 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 73923.204787 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 69140.165000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 108750 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 74193.262411 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 69358.912345 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 69633.325234 # average overall miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.writebacks::writebacks 59142 # number of writebacks
system.l2c.writebacks::total 59142 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst 6 # number of ReadReq MSHR hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_hits::cpu0.data 41 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_mshr_hits::cpu1.data 24 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_hits::cpu0.data 41 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_mshr_hits::cpu0.data 41 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 79 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 19 # number of ReadReq MSHR misses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_mshr_misses::cpu0.inst 6762 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 6072 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 19 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 5632 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 4580 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 23086 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 1534 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1392 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 2926 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 2 # number of SCUpgradeReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadExReq_mshr_misses::cpu0.data 70693 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 62500 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 133193 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 19 # number of demand (read+write) MSHR misses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_mshr_misses::cpu0.inst 6762 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 76765 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 19 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 5632 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 67080 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 156279 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 19 # number of overall MSHR misses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_mshr_misses::cpu0.inst 6762 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 76765 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 19 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 5632 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 67080 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 156279 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1889250 # number of ReadReq MSHR miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 105750 # number of ReadReq MSHR miss cycles
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 414261000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 369284748 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1823250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 346567500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 294016000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1427947498 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 15343534 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 13921392 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 29264926 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 20002 # number of SCUpgradeReq MSHR miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3965209485 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3507280046 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 7472489531 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1889250 # number of demand (read+write) MSHR miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 105750 # number of demand (read+write) MSHR miss cycles
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_mshr_miss_latency::cpu0.inst 414261000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 4334494233 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1823250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 346567500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 3801296046 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 8900437029 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1889250 # number of overall MSHR miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 105750 # number of overall MSHR miss cycles
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_mshr_miss_latency::cpu0.inst 414261000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 4334494233 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1823250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 346567500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 3801296046 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 8900437029 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6768250 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 82756804500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 84168652000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 166932224750 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 13405485754 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 10155458000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 23560943754 # number of WriteReq MSHR uncacheable cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 116250 # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 116250 # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 60000 # number of StoreCondReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::total 60000 # number of StoreCondReq MSHR uncacheable cycles
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6768250 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 96162290254 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 94324110000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 190493168504 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000287 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013414 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.032089 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011733 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.021902 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.015818 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.983964 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.985836 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.984854 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.285714 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.153846 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.548497 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.533185 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.541204 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000574 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000287 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013414 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.241317 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011733 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.205558 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.091627 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000574 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000287 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013414 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.241317 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011733 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.205558 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.091627 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 99434.210526 # average ReadReq mshr miss latency
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average ReadReq mshr miss latency
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 61263.087844 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60817.646245 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 95960.526316 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61535.422585 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64195.633188 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 61853.395911 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10002.303781 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.683527 # average UpgradeReq mshr miss latency
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56090.553308 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56116.480736 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 56102.719595 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 99434.210526 # average overall mshr miss latency
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61263.087844 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56464.459493 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 95960.526316 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61535.422585 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56668.098479 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 56952.226652 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 99434.210526 # average overall mshr miss latency
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61263.087844 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56464.459493 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 95960.526316 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61535.422585 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56668.098479 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 56952.226652 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.toL2Bus.throughput 58503668 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 2677420 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2677422 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.toL2Bus.trans_dist::Writeback 608377 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 2971 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 13 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 2984 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 246105 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 246105 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution
system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution
system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1969614 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 5798105 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 37248 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 149421 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count 7954388 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 62990656 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 85594465 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 54388 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 253832 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size 148893341 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 148893341 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 204156 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 4964785971 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.toL2Bus.respLayer0.occupancy 4437766959 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.toL2Bus.respLayer1.occupancy 4499076262 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.toL2Bus.respLayer2.occupancy 23705637 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.toL2Bus.respLayer3.occupancy 86451768 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.throughput 48459921 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 16322133 # Transaction distribution
system.iobus.trans_dist::ReadResp 16322133 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.trans_dist::WriteReq 8160 # Transaction distribution
system.iobus.trans_dist::WriteResp 8160 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.pkt_count_system.bridge.master::total 2382954 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.pkt_count::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.pkt_count::total 32660586 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.tot_pkt_size_system.bridge.master::total 2390325 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.tot_pkt_size::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.tot_pkt_size::total 123500853 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 123500853 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 521000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.respLayer0.occupancy 2374794000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.respLayer1.occupancy 41501177007 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.6 # Layer utilization (%)
system.cpu0.branchPred.lookups 7460849 # Number of BP lookups
system.cpu0.branchPred.condPredicted 5960235 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 378283 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 4914778 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 4045811 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.branchPred.BTBHitPct 82.319303 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 696591 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 38344 # Number of incorrect RAS predictions.
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.dtb.read_hits 25704058 # DTB read hits
system.cpu0.dtb.read_misses 39030 # DTB read misses
system.cpu0.dtb.write_hits 5997479 # DTB write hits
system.cpu0.dtb.write_misses 9591 # DTB write misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dtb.flush_tlb 258 # Number of times complete TLB was flushed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.dtb.flush_tlb_mva_asid 775 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 5605 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 1289 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 246 # Number of TLB faults due to prefetch
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.dtb.perms_faults 688 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 25743088 # DTB read accesses
system.cpu0.dtb.write_accesses 6007070 # DTB write accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.dtb.hits 31701537 # DTB hits
system.cpu0.dtb.misses 48621 # DTB misses
system.cpu0.dtb.accesses 31750158 # DTB accesses
system.cpu0.itb.inst_hits 6247488 # ITB inst hits
system.cpu0.itb.inst_misses 7199 # ITB inst misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.itb.flush_tlb 258 # Number of times complete TLB was flushed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.itb.flush_tlb_mva_asid 775 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2628 # Number of entries that have been flushed from TLB
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.itb.perms_faults 1719 # Number of TLB faults due to permissions restrictions
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.itb.inst_accesses 6254687 # ITB inst accesses
system.cpu0.itb.hits 6247488 # DTB hits
system.cpu0.itb.misses 7199 # DTB misses
system.cpu0.itb.accesses 6254687 # DTB accesses
system.cpu0.numCycles 237974378 # number of cpu cycles simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.fetch.icacheStallCycles 15699723 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 49234228 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 7460849 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 4742402 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 10819268 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 2791638 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 83518 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles 47679796 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 1230 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles 1910 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles 50382 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 1297285 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 371 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 6245426 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 421717 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 2971 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 77555768 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.784584 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.151481 # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.fetch.rateDist::0 66744115 86.06% 86.06% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 668305 0.86% 86.92% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 854486 1.10% 88.02% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 1301033 1.68% 89.70% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 1140084 1.47% 91.17% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 550475 0.71% 91.88% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 1373308 1.77% 93.65% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 375655 0.48% 94.14% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 4548307 5.86% 100.00% # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.fetch.rateDist::total 77555768 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.031351 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.206889 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 16771569 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 48649935 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 9795097 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 503008 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 1834030 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 1000504 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 90828 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 57451762 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 304997 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 1834030 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 17711945 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 19691518 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 25851696 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 9283653 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 3180864 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 54475085 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 7298 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 545691 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents 2120831 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents 197 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 56755313 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 249403500 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 249355386 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 48114 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 39528436 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 17226877 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 410327 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 362870 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 6606046 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 10343576 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 6897280 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1045135 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 1291149 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 49940914 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 982735 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 62750040 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 92397 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 11407526 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 29277622 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 263780 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 77555768 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.809096 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.520917 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.iq.issued_per_cycle::0 55086998 71.03% 71.03% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 6938242 8.95% 79.98% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 3598420 4.64% 84.61% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 3124608 4.03% 88.64% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 6233139 8.04% 96.68% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 1485765 1.92% 98.60% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 804564 1.04% 99.63% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 219887 0.28% 99.92% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 64145 0.08% 100.00% # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.iq.issued_per_cycle::total 77555768 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.iq.fu_full::IntAlu 31748 0.72% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 3 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.72% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 4146155 94.50% 95.22% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 209698 4.78% 100.00% # attempts to use FU when none available
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.iq.FU_type_0::No_OpClass 168420 0.27% 0.27% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 29819854 47.52% 47.79% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 48156 0.08% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 937 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.87% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 26415371 42.10% 89.96% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 6297270 10.04% 100.00% # Type of FU issued
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.iq.FU_type_0::total 62750040 # Type of FU issued
system.cpu0.iq.rate 0.263684 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 4387604 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.069922 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 207571986 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 62340159 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 43794455 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 12289 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 6579 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 5482 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 66962707 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 6517 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 317894 # Number of loads that had data forwarded from stores
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.iew.lsq.thread0.squashedLoads 2428904 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 3600 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 16156 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 921017 # Number of stores squashed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 16878789 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 486624 # Number of times an access to memory failed due to the cache being blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.iew.iewSquashCycles 1834030 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 15021196 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 239984 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 51041656 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 102587 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 10343576 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 6897280 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 695313 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 54984 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 10683 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 16156 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 184294 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 146657 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 330951 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 61443864 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 26034265 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 1306176 # Number of squashed instructions skipped in execute
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.iew.exec_nop 118007 # number of nop insts executed
system.cpu0.iew.exec_refs 32275135 # number of memory reference insts executed
system.cpu0.iew.exec_branches 5809455 # Number of branches executed
system.cpu0.iew.exec_stores 6240870 # Number of stores executed
system.cpu0.iew.exec_rate 0.258195 # Inst execution rate
system.cpu0.iew.wb_sent 60834498 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 43799937 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 23902926 # num instructions producing a value
system.cpu0.iew.wb_consumers 43468500 # num instructions consuming a value
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.iew.wb_rate 0.184053 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.549891 # average fanout of values written-back
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.commit.commitSquashedInsts 11258567 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 718955 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 288860 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 75721738 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.518964 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.500316 # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.commit.committed_per_cycle::0 61785849 81.60% 81.60% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 6716034 8.87% 90.47% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 2031673 2.68% 93.15% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 1100696 1.45% 94.60% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 996789 1.32% 95.92% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 567209 0.75% 96.67% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 697121 0.92% 97.59% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 401495 0.53% 98.12% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1424872 1.88% 100.00% # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.commit.committed_per_cycle::total 75721738 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 30484303 # Number of instructions committed
system.cpu0.commit.committedOps 39296836 # Number of ops (including micro ops) committed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.commit.refs 13890935 # Number of memory references committed
system.cpu0.commit.loads 7914672 # Number of loads committed
system.cpu0.commit.membars 201566 # Number of memory barriers committed
system.cpu0.commit.branches 4969836 # Number of branches committed
system.cpu0.commit.fp_insts 5449 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 34871152 # Number of committed integer instructions.
system.cpu0.commit.function_calls 489123 # Number of function calls committed.
system.cpu0.commit.bw_lim_events 1424872 # number cycles where commit BW limit reached
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.rob.rob_reads 123917155 # The number of ROB reads
system.cpu0.rob.rob_writes 103001078 # The number of ROB writes
system.cpu0.timesIdled 891630 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 160418610 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 2282332434 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 30404601 # Number of Instructions Simulated
system.cpu0.committedOps 39217134 # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total 30404601 # Number of Instructions Simulated
system.cpu0.cpi 7.826920 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 7.826920 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.127764 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.127764 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 278728087 # number of integer regfile reads
system.cpu0.int_regfile_writes 45052561 # number of integer regfile writes
system.cpu0.fp_regfile_reads 23012 # number of floating regfile reads
system.cpu0.fp_regfile_writes 19792 # number of floating regfile writes
system.cpu0.misc_regfile_reads 15437173 # number of misc regfile reads
system.cpu0.misc_regfile_writes 403324 # number of misc regfile writes
system.cpu0.icache.tags.replacements 984712 # number of replacements
system.cpu0.icache.tags.tagsinuse 510.392135 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 10916124 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 985224 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 11.079840 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 6946570250 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 153.798869 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 356.593266 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.300388 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.696471 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.996860 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 5698838 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 5217286 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 10916124 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 5698838 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 5217286 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 10916124 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 5698838 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 5217286 # number of overall hits
system.cpu0.icache.overall_hits::total 10916124 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 546469 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 520462 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1066931 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 546469 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 520462 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1066931 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 546469 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 520462 # number of overall misses
system.cpu0.icache.overall_misses::total 1066931 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7505000228 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7078718225 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 14583718453 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 7505000228 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 7078718225 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 14583718453 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 7505000228 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 7078718225 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 14583718453 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 6245307 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 5737748 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 11983055 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 6245307 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 5737748 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 11983055 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 6245307 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 5737748 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 11983055 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.087501 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.090708 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.089037 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.087501 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.090708 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.089037 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.087501 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.090708 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.089037 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13733.624831 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13600.835844 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13668.848738 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13733.624831 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13600.835844 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13668.848738 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13733.624831 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13600.835844 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13668.848738 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 8644 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 575 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 416 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.778846 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 575 # average number of cycles each access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41748 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39914 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 81662 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 41748 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst 39914 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 81662 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 41748 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst 39914 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 81662 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 504721 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 480548 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 985269 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 504721 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 480548 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 985269 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 504721 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 480548 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 985269 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6095694370 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5754767140 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 11850461510 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6095694370 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5754767140 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 11850461510 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6095694370 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5754767140 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 11850461510 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9176750 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9176750 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9176750 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 9176750 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.080816 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.083752 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.082222 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.080816 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.083752 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.082222 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.080816 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.083752 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.082222 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12077.354360 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11975.426263 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12027.640685 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12077.354360 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11975.426263 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12027.640685 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12077.354360 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11975.426263 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12027.640685 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.dcache.tags.replacements 643928 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.992040 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 21539454 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 644440 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 33.423521 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 49066250 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 194.023961 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 317.968079 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.378953 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.621031 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999984 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 7084507 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 6698400 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 13782907 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3631868 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 3629961 # number of WriteReq hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.WriteReq_hits::total 7261829 # number of WriteReq hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114762 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 129152 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 243914 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 116493 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 131183 # number of StoreCondReq hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.StoreCondReq_hits::total 247676 # number of StoreCondReq hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.dcache.demand_hits::cpu0.data 10716375 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 10328361 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 21044736 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 10716375 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 10328361 # number of overall hits
system.cpu0.dcache.overall_hits::total 21044736 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 339050 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 410986 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 750036 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1568875 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 1393123 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 2961998 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6956 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6622 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 13578 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 6 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 1907925 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 1804109 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 3712034 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1907925 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 1804109 # number of overall misses
system.cpu0.dcache.overall_misses::total 3712034 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5404290531 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6065987702 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 11470278233 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76728419243 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 66584790588 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 143313209831 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98583999 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 88165249 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 186749248 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 116502 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 78000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 194502 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 82132709774 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 72650778290 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 154783488064 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 82132709774 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 72650778290 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 154783488064 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7423557 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 7109386 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 14532943 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5200743 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 5023084 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 10223827 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 121718 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 135774 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 257492 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 116500 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 131189 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 247689 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 12624300 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 12132470 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 24756770 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 12624300 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 12132470 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 24756770 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.045672 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057809 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.051609 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.301664 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.277344 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.289715 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.057148 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.048772 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052732 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000060 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000046 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000052 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.151131 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.148701 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.149940 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.151131 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.148701 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.149940 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15939.509013 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14759.596925 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15292.970248 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48906.649187 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 47795.342255 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 48383.965766 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14172.512795 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13313.991090 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13753.811165 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16643.142857 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14961.692308 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43048.185738 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 40269.616908 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 41697.756018 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43048.185738 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 40269.616908 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 41697.756018 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 36942 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 23867 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 3499 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 298 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.557874 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 80.090604 # average number of cycles each access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.dcache.writebacks::writebacks 608377 # number of writebacks
system.cpu0.dcache.writebacks::total 608377 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 156045 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 207748 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 363793 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1438475 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1274543 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 2713018 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 694 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 696 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1390 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1594520 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 1482291 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 3076811 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1594520 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 1482291 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 3076811 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183005 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 203238 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 386243 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130400 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 118580 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 248980 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6262 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5926 # number of LoadLockedReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12188 # number of LoadLockedReq MSHR misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 6 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 313405 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 321818 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 635223 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 313405 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 321818 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 635223 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2537438499 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2706851142 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5244289641 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5705098821 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5073968451 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10779067272 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 78058501 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68010500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146069001 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 102498 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 66000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 168498 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8242537320 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7780819593 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 16023356913 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8242537320 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7780819593 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 16023356913 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 90382122001 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 91936686500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182318808501 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 18619452182 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 14311531070 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 32930983252 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 155750 # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 155750 # number of LoadLockedReq MSHR uncacheable cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 109001574183 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 106248217570 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215249791753 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024652 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028587 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026577 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025073 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023607 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.051447 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043646 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047334 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000060 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000046 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000052 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024826 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026525 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.025659 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.024826 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026525 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.025659 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13865.405311 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13318.627137 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13577.694977 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43750.757830 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42789.411798 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43292.904137 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12465.426541 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11476.628417 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11984.657122 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14642.571429 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12961.384615 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26299.954755 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24177.701661 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25224.774470 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26299.954755 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24177.701661 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25224.774470 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.branchPred.lookups 7195832 # Number of BP lookups
system.cpu1.branchPred.condPredicted 5758794 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 347995 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 4705708 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 3816103 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.branchPred.BTBHitPct 81.095193 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 703176 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 35899 # Number of incorrect RAS predictions.
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.dtb.read_hits 25676963 # DTB read hits
system.cpu1.dtb.read_misses 36626 # DTB read misses
system.cpu1.dtb.write_hits 5717501 # DTB write hits
system.cpu1.dtb.write_misses 9454 # DTB write misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dtb.flush_tlb 255 # Number of times complete TLB was flushed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.dtb.flush_tlb_mva_asid 664 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 5514 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 1965 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 245 # Number of TLB faults due to prefetch
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.dtb.perms_faults 578 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 25713589 # DTB read accesses
system.cpu1.dtb.write_accesses 5726955 # DTB write accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.dtb.hits 31394464 # DTB hits
system.cpu1.dtb.misses 46080 # DTB misses
system.cpu1.dtb.accesses 31440544 # DTB accesses
system.cpu1.itb.inst_hits 5739661 # ITB inst hits
system.cpu1.itb.inst_misses 6710 # ITB inst misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.itb.flush_tlb 255 # Number of times complete TLB was flushed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.itb.flush_tlb_mva_asid 664 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 2611 # Number of entries that have been flushed from TLB
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.itb.perms_faults 1312 # Number of TLB faults due to permissions restrictions
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.itb.inst_accesses 5746371 # ITB inst accesses
system.cpu1.itb.hits 5739661 # DTB hits
system.cpu1.itb.misses 6710 # DTB misses
system.cpu1.itb.accesses 5746371 # DTB accesses
system.cpu1.numCycles 238752144 # number of cpu cycles simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.fetch.icacheStallCycles 14725732 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 45766952 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 7195832 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 4519279 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 10135681 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 2420409 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 79807 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles 48403648 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 1533 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles 1933 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles 42395 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 1408034 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 243 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 5737749 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 344300 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 2901 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 76459821 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.743283 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.100006 # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.fetch.rateDist::0 66331645 86.75% 86.75% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 641052 0.84% 87.59% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 862069 1.13% 88.72% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 1143637 1.50% 90.22% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 1042629 1.36% 91.58% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 566145 0.74% 92.32% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 1286339 1.68% 94.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 374523 0.49% 94.49% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 4211782 5.51% 100.00% # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.fetch.rateDist::total 76459821 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.030139 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.191692 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 15725454 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 49459208 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 9192415 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 503929 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 1576672 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 971007 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 86673 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 53874532 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 286668 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 1576672 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 16583861 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 19404823 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 27005764 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 8762969 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 3123666 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 51462507 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 13354 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 564319 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents 2029977 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents 529 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 53559967 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 234998901 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 234956394 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 42507 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 38873752 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 14686214 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 422468 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 375757 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 6418869 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 9803560 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 6552959 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 903342 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 1157992 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 47368560 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 1003626 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 61323847 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 88809 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 9695135 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 24547753 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 239591 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 76459821 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.802040 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.511450 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.iq.issued_per_cycle::0 54334795 71.06% 71.06% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 6963817 9.11% 80.17% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 3541064 4.63% 84.80% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 3011943 3.94% 88.74% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 6202034 8.11% 96.85% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 1339759 1.75% 98.61% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 792493 1.04% 99.64% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 211144 0.28% 99.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 62772 0.08% 100.00% # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.iq.issued_per_cycle::total 76459821 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.iq.fu_full::IntAlu 28001 0.63% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 3 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 4231917 94.82% 95.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 203383 4.56% 100.00% # attempts to use FU when none available
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.iq.FU_type_0::No_OpClass 195246 0.32% 0.32% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 28699765 46.80% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 45365 0.07% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 6 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 1174 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.19% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 26341683 42.96% 90.15% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 6040595 9.85% 100.00% # Type of FU issued
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.iq.FU_type_0::total 61323847 # Type of FU issued
system.cpu1.iq.rate 0.256852 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 4463304 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.072783 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 203694277 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 58075857 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 42386346 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 11257 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 5873 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 4814 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 65585843 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 6062 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 307143 # Number of loads that had data forwarded from stores
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.iew.lsq.thread0.squashedLoads 2060794 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 3248 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 14926 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 795522 # Number of stores squashed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 17225652 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 391932 # Number of times an access to memory failed due to the cache being blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.iew.iewSquashCycles 1576672 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 14666749 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 228879 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 48476685 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 98660 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 9803560 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 6552959 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 716609 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 50437 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 9701 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 14926 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 170356 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 133051 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 303407 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 60276255 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 26034557 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 1047592 # Number of squashed instructions skipped in execute
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.iew.exec_nop 104499 # number of nop insts executed
system.cpu1.iew.exec_refs 32021114 # number of memory reference insts executed
system.cpu1.iew.exec_branches 5717498 # Number of branches executed
system.cpu1.iew.exec_stores 5986557 # Number of stores executed
system.cpu1.iew.exec_rate 0.252464 # Inst execution rate
system.cpu1.iew.wb_sent 59765334 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 42391160 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 23307297 # num instructions producing a value
system.cpu1.iew.wb_consumers 43055480 # num instructions consuming a value
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.iew.wb_rate 0.177553 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.541332 # average fanout of values written-back
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.commit.commitSquashedInsts 9596314 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 764035 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 262671 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 74883149 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.513666 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.490214 # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.commit.committed_per_cycle::0 61098286 81.59% 81.59% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 6805438 9.09% 90.68% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 1903916 2.54% 93.22% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 1064936 1.42% 94.64% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 1018174 1.36% 96.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 531111 0.71% 96.71% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 691593 0.92% 97.64% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 378534 0.51% 98.14% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 1391161 1.86% 100.00% # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.commit.committed_per_cycle::total 74883149 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 29982419 # Number of instructions committed
system.cpu1.commit.committedOps 38464913 # Number of ops (including micro ops) committed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.commit.refs 13500203 # Number of memory references committed
system.cpu1.commit.loads 7742766 # Number of loads committed
system.cpu1.commit.membars 202217 # Number of memory barriers committed
system.cpu1.commit.branches 4992962 # Number of branches committed
system.cpu1.commit.fp_insts 4763 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 33994528 # Number of committed integer instructions.
system.cpu1.commit.function_calls 502375 # Number of function calls committed.
system.cpu1.commit.bw_lim_events 1391161 # number cycles where commit BW limit reached
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.rob.rob_reads 120638730 # The number of ROB reads
system.cpu1.rob.rob_writes 97745041 # The number of ROB writes
system.cpu1.timesIdled 886317 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 162292323 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 2286407630 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 29911740 # Number of Instructions Simulated
system.cpu1.committedOps 38394234 # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total 29911740 # Number of Instructions Simulated
system.cpu1.cpi 7.981888 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 7.981888 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.125284 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.125284 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 272364887 # number of integer regfile reads
system.cpu1.int_regfile_writes 43577017 # number of integer regfile writes
system.cpu1.fp_regfile_reads 22187 # number of floating regfile reads
system.cpu1.fp_regfile_writes 19914 # number of floating regfile writes
system.cpu1.misc_regfile_reads 14848508 # number of misc regfile reads
system.cpu1.misc_regfile_writes 429527 # number of misc regfile writes
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1453044953007 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1453044953007 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1453044953007 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1453044953007 # number of overall MSHR uncacheable cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.kern.inst.quiesce 83067 # number of quiesce instructions executed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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