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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt

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tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
---------- Begin Simulation Statistics ----------
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
sim_seconds 2.548576 # Number of seconds simulated
sim_ticks 2548576209000 # Number of ticks simulated
final_tick 2548576209000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
test: update stats Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses.
2013-10-16 16:44:12 +02:00
host_inst_rate 64501 # Simulator instruction rate (inst/s)
host_op_rate 82996 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2725389479 # Simulator tick rate (ticks/s)
host_mem_usage 403492 # Number of bytes of host memory used
host_seconds 935.12 # Real time elapsed on the host
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
sim_insts 60316464 # Number of instructions simulated
sim_ops 77611603 # Number of ops (including micro ops) simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.bytes_read::cpu0.inst 483776 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 5166800 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 315264 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 3924504 # Number of bytes read from this memory
system.physmem.bytes_read::total 131003560 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 483776 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 315264 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 799040 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3783488 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 1522020 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 1494080 # Number of bytes written to this memory
system.physmem.bytes_written::total 6799588 # Number of bytes written to this memory
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.num_reads::cpu0.inst 7559 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 80765 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 4926 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 61326 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15293434 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 59117 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 380505 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 373520 # Number of write requests responded to by this memory
system.physmem.num_writes::total 813142 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47520858 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 728 # Total read bandwidth from this memory (bytes/s)
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.bw_read::cpu0.inst 189822 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 2027328 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 276 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 123702 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1539881 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51402646 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 189822 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 123702 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 313524 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1484550 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 597204 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 586241 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2667995 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1484550 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47520858 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 728 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.bw_total::cpu0.inst 189822 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 2624532 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 276 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 123702 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 2126122 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54070641 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15293434 # Total number of read requests accepted by DRAM controller
system.physmem.writeReqs 813142 # Total number of write requests accepted by DRAM controller
system.physmem.readBursts 15293434 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
system.physmem.writeBursts 813142 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead 978779776 # Total number of bytes read from memory
system.physmem.bytesWritten 52041088 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 131003560 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 6799588 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 13 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 4677 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 955864 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 955534 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 955684 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 955879 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 955769 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 955991 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 955868 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 955778 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 956236 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 955947 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 955508 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 955111 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 956226 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 955972 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 956075 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 955979 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 6690 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 6478 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 6630 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 6656 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 6589 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 6842 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 6835 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 6779 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 7114 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 6901 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 6563 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 6214 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 7157 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 6772 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 7070 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 6922 # Track writes on a per bank basis
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 2548575024500 # Total gap between requests
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.readPktSize::2 42 # Categorize read packet sizes
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.readPktSize::3 15138816 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.readPktSize::6 154576 # Categorize read packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.writePktSize::2 754025 # Categorize write packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.writePktSize::6 59117 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 1061686 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 987876 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 978214 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3738072 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2813374 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2806969 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2769477 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 15679 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 15363 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 29321 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 43265 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 29260 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1251 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1231 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1193 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1171 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.wrQLenPdf::0 4852 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 4837 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 4821 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 4810 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 4801 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 4788 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 4772 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 4751 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 4740 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 4724 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 4714 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 4703 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 4692 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 4682 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 4668 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 4650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 4625 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4617 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4608 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4598 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4589 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4583 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4575 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 39284 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 25091.701456 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 2070.748672 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 31471.829892 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-79 6644 16.91% 16.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-143 3436 8.75% 25.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-207 2300 5.85% 31.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-271 1832 4.66% 36.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-335 1227 3.12% 39.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-399 1105 2.81% 42.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-463 800 2.04% 44.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-527 812 2.07% 46.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-591 554 1.41% 47.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-655 516 1.31% 48.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-719 427 1.09% 50.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-783 432 1.10% 51.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-847 277 0.71% 51.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-911 299 0.76% 52.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-975 172 0.44% 53.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1039 211 0.54% 53.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1103 136 0.35% 53.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1167 132 0.34% 54.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1231 101 0.26% 54.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1295 106 0.27% 54.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1359 70 0.18% 54.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1423 391 1.00% 55.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1487 264 0.67% 56.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1551 450 1.15% 57.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1615 85 0.22% 57.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1679 167 0.43% 58.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1743 56 0.14% 58.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1807 95 0.24% 58.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1871 44 0.11% 58.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1935 79 0.20% 59.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1999 30 0.08% 59.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2063 69 0.18% 59.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2127 18 0.05% 59.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2191 44 0.11% 59.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2255 15 0.04% 59.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2319 32 0.08% 59.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2383 17 0.04% 59.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2447 19 0.05% 59.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2511 8 0.02% 59.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2575 26 0.07% 59.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2639 6 0.02% 59.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2703 18 0.05% 59.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2767 15 0.04% 59.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2831 16 0.04% 59.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2895 7 0.02% 59.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2959 13 0.03% 60.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3023 4 0.01% 60.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3087 18 0.05% 60.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3151 6 0.02% 60.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3215 6 0.02% 60.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3279 6 0.02% 60.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3343 11 0.03% 60.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3407 5 0.01% 60.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3471 8 0.02% 60.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3535 5 0.01% 60.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3599 6 0.02% 60.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3663 4 0.01% 60.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3727 10 0.03% 60.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3791 5 0.01% 60.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3855 3 0.01% 60.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3919 1 0.00% 60.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3983 13 0.03% 60.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4047 4 0.01% 60.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4111 32 0.08% 60.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4175 5 0.01% 60.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4239 4 0.01% 60.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4303 3 0.01% 60.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4367 6 0.02% 60.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4431 4 0.01% 60.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4495 5 0.01% 60.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4559 4 0.01% 60.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4623 6 0.02% 60.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4687 3 0.01% 60.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4751 4 0.01% 60.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4879 4 0.01% 60.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4943 2 0.01% 60.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-5007 7 0.02% 60.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5135 8 0.02% 60.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5199 2 0.01% 60.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5263 2 0.01% 60.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5327 1 0.00% 60.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5391 3 0.01% 60.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5455 3 0.01% 60.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5519 4 0.01% 60.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5583 1 0.00% 60.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5647 2 0.01% 60.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5711 1 0.00% 60.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5775 2 0.01% 60.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5903 2 0.01% 60.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6095 1 0.00% 60.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6159 6 0.02% 60.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6223 3 0.01% 60.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6287 2 0.01% 60.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6351 1 0.00% 60.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6415 3 0.01% 60.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6479 2 0.01% 60.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6543 3 0.01% 60.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6607 1 0.00% 60.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6735 1 0.00% 60.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6799 20 0.05% 60.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6863 3 0.01% 60.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7055 3 0.01% 60.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7119 2 0.01% 60.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7311 3 0.01% 60.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7375 2 0.01% 60.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7439 4 0.01% 60.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7567 9 0.02% 60.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7631 1 0.00% 60.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7695 7 0.02% 60.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7823 3 0.01% 60.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7887 4 0.01% 60.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7951 2 0.01% 60.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8079 11 0.03% 60.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8143 1 0.00% 60.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8207 311 0.79% 61.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8463 63 0.16% 61.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8512-8527 194 0.49% 62.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8576-8591 13 0.03% 62.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8768-8783 3 0.01% 62.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8832-8847 2 0.01% 62.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20480-20495 1 0.00% 62.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23680-23695 1 0.00% 62.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25600-25615 2 0.01% 62.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28352-28367 1 0.00% 62.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28416-28431 1 0.00% 62.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32192-32207 1 0.00% 62.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33344-33359 1 0.00% 62.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33664-33679 2 0.01% 62.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33807 2 0.01% 62.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34560-34575 1 0.00% 62.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37184-37199 1 0.00% 62.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39488-39503 1 0.00% 62.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45056-45071 1 0.00% 62.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::58112-58127 1 0.00% 62.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::64768-64783 1 0.00% 62.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65536-65551 14685 37.38% 99.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::68736-68751 1 0.00% 99.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::73920-73935 9 0.02% 99.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::73984-73999 43 0.11% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::74048-74063 33 0.08% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::74112-74127 3 0.01% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 39284 # Bytes accessed per row activation
system.physmem.totQLat 294283871250 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 386089225000 # Sum of mem lat for all requests
system.physmem.totBusLat 76467105000 # Total cycles spent in databus access
system.physmem.totBankLat 15338248750 # Total cycles spent in bank access
system.physmem.avgQLat 19242.51 # Average queueing delay per request
system.physmem.avgBankLat 1002.93 # Average bank access latency per request
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per request
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.avgMemAccLat 25245.45 # Average memory access latency
system.physmem.avgRdBW 384.05 # Average achieved read bandwidth in MB/s
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.avgWrBW 20.42 # Average achieved write bandwidth in MB/s
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.avgConsumedRdBW 51.40 # Average consumed read bandwidth in MB/s
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.avgConsumedWrBW 2.67 # Average consumed write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.busUtil 3.16 # Data bus utilization in percentage
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.avgRdQLen 0.15 # Average read queue length over time
system.physmem.avgWrQLen 1.08 # Average write queue length over time
system.physmem.readRowHits 15268174 # Number of row buffer hits during reads
system.physmem.writeRowHits 94166 # Number of row buffer hits during writes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.writeRowHitRate 11.58 # Row buffer hit rate for writes
system.physmem.avgGap 158231.96 # Average gap between requests
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.throughput 55011549 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 16346066 # Transaction distribution
system.membus.trans_dist::ReadResp 16346069 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.trans_dist::WriteReq 763348 # Transaction distribution
system.membus.trans_dist::WriteResp 763348 # Transaction distribution
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.trans_dist::Writeback 59117 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4675 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.trans_dist::UpgradeResp 4677 # Transaction distribution
system.membus.trans_dist::ReadExReq 131414 # Transaction distribution
system.membus.trans_dist::ReadExResp 131414 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution
system.membus.trans_dist::StoreCondReq 3 # Transaction distribution
system.membus.trans_dist::StoreCondResp 3 # Transaction distribution
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382956 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885757 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4272507 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.pkt_count::total 34550139 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390329 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16692620 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 19090597 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.tot_pkt_size::total 140201125 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 140201125 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.reqLayer0.occupancy 1475672000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.reqLayer2.occupancy 3615000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer6.occupancy 17572541000 # Layer occupancy (ticks)
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
system.membus.respLayer1.occupancy 4757385335 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.respLayer2.occupancy 34173123993 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.tags.replacements 64349 # number of replacements
system.l2c.tags.tagsinuse 51432.213982 # Cycle average of tags in use
system.l2c.tags.total_refs 1904557 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 129741 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 14.679685 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 2511462555500 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 36971.376669 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 19.336615 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000368 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4863.234399 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 3340.353025 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.819885 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 3340.869034 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 2888.223986 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.564138 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000295 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.074207 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.050970 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000135 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.050978 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.044071 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.784793 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 31056 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 6811 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 489944 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 180708 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 32283 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 7013 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 480968 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 206794 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1435577 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 608201 # number of Writeback hits
system.l2c.Writeback_hits::total 608201 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 22 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 40 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 56719 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 56246 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 112965 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 31056 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 6811 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 489944 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 237427 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 32283 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 7013 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 480968 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 263040 # number of demand (read+write) hits
system.l2c.demand_hits::total 1548542 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 31056 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 6811 # number of overall hits
system.l2c.overall_hits::cpu0.inst 489944 # number of overall hits
system.l2c.overall_hits::cpu0.data 237427 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 32283 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 7013 # number of overall hits
system.l2c.overall_hits::cpu1.inst 480968 # number of overall hits
system.l2c.overall_hits::cpu1.data 263040 # number of overall hits
system.l2c.overall_hits::total 1548542 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 29 # number of ReadReq misses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.ReadReq_misses::cpu0.inst 7450 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 6327 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 4932 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 4374 # number of ReadReq misses
system.l2c.ReadReq_misses::total 23125 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 1313 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1598 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2911 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.ReadExReq_misses::cpu0.data 75216 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 57962 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 133178 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 29 # number of demand (read+write) misses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.demand_misses::cpu0.inst 7450 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 81543 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 4932 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 62336 # number of demand (read+write) misses
system.l2c.demand_misses::total 156303 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 29 # number of overall misses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.overall_misses::cpu0.inst 7450 # number of overall misses
system.l2c.overall_misses::cpu0.data 81543 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses
system.l2c.overall_misses::cpu1.inst 4932 # number of overall misses
system.l2c.overall_misses::cpu1.data 62336 # number of overall misses
system.l2c.overall_misses::total 156303 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2773750 # number of ReadReq miss cycles
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 130250 # number of ReadReq miss cycles
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.ReadReq_miss_latency::cpu0.inst 535863000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 458241999 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1150250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 375877250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 330560248 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1704596747 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 185492 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 279988 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 465480 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 5248575225 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 3913924011 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 9162499236 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 2773750 # number of demand (read+write) miss cycles
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_miss_latency::cpu0.itb.walker 130250 # number of demand (read+write) miss cycles
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.demand_miss_latency::cpu0.inst 535863000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 5706817224 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 1150250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 375877250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 4244484259 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 10867095983 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 2773750 # number of overall miss cycles
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_miss_latency::cpu0.itb.walker 130250 # number of overall miss cycles
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.overall_miss_latency::cpu0.inst 535863000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 5706817224 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 1150250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 375877250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 4244484259 # number of overall miss cycles
system.l2c.overall_miss_latency::total 10867095983 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 31085 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 6813 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 497394 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 187035 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 32294 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 7013 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 485900 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 211168 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1458702 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 608201 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 608201 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 1331 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1620 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 2951 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 8 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 10 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 131935 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 114208 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 246143 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 31085 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 6813 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 497394 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 318970 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 32294 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 7013 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 485900 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 325376 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1704845 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 31085 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 6813 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 497394 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 318970 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 32294 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 7013 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 485900 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 325376 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1704845 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000933 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000294 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.014978 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.033828 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000341 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.010150 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.020713 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.015853 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.986476 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.986420 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.986445 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.250000 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.200000 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.570099 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.507513 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.541059 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000933 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000294 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.014978 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.255645 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000341 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.010150 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.191581 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.091682 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000933 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000294 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.014978 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.255645 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000341 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.010150 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.191581 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.091682 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 95646.551724 # average ReadReq miss latency
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 65125 # average ReadReq miss latency
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71927.919463 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 72426.426268 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 104568.181818 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76211.932279 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 75573.902149 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 73712.291762 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 141.273420 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 175.211514 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 159.903813 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69780.036495 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 67525.689434 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 68798.894983 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 95646.551724 # average overall miss latency
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 65125 # average overall miss latency
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.demand_avg_miss_latency::cpu0.inst 71927.919463 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 69985.372429 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 104568.181818 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 76211.932279 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 68090.417399 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 69525.831129 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 95646.551724 # average overall miss latency
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 65125 # average overall miss latency
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.overall_avg_miss_latency::cpu0.inst 71927.919463 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 69985.372429 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 104568.181818 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 76211.932279 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 68090.417399 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 69525.831129 # average overall miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.writebacks::writebacks 59117 # number of writebacks
system.l2c.writebacks::total 59117 # number of writebacks
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_mshr_hits::cpu0.inst 6 # number of ReadReq MSHR hits
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.ReadReq_mshr_hits::cpu0.data 39 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data 27 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.demand_mshr_hits::cpu0.data 39 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data 27 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 78 # number of demand (read+write) MSHR hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.overall_mshr_hits::cpu0.data 39 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data 27 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 78 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 29 # number of ReadReq MSHR misses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.ReadReq_mshr_misses::cpu0.inst 7444 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 6288 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 4926 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 4347 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 23047 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 1313 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1598 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 2911 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 2 # number of SCUpgradeReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.ReadExReq_mshr_misses::cpu0.data 75216 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 57962 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 133178 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 29 # number of demand (read+write) MSHR misses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.demand_mshr_misses::cpu0.inst 7444 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 81504 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 4926 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 62309 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 156225 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 29 # number of overall MSHR misses
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.overall_mshr_misses::cpu0.inst 7444 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 81504 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 4926 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 62309 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 156225 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2403250 # number of ReadReq MSHR miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 105750 # number of ReadReq MSHR miss cycles
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 440932000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 376527749 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1009250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 313110000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 273532998 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1407620997 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13131313 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15986098 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 29117411 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 20002 # number of SCUpgradeReq MSHR miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4295181775 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3176975989 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 7472157764 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2403250 # number of demand (read+write) MSHR miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 105750 # number of demand (read+write) MSHR miss cycles
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.demand_mshr_miss_latency::cpu0.inst 440932000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 4671709524 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1009250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 313110000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 3450508987 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 8879778761 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2403250 # number of overall MSHR miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 105750 # number of overall MSHR miss cycles
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.overall_mshr_miss_latency::cpu0.inst 440932000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 4671709524 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1009250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 313110000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 3450508987 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 8879778761 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6023999 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84465244500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82459599500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 166930867999 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8917288738 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8449538500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 17366827238 # number of WriteReq MSHR uncacheable cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 116250 # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 116250 # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 60000 # number of StoreCondReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::total 60000 # number of StoreCondReq MSHR uncacheable cycles
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6023999 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 93382533238 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 90909138000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 184297695237 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000933 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000294 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014966 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.033619 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000341 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010138 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020586 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.015800 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.986476 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.986420 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.986445 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.250000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.570099 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.507513 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.541059 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000933 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000294 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014966 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.255522 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000341 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010138 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.191498 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.091636 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000933 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000294 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014966 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.255522 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000341 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010138 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.191498 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.091636 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 82870.689655 # average ReadReq mshr miss latency
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average ReadReq mshr miss latency
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59233.207953 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 59880.367207 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 91750 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63562.728380 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62924.545204 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 61076.105220 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.816020 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.545861 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57104.629002 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 54811.358977 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 56106.547358 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 82870.689655 # average overall mshr miss latency
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59233.207953 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57318.776060 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 91750 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63562.728380 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55377.377056 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 56839.678419 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 82870.689655 # average overall mshr miss latency
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59233.207953 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57318.776060 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 91750 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63562.728380 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55377.377056 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 56839.678419 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.toL2Bus.throughput 58475740 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 2676749 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2676751 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.toL2Bus.trans_dist::Writeback 608201 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 2951 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 2961 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 246143 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 246143 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution
system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution
system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967991 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5797697 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37845 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149237 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 7952770 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62938176 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85577189 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55304 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 253516 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total 148824185 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 148824185 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 205696 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 4963674463 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.toL2Bus.respLayer0.occupancy 4434137240 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.toL2Bus.respLayer1.occupancy 4494378467 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.toL2Bus.respLayer2.occupancy 24064152 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.toL2Bus.respLayer3.occupancy 86310594 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.throughput 48458766 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 16322134 # Transaction distribution
system.iobus.trans_dist::ReadResp 16322134 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.trans_dist::WriteReq 8160 # Transaction distribution
system.iobus.trans_dist::WriteResp 8160 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.pkt_count_system.bridge.master::total 2382956 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.pkt_count::total 32660588 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.tot_pkt_size_system.bridge.master::total 2390329 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.tot_pkt_size::total 123500857 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 123500857 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.reqLayer1.occupancy 3974000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 521000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.respLayer0.occupancy 2374796000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.respLayer1.occupancy 41501700007 # Layer occupancy (ticks)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.respLayer1.utilization 1.6 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.branchPred.lookups 7055231 # Number of BP lookups
system.cpu0.branchPred.condPredicted 5603867 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 360036 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 4627391 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 3766189 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.branchPred.BTBHitPct 81.389038 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 696378 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 37374 # Number of incorrect RAS predictions.
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.dtb.read_hits 25604020 # DTB read hits
system.cpu0.dtb.read_misses 37101 # DTB read misses
system.cpu0.dtb.write_hits 6019786 # DTB write hits
system.cpu0.dtb.write_misses 10089 # DTB write misses
system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.dtb.flush_tlb_mva_asid 658 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 5563 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 1360 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 245 # Number of TLB faults due to prefetch
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.dtb.perms_faults 609 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 25641121 # DTB read accesses
system.cpu0.dtb.write_accesses 6029875 # DTB write accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.dtb.hits 31623806 # DTB hits
system.cpu0.dtb.misses 47190 # DTB misses
system.cpu0.dtb.accesses 31670996 # DTB accesses
system.cpu0.itb.inst_hits 5711817 # ITB inst hits
system.cpu0.itb.inst_misses 6786 # ITB inst misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.itb.flush_tlb_mva_asid 658 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2595 # Number of entries that have been flushed from TLB
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.itb.perms_faults 1280 # Number of TLB faults due to permissions restrictions
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.itb.inst_accesses 5718603 # ITB inst accesses
system.cpu0.itb.hits 5711817 # DTB hits
system.cpu0.itb.misses 6786 # DTB misses
system.cpu0.itb.accesses 5718603 # DTB accesses
system.cpu0.numCycles 240384739 # number of cpu cycles simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.fetch.icacheStallCycles 15036708 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 44324460 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 7055231 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 4462567 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 9979880 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 2348952 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 79920 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles 48371030 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 1557 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles 1896 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles 40136 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 1395788 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 332 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 5710035 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 358939 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 3057 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 76524952 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.728839 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.080650 # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.fetch.rateDist::0 66552751 86.97% 86.97% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 648002 0.85% 87.82% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 843291 1.10% 88.92% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 1146450 1.50% 90.42% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 1051496 1.37% 91.79% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 533927 0.70% 92.49% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 1248962 1.63% 94.12% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 369566 0.48% 94.60% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 4130507 5.40% 100.00% # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.fetch.rateDist::total 76524952 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.029350 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.184390 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 15988793 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 49427885 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 9067900 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 506950 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 1531254 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 959604 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 89006 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 53104636 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 296594 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 1531254 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 16866391 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 20063365 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 26274348 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 8616750 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 3170765 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 50610961 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 7411 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 529520 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents 2115247 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents 208 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 52034450 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 231667374 # Number of register rename lookups that rename has made
test: update stats Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses.
2013-10-16 16:44:12 +02:00
system.cpu0.rename.int_rename_lookups 214169305 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 4937 # Number of floating rename lookups
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.rename.CommittedMaps 38251156 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 13783293 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 411980 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 362796 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 6588533 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 9723453 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 6830710 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1010499 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 1245426 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 47056287 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 968125 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 61041577 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 84130 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 9522170 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 23883479 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 244384 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 76524952 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.797669 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.517362 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.iq.issued_per_cycle::0 54759555 71.56% 71.56% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 6733047 8.80% 80.36% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 3420180 4.47% 84.83% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 2920085 3.82% 88.64% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 6164290 8.06% 96.70% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 1467950 1.92% 98.62% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 772657 1.01% 99.62% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 222441 0.29% 99.92% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 64747 0.08% 100.00% # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.iq.issued_per_cycle::total 76524952 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.iq.fu_full::IntAlu 27542 0.62% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 4220431 94.60% 95.22% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 213140 4.78% 100.00% # attempts to use FU when none available
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.iq.FU_type_0::No_OpClass 171568 0.28% 0.28% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 28242983 46.27% 46.55% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 47431 0.08% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 1218 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.63% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 26256845 43.01% 89.64% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 6321515 10.36% 100.00% # Type of FU issued
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.iq.FU_type_0::total 61041577 # Type of FU issued
system.cpu0.iq.rate 0.253933 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 4461113 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.073083 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 203189112 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 57554843 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 42164489 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 11244 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 5997 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 4944 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 65325122 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 6000 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 306679 # Number of loads that had data forwarded from stores
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.iew.lsq.thread0.squashedLoads 2052481 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 3874 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 14810 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 826086 # Number of stores squashed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 17207144 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 348104 # Number of times an access to memory failed due to the cache being blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.iew.iewSquashCycles 1531254 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 15306015 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 241273 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 48127004 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 101529 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 9723453 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 6830710 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 683062 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 53931 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 11240 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 14810 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 174193 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 137584 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 311777 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 60001377 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 25939220 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 1040200 # Number of squashed instructions skipped in execute
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.iew.exec_nop 102592 # number of nop insts executed
system.cpu0.iew.exec_refs 32204815 # number of memory reference insts executed
system.cpu0.iew.exec_branches 5606114 # Number of branches executed
system.cpu0.iew.exec_stores 6265595 # Number of stores executed
system.cpu0.iew.exec_rate 0.249606 # Inst execution rate
system.cpu0.iew.wb_sent 59520960 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 42169433 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 22855569 # num instructions producing a value
system.cpu0.iew.wb_consumers 42162980 # num instructions consuming a value
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.iew.wb_rate 0.175425 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.542077 # average fanout of values written-back
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.commit.commitSquashedInsts 9402485 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 723741 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 272429 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 74993698 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.510414 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.487877 # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.commit.committed_per_cycle::0 61390308 81.86% 81.86% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 6607868 8.81% 90.67% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 1921399 2.56% 93.23% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 1064491 1.42% 94.65% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 990154 1.32% 95.97% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 565334 0.75% 96.73% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 721378 0.96% 97.69% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 343964 0.46% 98.15% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1388802 1.85% 100.00% # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.commit.committed_per_cycle::total 74993698 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 29384265 # Number of instructions committed
system.cpu0.commit.committedOps 38277857 # Number of ops (including micro ops) committed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.commit.refs 13675596 # Number of memory references committed
system.cpu0.commit.loads 7670972 # Number of loads committed
system.cpu0.commit.membars 201047 # Number of memory barriers committed
system.cpu0.commit.branches 4859392 # Number of branches committed
system.cpu0.commit.fp_insts 4891 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 33962414 # Number of committed integer instructions.
system.cpu0.commit.function_calls 491145 # Number of function calls committed.
system.cpu0.commit.bw_lim_events 1388802 # number cycles where commit BW limit reached
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.rob.rob_reads 120378043 # The number of ROB reads
system.cpu0.rob.rob_writes 96934970 # The number of ROB writes
system.cpu0.timesIdled 903993 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 163859787 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 2252055071 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 29315772 # Number of Instructions Simulated
system.cpu0.committedOps 38209364 # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total 29315772 # Number of Instructions Simulated
system.cpu0.cpi 8.199843 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 8.199843 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.121954 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.121954 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 271685631 # number of integer regfile reads
system.cpu0.int_regfile_writes 42795201 # number of integer regfile writes
system.cpu0.fp_regfile_reads 22306 # number of floating regfile reads
system.cpu0.fp_regfile_writes 19768 # number of floating regfile writes
system.cpu0.misc_regfile_reads 15093810 # number of misc regfile reads
system.cpu0.misc_regfile_writes 401151 # number of misc regfile writes
system.cpu0.icache.tags.replacements 983925 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.538497 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 10508756 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 984437 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 10.674889 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 6941856250 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 321.486243 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 190.052254 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.627903 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.371196 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999099 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 5171009 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 5337747 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 10508756 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 5171009 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 5337747 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 10508756 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 5171009 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 5337747 # number of overall hits
system.cpu0.icache.overall_hits::total 10508756 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 538904 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 526390 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1065294 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 538904 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 526390 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1065294 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 538904 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 526390 # number of overall misses
system.cpu0.icache.overall_misses::total 1065294 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7446919215 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7105468986 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 14552388201 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 7446919215 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 7105468986 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 14552388201 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 7446919215 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 7105468986 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 14552388201 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 5709913 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 5864137 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 11574050 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 5709913 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 5864137 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 11574050 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 5709913 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 5864137 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 11574050 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.094380 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.089764 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.092042 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.094380 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.089764 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.092042 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.094380 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.089764 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.092042 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13818.637856 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13498.487787 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13660.443221 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13818.637856 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13498.487787 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13660.443221 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13818.637856 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13498.487787 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13660.443221 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 6869 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 1025 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 398 # number of cycles access was blocked
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.258794 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 1025 # average number of cycles each access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 40970 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39858 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 80828 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 40970 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst 39858 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 80828 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 40970 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst 39858 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 80828 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 497934 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 486532 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 984466 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 497934 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 486532 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 984466 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 497934 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 486532 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 984466 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6047465345 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5786819388 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 11834284733 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6047465345 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5786819388 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 11834284733 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6047465345 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5786819388 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 11834284733 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8439000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8439000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8439000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 8439000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087205 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.082967 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085058 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087205 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.082967 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.085058 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087205 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.082967 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.085058 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12145.114302 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11894.015991 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12021.019246 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12145.114302 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11894.015991 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12021.019246 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12145.114302 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11894.015991 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12021.019246 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.dcache.tags.replacements 643834 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.993352 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 21533253 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 644346 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 33.418773 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 42568250 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.929916 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 257.063436 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497910 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.502077 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 6778619 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 6998983 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 13777602 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3655456 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 3606248 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 7261704 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 113306 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 129840 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 243146 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 115957 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 131727 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 247684 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 10434075 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 10605231 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 21039306 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 10434075 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 10605231 # number of overall hits
system.cpu0.dcache.overall_hits::total 21039306 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 328027 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 420957 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 748984 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1610503 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 1351638 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 2962141 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7363 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6159 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 13522 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 8 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 1938530 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 1772595 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 3711125 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1938530 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 1772595 # number of overall misses
system.cpu0.dcache.overall_misses::total 3711125 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5252707334 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6136741422 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 11389448756 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 82511290457 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 60760612895 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 143271903352 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 104363999 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 83076247 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 187440246 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 26000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 129002 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 155002 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 87763997791 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 66897354317 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 154661352108 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 87763997791 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 66897354317 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 154661352108 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7106646 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 7419940 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 14526586 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5265959 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 4957886 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 10223845 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 120669 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 135999 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 256668 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 115959 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 131735 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 247694 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 12372605 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 12377826 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 24750431 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 12372605 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 12377826 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 24750431 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.046158 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.056733 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.051560 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.305833 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.272624 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.289729 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.061018 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045287 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052683 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000017 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000061 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000040 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.156679 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.143207 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.149942 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.156679 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.143207 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.149942 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16013.033482 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14578.071922 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15206.531456 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 51233.242321 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44953.318044 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 48367.685182 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14174.113676 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13488.593440 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13861.872948 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16125.250000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15500.200000 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45273.479281 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 37739.785070 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 41675.058670 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45273.479281 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 37739.785070 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 41675.058670 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 36870 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 26211 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 3510 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 295 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.504274 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 88.850847 # average number of cycles each access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.dcache.writebacks::writebacks 608201 # number of writebacks
system.cpu0.dcache.writebacks::total 608201 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 147533 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 215292 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 362825 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1477292 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1235866 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 2713158 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 767 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 600 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1367 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1624825 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 1451158 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 3075983 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1624825 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 1451158 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 3075983 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 180494 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 205665 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 386159 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 133211 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 115772 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 248983 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6596 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5559 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12155 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 8 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 313705 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 321437 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 635142 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 313705 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 321437 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 635142 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2529137468 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2700943395 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5230080863 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6074560248 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4703819078 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10778379326 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 82036251 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 64895003 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146931254 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 22000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 112998 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 134998 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8603697716 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7404762473 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 16008460189 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8603697716 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7404762473 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 16008460189 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 92246094501 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90072157750 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182318252251 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13667158074 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13097409574 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26764567648 # number of WriteReq MSHR uncacheable cycles
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 155750 # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 155750 # number of LoadLockedReq MSHR uncacheable cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105913252575 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103169567324 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209082819899 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025398 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027718 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026583 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025297 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023351 # mshr miss rate for WriteReq accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.054662 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040875 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047357 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000017 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000061 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025355 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025969 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.025662 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025355 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025969 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.025662 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14012.307711 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13132.732332 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13543.853343 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45601.040815 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40630.023477 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43289.619476 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12437.272741 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11673.862745 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12088.132785 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14124.750000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13499.800000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27426.077735 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23036.434738 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25204.537236 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27426.077735 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23036.434738 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25204.537236 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.branchPred.lookups 7417918 # Number of BP lookups
system.cpu1.branchPred.condPredicted 5931932 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 364646 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 4881678 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 3917644 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.branchPred.BTBHitPct 80.251995 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 703527 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 35801 # Number of incorrect RAS predictions.
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.dtb.read_hits 25617777 # DTB read hits
system.cpu1.dtb.read_misses 38543 # DTB read misses
system.cpu1.dtb.write_hits 5691491 # DTB write hits
system.cpu1.dtb.write_misses 8859 # DTB write misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dtb.flush_tlb 255 # Number of times complete TLB was flushed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.dtb.flush_tlb_mva_asid 781 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 5585 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 2011 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 285 # Number of TLB faults due to prefetch
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.dtb.perms_faults 659 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 25656320 # DTB read accesses
system.cpu1.dtb.write_accesses 5700350 # DTB write accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.dtb.hits 31309268 # DTB hits
system.cpu1.dtb.misses 47402 # DTB misses
system.cpu1.dtb.accesses 31356670 # DTB accesses
system.cpu1.itb.inst_hits 5866342 # ITB inst hits
system.cpu1.itb.inst_misses 7403 # ITB inst misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.itb.flush_tlb 255 # Number of times complete TLB was flushed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.itb.flush_tlb_mva_asid 781 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 2681 # Number of entries that have been flushed from TLB
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.itb.perms_faults 1687 # Number of TLB faults due to permissions restrictions
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.itb.inst_accesses 5873745 # ITB inst accesses
system.cpu1.itb.hits 5866342 # DTB hits
system.cpu1.itb.misses 7403 # DTB misses
system.cpu1.itb.accesses 5873745 # DTB accesses
system.cpu1.numCycles 234836749 # number of cpu cycles simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.fetch.icacheStallCycles 14958684 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 46343438 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 7417918 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 4621171 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 10240931 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 2382000 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 84846 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles 47705916 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 1143 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles 1885 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles 51796 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 1300956 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 5864138 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 361139 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 3128 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 75991069 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.753206 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.110012 # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.fetch.rateDist::0 65758157 86.53% 86.53% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 661623 0.87% 87.40% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 874095 1.15% 88.55% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 1155735 1.52% 90.08% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 1058337 1.39% 91.47% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 579833 0.76% 92.23% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 1309635 1.72% 93.96% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 379645 0.50% 94.45% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 4214009 5.55% 100.00% # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.fetch.rateDist::total 75991069 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.031588 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.197343 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 15934805 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 48666188 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 9324612 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 504366 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 1558997 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 1010894 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 88249 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 54549781 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 295589 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 1558997 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 16808618 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 19027959 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 26571393 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 8885070 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 3136997 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 52018175 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 13230 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 586421 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents 2033878 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents 525 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 54353089 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 236755846 # Number of register rename lookups that rename has made
test: update stats Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses.
2013-10-16 16:44:12 +02:00
system.cpu1.rename.int_rename_lookups 219276243 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 5446 # Number of floating rename lookups
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.rename.CommittedMaps 40151278 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 14201811 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 419760 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 374760 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 6443032 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 10070258 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 6501681 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 951169 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 1220754 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 48367033 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 1016747 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 62006899 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 95474 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 9693963 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 24244292 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 257471 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 75991069 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.815976 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.521890 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.iq.issued_per_cycle::0 53638566 70.59% 70.59% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 7003056 9.22% 79.80% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 3617950 4.76% 84.56% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 3068918 4.04% 88.60% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 6184871 8.14% 96.74% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 1401826 1.84% 98.58% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 782382 1.03% 99.61% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 229717 0.30% 99.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 63783 0.08% 100.00% # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.iq.issued_per_cycle::total 75991069 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.iq.fu_full::IntAlu 31911 0.73% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 5 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.73% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 4158175 94.76% 95.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 198234 4.52% 100.00% # attempts to use FU when none available
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.iq.FU_type_0::No_OpClass 192098 0.31% 0.31% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 29460264 47.51% 47.82% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 45939 0.07% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 896 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.90% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 26296905 42.41% 90.31% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 6010767 9.69% 100.00% # Type of FU issued
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.iq.FU_type_0::total 62006899 # Type of FU issued
system.cpu1.iq.rate 0.264043 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 4388325 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.070772 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 204523942 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 59086561 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 43409940 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 11938 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 6483 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 5383 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 66196788 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 6338 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 319760 # Number of loads that had data forwarded from stores
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.iew.lsq.thread0.squashedLoads 2083716 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 3064 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 15874 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 772589 # Number of stores squashed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 16902604 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 332952 # Number of times an access to memory failed due to the cache being blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.iew.iewSquashCycles 1558997 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 14375191 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 227377 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 49504406 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 98291 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 10070258 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 6501681 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 727587 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 51733 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 9370 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 15874 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 179251 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 141654 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 320905 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 60955471 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 25970384 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 1051428 # Number of squashed instructions skipped in execute
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.iew.exec_nop 120626 # number of nop insts executed
system.cpu1.iew.exec_refs 31928214 # number of memory reference insts executed
system.cpu1.iew.exec_branches 5888736 # Number of branches executed
system.cpu1.iew.exec_stores 5957830 # Number of stores executed
system.cpu1.iew.exec_rate 0.259565 # Inst execution rate
system.cpu1.iew.wb_sent 60476945 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 43415323 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 24094324 # num instructions producing a value
system.cpu1.iew.wb_consumers 44023151 # num instructions consuming a value
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.iew.wb_rate 0.184874 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.547310 # average fanout of values written-back
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.commit.commitSquashedInsts 9567264 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 759276 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 277731 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 74432072 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.530472 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.515537 # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.commit.committed_per_cycle::0 60336914 81.06% 81.06% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 6930423 9.31% 90.37% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 1972494 2.65% 93.02% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 1094851 1.47% 94.50% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 1021489 1.37% 95.87% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 524731 0.70% 96.57% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 707921 0.95% 97.52% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 378966 0.51% 98.03% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 1464283 1.97% 100.00% # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.commit.committed_per_cycle::total 74432072 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 31082580 # Number of instructions committed
system.cpu1.commit.committedOps 39484127 # Number of ops (including micro ops) committed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.commit.refs 13715634 # Number of memory references committed
system.cpu1.commit.loads 7986542 # Number of loads committed
system.cpu1.commit.membars 202747 # Number of memory barriers committed
system.cpu1.commit.branches 5103464 # Number of branches committed
system.cpu1.commit.fp_insts 5321 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 34903456 # Number of committed integer instructions.
system.cpu1.commit.function_calls 500366 # Number of function calls committed.
system.cpu1.commit.bw_lim_events 1464283 # number cycles where commit BW limit reached
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.rob.rob_reads 121076761 # The number of ROB reads
system.cpu1.rob.rob_writes 99705340 # The number of ROB writes
system.cpu1.timesIdled 873554 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 158845680 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 2319747272 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 31000692 # Number of Instructions Simulated
system.cpu1.committedOps 39402239 # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total 31000692 # Number of Instructions Simulated
system.cpu1.cpi 7.575210 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 7.575210 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.132010 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.132010 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 276194442 # number of integer regfile reads
system.cpu1.int_regfile_writes 44861664 # number of integer regfile writes
system.cpu1.fp_regfile_reads 22699 # number of floating regfile reads
system.cpu1.fp_regfile_writes 19852 # number of floating regfile writes
system.cpu1.misc_regfile_reads 15196533 # number of misc regfile reads
system.cpu1.misc_regfile_writes 431717 # number of misc regfile writes
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1441896554007 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1441896554007 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1441896554007 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1441896554007 # number of overall MSHR uncacheable cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.kern.inst.quiesce 83067 # number of quiesce instructions executed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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