gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.814521                       # Number of seconds simulated
sim_ticks                                2814521286500                       # Number of ticks simulated
final_tick                               2814521286500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 106354                       # Simulator instruction rate (inst/s)
host_op_rate                                   129085                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2558515098                       # Simulator tick rate (ticks/s)
host_mem_usage                                 570360                       # Number of bytes of host memory used
host_seconds                                  1100.06                       # Real time elapsed on the host
sim_insts                                   116996192                       # Number of instructions simulated
sim_ops                                     142001364                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker         4288                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           746368                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          5095008                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker         4352                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           629952                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4708740                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11189732                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       746368                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       629952                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1376320                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8426816                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8444340                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker           67                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             11662                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             80128                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           68                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              9843                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             73575                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                175359                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          131669                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               136050                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          1524                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              265185                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1810257                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          1546                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              223822                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1673016                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              341                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3975714                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         265185                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         223822                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             489007                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2994049                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6223                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3000276                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2994049                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         1524                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             265185                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1816481                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         1546                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             223822                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            1673019                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             341                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6975990                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        175360                       # Number of read requests accepted
system.physmem.writeReqs                       172246                       # Number of write requests accepted
system.physmem.readBursts                      175360                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     172246                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 11215872                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7168                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  10651968                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  11189796                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               10760884                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      112                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    5779                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           4663                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11102                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11119                       # Per bank write bursts
system.physmem.perBankRdBursts::2               11680                       # Per bank write bursts
system.physmem.perBankRdBursts::3               11222                       # Per bank write bursts
system.physmem.perBankRdBursts::4               11370                       # Per bank write bursts
system.physmem.perBankRdBursts::5               11380                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11917                       # Per bank write bursts
system.physmem.perBankRdBursts::7               11794                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10207                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10426                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10580                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9765                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10349                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11405                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10639                       # Per bank write bursts
system.physmem.perBankRdBursts::15              10293                       # Per bank write bursts
system.physmem.perBankWrBursts::0               10392                       # Per bank write bursts
system.physmem.perBankWrBursts::1               10480                       # Per bank write bursts
system.physmem.perBankWrBursts::2               10999                       # Per bank write bursts
system.physmem.perBankWrBursts::3               10520                       # Per bank write bursts
system.physmem.perBankWrBursts::4               10645                       # Per bank write bursts
system.physmem.perBankWrBursts::5               10713                       # Per bank write bursts
system.physmem.perBankWrBursts::6               11169                       # Per bank write bursts
system.physmem.perBankWrBursts::7               10762                       # Per bank write bursts
system.physmem.perBankWrBursts::8                9958                       # Per bank write bursts
system.physmem.perBankWrBursts::9               10000                       # Per bank write bursts
system.physmem.perBankWrBursts::10               9968                       # Per bank write bursts
system.physmem.perBankWrBursts::11               9745                       # Per bank write bursts
system.physmem.perBankWrBursts::12              10100                       # Per bank write bursts
system.physmem.perBankWrBursts::13              10962                       # Per bank write bursts
system.physmem.perBankWrBursts::14              10229                       # Per bank write bursts
system.physmem.perBankWrBursts::15               9795                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
system.physmem.totGap                    2814521100500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     541                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  174805                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 167865                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    104183                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     61033                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      8516                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      1495                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        11                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       107                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                        99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2229                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3840                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6148                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     8662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     9336                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    10292                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    10753                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    11486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    11345                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    11872                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    11140                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    10729                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     9940                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    10200                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8319                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8066                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     8180                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7636                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      590                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      442                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      381                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      341                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      317                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      280                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      278                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      265                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      239                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      240                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      230                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      205                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      157                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      120                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       73                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       51                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       37                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        1                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        67109                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      325.854595                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     188.388710                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     345.406571                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          24509     36.52%     36.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        15902     23.70%     60.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6498      9.68%     69.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3742      5.58%     75.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2828      4.21%     79.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1529      2.28%     81.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1119      1.67%     83.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1119      1.67%     85.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         9863     14.70%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          67109                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          7131                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        24.571869                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      462.936248                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           7128     99.96%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-8191            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::36864-38911            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            7131                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          7131                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        23.339924                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       19.576956                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       21.763951                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                15      0.21%      0.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                 7      0.10%      0.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11                3      0.04%      0.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15               7      0.10%      0.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5889     82.58%     83.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             114      1.60%     84.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              53      0.74%     85.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             224      3.14%     88.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             142      1.99%     90.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              54      0.76%     91.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              26      0.36%     91.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              40      0.56%     92.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             124      1.74%     93.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              11      0.15%     94.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              11      0.15%     94.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              11      0.15%     94.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67              24      0.34%     94.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              13      0.18%     94.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              13      0.18%     95.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              32      0.45%     95.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              59      0.83%     96.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               9      0.13%     96.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               6      0.08%     96.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               9      0.13%     96.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99              92      1.29%     97.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             5      0.07%     98.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             8      0.11%     98.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             4      0.06%     98.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115            17      0.24%     98.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             3      0.04%     98.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123            14      0.20%     98.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             3      0.04%     98.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            38      0.53%     99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             9      0.13%     99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             4      0.06%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             9      0.13%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             3      0.04%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             3      0.04%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             7      0.10%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             3      0.04%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             2      0.03%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.01%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187             1      0.01%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             1      0.01%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-211             3      0.04%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-219             1      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::220-223             1      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-227             1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::228-231             1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::252-255             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            7131                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2737638250                       # Total ticks spent queuing
system.physmem.totMemAccLat                6023538250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    876240000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       15621.51                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  34371.51                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.99                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.78                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.98                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.82                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.45                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        11.89                       # Average write queue length when enqueuing
system.physmem.readRowHits                     144870                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    129705                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.67                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  77.92                       # Row buffer hit rate for writes
system.physmem.avgGap                      8096871.46                       # Average gap between requests
system.physmem.pageHitRate                      80.35                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     2688100208500                       # Time in different power states
system.physmem.memoryStateTime::REF       93982980000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       32438087000                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                 267820560                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                 239523480                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                 146132250                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                 130692375                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0                714347400                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1                652579200                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0               555206400                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1               523305360                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          183830708880                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          183830708880                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0           78196283910                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1           77193580095                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          1620118404000                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          1620997968750                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            1883828903400                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            1883568358140                       # Total energy per rank (pJ)
system.physmem.averagePower::0             669.325253                       # Core power per rank (mW)
system.physmem.averagePower::1             669.232681                       # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu0.inst          640                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           640                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          640                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          640                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           10                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             10                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst          227                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              227                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst          227                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          227                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst          227                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             227                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               27454524                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         14302225                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           560028                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            17144432                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               12924274                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            75.384673                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                6779174                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             30579                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    14369333                       # DTB read hits
system.cpu0.dtb.read_misses                     50679                       # DTB read misses
system.cpu0.dtb.write_hits                   10383293                       # DTB write hits
system.cpu0.dtb.write_misses                     7631                       # DTB write misses
system.cpu0.dtb.flush_tlb                         181                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     476                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3537                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1074                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1312                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      596                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                14420012                       # DTB read accesses
system.cpu0.dtb.write_accesses               10390924                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         24752626                       # DTB hits
system.cpu0.dtb.misses                          58310                       # DTB misses
system.cpu0.dtb.accesses                     24810936                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                    20633477                       # ITB inst hits
system.cpu0.itb.inst_misses                      8891                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         181                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     476                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2375                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1486                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                20642368                       # ITB inst accesses
system.cpu0.itb.hits                         20633477                       # DTB hits
system.cpu0.itb.misses                           8891                       # DTB misses
system.cpu0.itb.accesses                     20642368                       # DTB accesses
system.cpu0.numCycles                       108176623                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          40839610                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     106163283                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   27454524                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          19703448                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     62043143                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                3268003                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                    133218                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles                6760                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles              444                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles       566983                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       143911                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          303                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                 20632158                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               383201                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   3475                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         105368337                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.210422                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.308267                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                76140836     72.26%     72.26% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                 3909718      3.71%     75.97% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 2409828      2.29%     78.26% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                 8201309      7.78%     86.04% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 1666024      1.58%     87.62% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                 1066995      1.01%     88.64% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                 6252269      5.93%     94.57% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                 1076692      1.02%     95.59% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4644666      4.41%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           105368337                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.253794                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.981388                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                28207041                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             58279935                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 15901267                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles              1497528                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1482288                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             1929977                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred               153844                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              87989191                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               497994                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1482288                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                29073693                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                7845343                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      44593101                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 16518954                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              5854664                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              84134111                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 3122                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents               1216605                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                229511                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents               3673419                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands           86811691                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            387318144                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        93734921                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups             6132                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             72788537                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                14023138                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1551068                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts       1456111                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  8913232                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            15130036                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           11520954                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1958410                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         2751427                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  80936298                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1061855                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 77564111                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            93737                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       10215309                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     25112322                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        116543                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    105368337                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.736124                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.430465                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           74478008     70.68%     70.68% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           10230371      9.71%     80.39% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            7904463      7.50%     87.89% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            6602787      6.27%     94.16% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2340926      2.22%     96.38% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1499410      1.42%     97.81% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6            1574332      1.49%     99.30% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             494613      0.47%     99.77% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8             243427      0.23%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      105368337                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                 114999     10.01%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     3      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     10.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                537121     46.77%     56.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               496300     43.22%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             2212      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             51748002     66.72%     66.72% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               57664      0.07%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   2      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  1      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc          4488      0.01%     66.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            7      0.00%     66.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.80% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            14779498     19.05%     85.85% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           10972237     14.15%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              77564111                       # Type of FU issued
system.cpu0.iq.rate                          0.717014                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    1148423                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.014806                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         261725178                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         92258450                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     75089604                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              13541                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              7156                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         5898                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              78703023                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   7299                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          349741                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      2246191                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2538                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        53151                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      1141086                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads       210404                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       206292                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1482288                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                5387849                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles              2181647                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           82121235                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           133747                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             15130036                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            11520954                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            554131                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 44613                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents              2124772                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         53151                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        259624                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       223920                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              483544                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             76945762                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             14537604                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           560147                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       123082                       # number of nop insts executed
system.cpu0.iew.exec_refs                    25403316                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                14507602                       # Number of branches executed
system.cpu0.iew.exec_stores                  10865712                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.711298                       # Inst execution rate
system.cpu0.iew.wb_sent                      76276982                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     75095502                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 39231378                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 67987446                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.694193                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.577039                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts       11493235                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         945312                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           408278                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    102784889                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.686324                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.576953                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     75343720     73.30%     73.30% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1     12296354     11.96%     85.27% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      6287520      6.12%     91.38% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2655547      2.58%     93.97% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1297923      1.26%     95.23% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       837088      0.81%     96.04% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      1893538      1.84%     97.89% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       418210      0.41%     98.29% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1754989      1.71%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    102784889                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            58163617                       # Number of instructions committed
system.cpu0.commit.committedOps              70543777                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      23263713                       # Number of memory references committed
system.cpu0.commit.loads                     12883845                       # Number of loads committed
system.cpu0.commit.membars                     375648                       # Number of memory barriers committed
system.cpu0.commit.branches                  13703294                       # Number of branches committed
system.cpu0.commit.fp_insts                      5822                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 61764808                       # Number of committed integer instructions.
system.cpu0.commit.function_calls             2662565                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        47219648     66.94%     66.94% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult          55928      0.08%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc         4488      0.01%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.02% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       12883845     18.26%     85.29% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      10379868     14.71%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total         70543777                       # Class of committed instruction
system.cpu0.commit.bw_lim_events              1754989                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   170407355                       # The number of ROB reads
system.cpu0.rob.rob_writes                  166661887                       # The number of ROB writes
system.cpu0.timesIdled                         403384                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                        2808286                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  2462180041                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   58092959                       # Number of Instructions Simulated
system.cpu0.committedOps                     70473119                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.862130                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.862130                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.537020                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.537020                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                83669019                       # number of integer regfile reads
system.cpu0.int_regfile_writes               47858513                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                    16561                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                   13070                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                272007090                       # number of cc regfile reads
system.cpu0.cc_regfile_writes                28371958                       # number of cc regfile writes
system.cpu0.misc_regfile_reads              192053211                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                725022                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements           853093                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.984491                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           42526051                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           853605                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            49.819356                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         91705250                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   331.074612                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   180.909879                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.646630                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.353340                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999970                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          305                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           20                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        189920314                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       189920314                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     12675400                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     12670649                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       25346049                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      7759190                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      8148697                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      15907887                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       181607                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       180873                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       362480                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       209218                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       237638                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       446856                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       215214                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       244406                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       459620                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     20434590                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     20819346                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        41253936                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     20616197                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     21000219                       # number of overall hits
system.cpu0.dcache.overall_hits::total       41616416                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       429328                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       400663                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       829991                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1922864                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      1781286                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      3704150                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data        97758                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        84121                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       181879                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13488                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        14194                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        27682                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data           28                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data           50                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total           78                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      2352192                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      2181949                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       4534141                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      2449950                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      2266070                       # number of overall misses
system.cpu0.dcache.overall_misses::total      4716020                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   7076789424                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   6619917975                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  13696707399                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  83693793081                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  75813102630                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 159506895711                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    183195494                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    209562743                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    392758237                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       592508                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       853516                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total      1446024                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  90770582505                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  82433020605                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 173203603110                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  90770582505                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  82433020605                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 173203603110                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     13104728                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     13071312                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     26176040                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      9682054                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      9929983                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     19612037                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       279365                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       264994                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       544359                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       222706                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       251832                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       474538                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       215242                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       244456                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       459698                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     22786782                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     23001295                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     45788077                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     23066147                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     23266289                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     46332436                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032761                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.030652                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.031708                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.198601                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.179385                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.188871                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.349929                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.317445                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.334116                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.060564                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.056363                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058335                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000130                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000205                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000170                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.103226                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.094862                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.099024                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.106214                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.097397                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.101787                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16483.409943                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16522.409045                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 16502.236047                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43525.591556                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 42560.881650                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 43061.672910                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13582.109579                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14764.178033                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14188.217506                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        21161                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 17070.320000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 18538.769231                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 38589.784552                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 37779.535913                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 38199.871400                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37049.973471                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 36377.084823                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 36726.647281                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      1109617                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       154794                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            70377                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets           2390                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    15.766756                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    64.767364                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       704003                       # number of writebacks
system.cpu0.dcache.writebacks::total           704003                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       215622                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       188357                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       403979                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1768499                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1636007                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      3404506                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         9539                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         8963                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18502                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1984121                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data      1824364                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      3808485                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1984121                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data      1824364                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      3808485                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       213706                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       212306                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       426012                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       154365                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       145279                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       299644                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        64075                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        57558                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       121633                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         3949                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5231                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9180                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           28                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           50                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total           78                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       368071                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       357585                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       725656                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       432146                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       415143                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       847289                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2880376399                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2931260112                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5811636511                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6719128315                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6232840178                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  12951968493                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    978421259                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    894015008                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1872436267                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     46952751                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     79934003                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    126886754                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       536492                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       753484                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1289976                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9599504714                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   9164100290                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  18763605004                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10577925973                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  10058115298                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  20636041271                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3170222000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2614349000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5784571000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2418015877                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2018079000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4436094877                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5588237877                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   4632428000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10220665877                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016308                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016242                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016275                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015943                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014630                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015279                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.229359                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.217205                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.223443                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017732                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.020772                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.019345                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000130                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000205                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000170                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016153                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015546                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.015848                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018735                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017843                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.018287                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13478.219605                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13806.770002                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13641.954947                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43527.537428                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42902.554244                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43224.521409                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15269.937714                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15532.419612                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15394.146876                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11889.782477                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15280.826419                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13822.086492                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19160.428571                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15069.680000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16538.153846                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26080.578785                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25627.753653                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25857.437965                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24477.667207                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24228.073936                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24355.374932                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1945413                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.581807                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           39117111                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1945925                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            20.102065                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       9481344250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   277.889096                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   233.692710                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.542752                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.456431                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999183                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          229                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          158                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         43149539                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        43149539                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     19581058                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     19536053                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       39117111                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     19581058                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     19536053                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        39117111                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     19581058                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     19536053                       # number of overall hits
system.cpu0.icache.overall_hits::total       39117111                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1050436                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      1035972                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      2086408                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1050436                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      1035972                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       2086408                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1050436                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      1035972                       # number of overall misses
system.cpu0.icache.overall_misses::total      2086408                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14355946637                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  14071596928                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  28427543565                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  14355946637                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  14071596928                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  28427543565                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  14355946637                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  14071596928                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  28427543565                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     20631494                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     20572025                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     41203519                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     20631494                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     20572025                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     41203519                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     20631494                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     20572025                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     41203519                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.050914                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.050358                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.050637                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.050914                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.050358                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.050637                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.050914                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.050358                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.050637                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13666.655215                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13582.989625                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13625.112425                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13666.655215                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13582.989625                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13625.112425                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13666.655215                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13582.989625                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13625.112425                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         9173                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              525                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    17.472381                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        70447                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        69940                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       140387                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        70447                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst        69940                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       140387                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        70447                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst        69940                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       140387                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       979989                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       966032                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1946021                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       979989                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       966032                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1946021                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       979989                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       966032                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1946021                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11725666308                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  11493227261                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  23218893569                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11725666308                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  11493227261                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  23218893569                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11725666308                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  11493227261                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  23218893569                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst     49455500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total     49455500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst     49455500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total     49455500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.047500                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.046959                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047229                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.047500                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.046959                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.047229                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.047500                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.046959                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.047229                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11965.099923                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11897.356672                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11931.471227                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11965.099923                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11897.356672                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11931.471227                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11965.099923                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11897.356672                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11931.471227                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups               27255758                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         14164958                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           545624                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            17245755                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               12796801                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            74.202614                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                6756979                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             29539                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    14301761                       # DTB read hits
system.cpu1.dtb.read_misses                     48555                       # DTB read misses
system.cpu1.dtb.write_hits                   10652785                       # DTB write hits
system.cpu1.dtb.write_misses                    10002                       # DTB write misses
system.cpu1.dtb.flush_tlb                         175                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     441                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    3340                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      749                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  1278                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      539                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                14350316                       # DTB read accesses
system.cpu1.dtb.write_accesses               10662787                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         24954546                       # DTB hits
system.cpu1.dtb.misses                          58557                       # DTB misses
system.cpu1.dtb.accesses                     25013103                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                    20573712                       # ITB inst hits
system.cpu1.itb.inst_misses                      7567                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         175                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     441                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    2209                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1224                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                20581279                       # ITB inst accesses
system.cpu1.itb.hits                         20573712                       # DTB hits
system.cpu1.itb.misses                           7567                       # DTB misses
system.cpu1.itb.accesses                     20581279                       # DTB accesses
system.cpu1.numCycles                       106992745                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          40476291                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     106336791                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                   27255758                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          19553780                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     61749013                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                3214085                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                    109935                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles                4125                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles              398                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles       310457                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       137038                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          115                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                 20572028                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               377209                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   3305                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         104394378                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.225923                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.323476                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                75141351     71.98%     71.98% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                 3905835      3.74%     75.72% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                 2486724      2.38%     78.10% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 8099869      7.76%     85.86% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1581267      1.51%     87.38% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                 1170303      1.12%     88.50% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 6153110      5.89%     94.39% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                 1141979      1.09%     95.48% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 4713940      4.52%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           104394378                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.254744                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.993869                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                27669699                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             57891094                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 15657559                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles              1717451                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               1458318                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             1956668                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred               150768                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              88739686                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               487490                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               1458318                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                28613011                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                6694397                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      45325373                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 16423590                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              5879419                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              84880856                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                 2064                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents               1581177                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                275105                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents               3240122                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands           87684483                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            391488803                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        94864107                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups             5764                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             73992323                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                13692160                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts           1588753                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts       1487965                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 10049323                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            15109971                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           11816534                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          2163704                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         2733219                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  81632312                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded            1156422                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 78295274                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            93656                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        9981310                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     25207475                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        106198                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    104394378                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.749995                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.429509                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           72878860     69.81%     69.81% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1           10639333     10.19%     80.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            8017923      7.68%     87.68% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            6659758      6.38%     94.06% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            2479715      2.38%     96.44% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1538380      1.47%     97.91% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6            1459445      1.40%     99.31% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             494321      0.47%     99.78% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8             226643      0.22%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      104394378                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                 101103      8.77%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     4      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      8.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                535174     46.44%     55.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               516045     44.78%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass              125      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             52268288     66.76%     66.76% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               59024      0.08%     66.83% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     66.83% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     66.83% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     66.83% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     66.83% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     66.83% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     66.83% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     66.83% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     66.83% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     66.83% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     66.83% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     66.83% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     66.83% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     66.83% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     66.83% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     66.83% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     66.83% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.83% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     66.83% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.83% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.83% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              1      0.00%     66.83% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              1      0.00%     66.83% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              1      0.00%     66.83% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          4106      0.01%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            4      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.84% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            14700600     18.78%     85.61% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           11263124     14.39%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              78295274                       # Type of FU issued
system.cpu1.iq.rate                          0.731781                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    1152326                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.014718                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         262217922                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         92814464                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     75924804                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              12986                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              6859                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         5648                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              79440457                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   7018                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          366358                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      2171723                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         2780                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        52487                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      1144439                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads       191401                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked       154292                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               1458318                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                4304329                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles              2156600                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           82933418                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           134740                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             15109971                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            11816534                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            582996                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 47778                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents              2096463                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         52487                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        251579                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       218702                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              470281                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             77694436                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             14463933                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           542445                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       144684                       # number of nop insts executed
system.cpu1.iew.exec_refs                    25618626                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                14454326                       # Number of branches executed
system.cpu1.iew.exec_stores                  11154693                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.726165                       # Inst execution rate
system.cpu1.iew.wb_sent                      77075073                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     75930452                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 39739983                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 69711076                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.709679                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.570067                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts       11308333                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls        1050224                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           396863                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    101852612                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.703099                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.586744                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     73894552     72.55%     72.55% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1     12525380     12.30%     84.85% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      6426003      6.31%     91.16% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      2662589      2.61%     93.77% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4      1410437      1.38%     95.16% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       930996      0.91%     96.07% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      1822810      1.79%     97.86% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       425009      0.42%     98.28% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1754836      1.72%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    101852612                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            58987480                       # Number of instructions committed
system.cpu1.commit.committedOps              71612492                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      23610343                       # Number of memory references committed
system.cpu1.commit.loads                     12938248                       # Number of loads committed
system.cpu1.commit.membars                     439261                       # Number of memory barriers committed
system.cpu1.commit.branches                  13694369                       # Number of branches committed
system.cpu1.commit.fp_insts                      5606                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 62760739                       # Number of committed integer instructions.
system.cpu1.commit.function_calls             2679383                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu        47940825     66.94%     66.94% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          57221      0.08%     67.02% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.02% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.02% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.02% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.02% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.02% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.02% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.02% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.02% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.02% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.02% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.02% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.02% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.02% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.02% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.02% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.02% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.02% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.02% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.02% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.02% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.02% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.02% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.02% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc         4103      0.01%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.03% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       12938248     18.07%     85.10% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      10672095     14.90%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total         71612492                       # Class of committed instruction
system.cpu1.commit.bw_lim_events              1754836                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   170535238                       # The number of ROB reads
system.cpu1.rob.rob_writes                  168387616                       # The number of ROB writes
system.cpu1.timesIdled                         388789                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                        2598367                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  2951659136                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   58903233                       # Number of Instructions Simulated
system.cpu1.committedOps                     71528245                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.816415                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.816415                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.550535                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.550535                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                84575323                       # number of integer regfile reads
system.cpu1.int_regfile_writes               48329446                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    16299                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   13042                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                274393748                       # number of cc regfile reads
system.cpu1.cc_regfile_writes                28845956                       # number of cc regfile writes
system.cpu1.misc_regfile_reads              191595742                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                795775                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq                30210                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30210                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59038                       # Transaction distribution
system.iobus.trans_dist::WriteResp              22814                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54242                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105550                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72946                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72946                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178496                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67959                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159197                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321224                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321224                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480421                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             38529000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                85000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           347069959                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82736000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36834574                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36411                       # number of replacements
system.iocache.tags.tagsinuse                1.036467                       # Cycle average of tags in use
system.iocache.tags.total_refs                     28                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36427                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000769                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         234012835000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.036467                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.064779                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.064779                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328229                       # Number of tag accesses
system.iocache.tags.data_accesses              328229                       # Number of data accesses
system.iocache.WriteInvalidateReq_hits::realview.ide           27                       # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total           27                       # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::realview.ide          249                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              249                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide        36197                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        36197                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide          249                       # number of demand (read+write) misses
system.iocache.demand_misses::total               249                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          249                       # number of overall misses
system.iocache.overall_misses::total              249                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     29650777                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     29650777                       # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9620896608                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total   9620896608                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ide     29650777                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     29650777                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     29650777                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     29650777                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          249                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            249                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          249                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             249                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          249                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            249                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.999255                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total     0.999255                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 119079.425703                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 119079.425703                       # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265792.651546                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 265792.651546                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 119079.425703                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 119079.425703                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 119079.425703                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 119079.425703                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         56505                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 7228                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     7.817515                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36162                       # number of writebacks
system.iocache.writebacks::total                36162                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          249                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          249                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36197                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        36197                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          249                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          249                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          249                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          249                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     16701777                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     16701777                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7738504756                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7738504756                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     16701777                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     16701777                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     16701777                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     16701777                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide     0.999255                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.999255                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67075.409639                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 67075.409639                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213788.566898                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213788.566898                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 67075.409639                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 67075.409639                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 67075.409639                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 67075.409639                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   104261                       # number of replacements
system.l2c.tags.tagsinuse                65126.190512                       # Cycle average of tags in use
system.l2c.tags.total_refs                    3112631                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   169500                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    18.363605                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   48604.861621                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    48.289581                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000234                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     5571.225601                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2881.829872                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    43.411642                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     4982.002827                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     2994.569133                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.741651                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000737                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.085010                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.043973                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000662                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.076019                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.045693                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.993747                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023           65                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65174                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           65                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           15                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          326                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3251                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         9024                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        52558                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.000992                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.994476                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 29243192                       # Number of tag accesses
system.l2c.tags.data_accesses                29243192                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker        37242                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         8932                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             968875                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             274747                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        36318                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         7553                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             956014                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             266907                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                2556588                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          704003                       # number of Writeback hits
system.l2c.Writeback_hits::total               704003                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data              44                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              49                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  93                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            18                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            34                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                52                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            79209                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            77301                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               156510                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         37242                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          8932                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              968875                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              353956                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         36318                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          7553                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              956014                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              344208                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2713098                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        37242                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         8932                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             968875                       # number of overall hits
system.l2c.overall_hits::cpu0.data             353956                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        36318                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         7553                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             956014                       # number of overall hits
system.l2c.overall_hits::cpu1.data             344208                       # number of overall hits
system.l2c.overall_hits::total                2713098                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           67                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst            11018                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6966                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           68                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             9850                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             8162                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                36132                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1329                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1421                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2750                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data           10                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data           16                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total              26                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          73800                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          66534                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140334                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker           67                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             11018                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             80766                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           68                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              9850                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             74696                       # number of demand (read+write) misses
system.l2c.demand_misses::total                176466                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           67                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            11018                       # number of overall misses
system.l2c.overall_misses::cpu0.data            80766                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           68                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             9850                       # number of overall misses
system.l2c.overall_misses::cpu1.data            74696                       # number of overall misses
system.l2c.overall_misses::total               176466                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      5307250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker        74500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    830260250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    561837990                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      5302000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    743997000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    680663491                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     2827442481                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data       302987                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       512478                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       815465                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       261495                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       116495                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       377990                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   5655044288                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   5198826325                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  10853870613                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      5307250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker        74500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    830260250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   6216882278                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      5302000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    743997000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   5879489816                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     13681313094                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      5307250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker        74500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    830260250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   6216882278                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      5302000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    743997000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   5879489816                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    13681313094                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        37309                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         8933                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         979893                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         281713                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        36386                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         7553                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         965864                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         275069                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2592720                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       704003                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           704003                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1373                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1470                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2843                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data           28                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data           50                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            78                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       153009                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       143835                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           296844                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        37309                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         8933                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          979893                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          434722                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        36386                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         7553                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          965864                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          418904                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2889564                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        37309                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         8933                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         979893                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         434722                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        36386                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         7553                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         965864                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         418904                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2889564                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001796                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000112                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.011244                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.024727                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.001869                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.010198                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.029673                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.013936                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.967953                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.966667                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.967288                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.357143                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.320000                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.333333                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.482325                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.462572                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.472753                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001796                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000112                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.011244                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.185788                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.001869                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.010198                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.178313                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.061070                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001796                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000112                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.011244                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.185788                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.001869                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.010198                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.178313                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.061070                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79212.686567                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        74500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 75354.896533                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 80654.319552                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 77970.588235                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75532.690355                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 83394.203749                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 78253.140734                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   227.981189                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   360.646024                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   296.532727                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 26149.500000                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  7280.937500                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 14538.076923                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76626.616369                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 78137.889275                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 77343.128629                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79212.686567                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        74500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 75354.896533                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 76974.002402                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 77970.588235                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 75532.690355                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 78712.244511                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 77529.456632                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79212.686567                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        74500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 75354.896533                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 76974.002402                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 77970.588235                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 75532.690355                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 78712.244511                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 77529.456632                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               95507                       # number of writebacks
system.l2c.writebacks::total                    95507                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             6                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            72                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             5                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            68                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total               151                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             72                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             68                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                151                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            72                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            68                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               151                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           67                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst        11012                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         6894                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           68                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         9845                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         8094                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           35981                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1329                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1421                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2750                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           10                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           16                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total           26                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        73800                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        66534                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        140334                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           67                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        11012                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        80694                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           68                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         9845                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        74628                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           176315                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           67                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        11012                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        80694                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           68                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         9845                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        74628                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          176315                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      4476750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        62500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    691435500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    471945740                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      4460500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    619827250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    575916991                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   2368125231                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     13292828                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     14439421                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     27732249                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       200508                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       160016                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       360524                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4733648712                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4371400175                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   9105048887                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      4476750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    691435500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   5205594452                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      4460500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    619827250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   4947317166                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  11473174118                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      4476750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        62500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    691435500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   5205594452                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      4460500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    619827250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   4947317166                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  11473174118                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst     35706500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2948514500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2430763500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   5414984500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2216677000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1885542998                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4102219998                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst     35706500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5165191500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   4316306498                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   9517204498                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.001796                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000112                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.011238                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.024472                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.001869                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010193                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.029425                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.013878                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.967953                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.966667                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.967288                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.357143                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.320000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.333333                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.482325                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.462572                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.472753                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.001796                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000112                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.011238                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.185622                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.001869                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010193                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.178151                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.061018                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001796                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000112                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.011238                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.185622                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.001869                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010193                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.178151                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.061018                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66817.164179                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 62789.275336                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68457.461561                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65595.588235                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62958.583037                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 71153.569434                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 65815.992635                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10002.127916                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10161.450387                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10084.454182                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20050.800000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 13866.307692                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 64141.581463                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65701.749106                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 64881.275293                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66817.164179                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 62789.275336                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64510.303765                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65595.588235                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62958.583037                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66293.042370                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 65072.025171                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66817.164179                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 62789.275336                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64510.303765                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65595.588235                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62958.583037                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66293.042370                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 65072.025171                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               68031                       # Transaction distribution
system.membus.trans_dist::ReadResp              68030                       # Transaction distribution
system.membus.trans_dist::WriteReq              27609                       # Transaction distribution
system.membus.trans_dist::WriteResp             27609                       # Transaction distribution
system.membus.trans_dist::Writeback            131669                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        36196                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        36196                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4639                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq             26                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4665                       # Transaction distribution
system.membus.trans_dist::ReadExReq            138446                       # Transaction distribution
system.membus.trans_dist::ReadExResp           138446                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105550                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           20                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2076                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       464572                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       572218                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108820                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108820                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 681038                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159197                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          640                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4152                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17318744                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     17482733                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4631872                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      4631872                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                22114605                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              524                       # Total snoops (count)
system.membus.snoop_fanout::samples            347207                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  347207    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              347207                       # Request fanout histogram
system.membus.reqLayer0.occupancy            81506999                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               15812                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1714000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1759264748                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1730266590                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer3.occupancy           38512426                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq            2657108                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2657013                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             27609                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            27609                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           704003                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq        36196                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            2844                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq            78                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           2921                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           296844                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          296844                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      3893099                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2534750                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        42773                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       169663                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               6640285                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    124570688                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     99881325                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        65944                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       294780                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              224812737                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                           68939                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          3665274                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            5.009944                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.099221                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5                3628828     99.01%     99.01% # Request fanout histogram
system.toL2Bus.snoop_fanout::6                  36446      0.99%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              5                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              6                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            3665274                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         4674358232                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           697500                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        8766890883                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.3                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        3912089949                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          26359345                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          96778607                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    3042                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------