2013-01-07 19:05:52 +01:00
---------- Begin Simulation Statistics ----------
2015-11-06 09:26:50 +01:00
sim_seconds 2.823500 # Number of seconds simulated
2015-12-05 01:11:25 +01:00
sim_ticks 2823500372500 # Number of ticks simulated
final_tick 2823500372500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2013-01-07 19:05:52 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2015-12-05 01:11:25 +01:00
host_inst_rate 115105 # Simulator instruction rate (inst/s)
host_op_rate 139706 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2779881687 # Simulator tick rate (ticks/s)
host_mem_usage 588972 # Number of bytes of host memory used
host_seconds 1015.69 # Real time elapsed on the host
sim_insts 116911425 # Number of instructions simulated
sim_ops 141898519 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2015-12-05 01:11:25 +01:00
system.physmem.bytes_read::cpu0.dtb.walker 3648 # Number of bytes read from this memory
2014-06-22 23:33:09 +02:00
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
2015-12-05 01:11:25 +01:00
system.physmem.bytes_read::cpu0.inst 660992 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 5280544 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 5120 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 712768 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 4516872 # Number of bytes read from this memory
2014-11-12 15:05:25 +01:00
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
2015-12-05 01:11:25 +01:00
system.physmem.bytes_read::total 11180968 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 660992 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 712768 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1373760 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8429056 # Number of bytes written to this memory
2014-10-30 05:18:29 +01:00
system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory
2015-12-05 01:11:25 +01:00
system.physmem.bytes_written::total 8446580 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 57 # Number of read requests responded to by this memory
2014-06-22 23:33:09 +02:00
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
2015-12-05 01:11:25 +01:00
system.physmem.num_reads::cpu0.inst 10328 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 83027 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 80 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 11137 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 70578 # Number of read requests responded to by this memory
2014-11-12 15:05:25 +01:00
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
2015-12-05 01:11:25 +01:00
system.physmem.num_reads::total 175223 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 131704 # Number of write requests responded to by this memory
2014-10-30 05:18:29 +01:00
system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
2015-12-05 01:11:25 +01:00
system.physmem.num_writes::total 136085 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 1292 # Total read bandwidth from this memory (bytes/s)
2014-10-30 05:18:29 +01:00
system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
2015-12-05 01:11:25 +01:00
system.physmem.bw_read::cpu0.inst 234104 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1870212 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 1813 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 252441 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1599742 # Total read bandwidth from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
2015-12-05 01:11:25 +01:00
system.physmem.bw_read::total 3959967 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 234104 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 252441 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 486545 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2985321 # Write bandwidth from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_write::cpu0.data 6204 # Write bandwidth from this memory (bytes/s)
2014-10-30 05:18:29 +01:00
system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
2015-12-05 01:11:25 +01:00
system.physmem.bw_write::total 2991528 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2985321 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 1292 # Total bandwidth to/from this memory (bytes/s)
2014-10-30 05:18:29 +01:00
system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
2015-12-05 01:11:25 +01:00
system.physmem.bw_total::cpu0.inst 234104 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1876416 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 1813 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 252441 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 1599745 # Total bandwidth to/from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
2015-12-05 01:11:25 +01:00
system.physmem.bw_total::total 6951495 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 175224 # Number of read requests accepted
system.physmem.writeReqs 136085 # Number of write requests accepted
system.physmem.readBursts 175224 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 136085 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 11205440 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue
system.physmem.bytesWritten 8458688 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 11181032 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 8446580 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue
2015-09-25 13:27:03 +02:00
system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one
2015-12-05 01:11:25 +01:00
system.physmem.neitherReadNorWriteReqs 49641 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 11401 # Per bank write bursts
system.physmem.perBankRdBursts::1 10979 # Per bank write bursts
system.physmem.perBankRdBursts::2 11428 # Per bank write bursts
system.physmem.perBankRdBursts::3 11300 # Per bank write bursts
system.physmem.perBankRdBursts::4 11019 # Per bank write bursts
system.physmem.perBankRdBursts::5 10545 # Per bank write bursts
system.physmem.perBankRdBursts::6 11444 # Per bank write bursts
system.physmem.perBankRdBursts::7 11405 # Per bank write bursts
system.physmem.perBankRdBursts::8 11225 # Per bank write bursts
system.physmem.perBankRdBursts::9 11073 # Per bank write bursts
system.physmem.perBankRdBursts::10 10490 # Per bank write bursts
system.physmem.perBankRdBursts::11 10075 # Per bank write bursts
system.physmem.perBankRdBursts::12 10628 # Per bank write bursts
system.physmem.perBankRdBursts::13 11391 # Per bank write bursts
system.physmem.perBankRdBursts::14 10678 # Per bank write bursts
system.physmem.perBankRdBursts::15 10004 # Per bank write bursts
system.physmem.perBankWrBursts::0 8636 # Per bank write bursts
system.physmem.perBankWrBursts::1 8268 # Per bank write bursts
system.physmem.perBankWrBursts::2 8882 # Per bank write bursts
system.physmem.perBankWrBursts::3 8813 # Per bank write bursts
system.physmem.perBankWrBursts::4 7855 # Per bank write bursts
system.physmem.perBankWrBursts::5 7878 # Per bank write bursts
system.physmem.perBankWrBursts::6 8477 # Per bank write bursts
system.physmem.perBankWrBursts::7 8545 # Per bank write bursts
system.physmem.perBankWrBursts::8 8487 # Per bank write bursts
system.physmem.perBankWrBursts::9 8481 # Per bank write bursts
system.physmem.perBankWrBursts::10 7867 # Per bank write bursts
system.physmem.perBankWrBursts::11 7716 # Per bank write bursts
system.physmem.perBankWrBursts::12 8202 # Per bank write bursts
system.physmem.perBankWrBursts::13 8761 # Per bank write bursts
system.physmem.perBankWrBursts::14 7974 # Per bank write bursts
system.physmem.perBankWrBursts::15 7325 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2015-12-05 01:11:25 +01:00
system.physmem.numWrRetry 9 # Number of times write queue was full causing retry
system.physmem.totGap 2823500194500 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
2015-05-05 09:22:39 +02:00
system.physmem.readPktSize::2 542 # Read request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.readPktSize::3 14 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2015-12-05 01:11:25 +01:00
system.physmem.readPktSize::6 174668 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2015-12-05 01:11:25 +01:00
system.physmem.writePktSize::6 131704 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 107487 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 59144 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 6664 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1770 # What read queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
2014-10-30 05:18:29 +01:00
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
2013-11-27 00:05:25 +01:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
2013-01-07 19:05:52 +01:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2015-12-05 01:11:25 +01:00
system.physmem.wrQLenPdf::0 109 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 97 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.wrQLenPdf::2 97 # What write queue length does an incoming req see
2015-12-05 01:11:25 +01:00
system.physmem.wrQLenPdf::3 96 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 95 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.wrQLenPdf::5 92 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 92 # What write queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.wrQLenPdf::7 92 # What write queue length does an incoming req see
2015-12-05 01:11:25 +01:00
system.physmem.wrQLenPdf::8 92 # What write queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.wrQLenPdf::9 89 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 88 # What write queue length does an incoming req see
2015-12-05 01:11:25 +01:00
system.physmem.wrQLenPdf::11 88 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 86 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 85 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.wrQLenPdf::14 85 # What write queue length does an incoming req see
2015-12-05 01:11:25 +01:00
system.physmem.wrQLenPdf::15 2052 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2383 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4847 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6230 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 7012 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 7286 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 8145 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 7696 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 8524 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 8763 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 8680 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 10155 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 8152 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7954 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 8353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7289 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7117 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 6804 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 380 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 246 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 259 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 238 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 138 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 92 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 92 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 121 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 134 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 166 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 73 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 103 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 124 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 99 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 132 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 80 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 63 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 33 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 34 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 34 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 23 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 35 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 17 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 65624 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 299.646471 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 177.275715 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 322.864593 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 24692 37.63% 37.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 16213 24.71% 62.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6759 10.30% 72.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3713 5.66% 78.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2878 4.39% 82.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1688 2.57% 85.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1064 1.62% 86.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1117 1.70% 88.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7500 11.43% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 65624 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6648 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 26.331227 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 483.912144 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 6646 99.97% 99.97% # Reads before turning the bus around for writes
2015-11-06 09:26:50 +01:00
system.physmem.rdPerTurnAround::6144-8191 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::36864-38911 1 0.02% 100.00% # Reads before turning the bus around for writes
2015-12-05 01:11:25 +01:00
system.physmem.rdPerTurnAround::total 6648 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6648 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 19.880716 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.279022 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 12.177011 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 14 0.21% 0.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 3 0.05% 0.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11 5 0.08% 0.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15 11 0.17% 0.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 5692 85.62% 86.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 171 2.57% 88.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 60 0.90% 89.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 185 2.78% 92.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 34 0.51% 92.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 150 2.26% 95.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 50 0.75% 95.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 10 0.15% 96.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 23 0.35% 96.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 19 0.29% 96.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 7 0.11% 96.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 8 0.12% 96.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 143 2.15% 99.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 5 0.08% 99.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 7 0.11% 99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 20 0.30% 99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 1 0.02% 99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 1 0.02% 99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 1 0.02% 99.58% # Writes before turning the bus around for reads
2015-11-06 09:26:50 +01:00
system.physmem.wrPerTurnAround::96-99 1 0.02% 99.59% # Writes before turning the bus around for reads
2015-12-05 01:11:25 +01:00
system.physmem.wrPerTurnAround::100-103 2 0.03% 99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 1 0.02% 99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 13 0.20% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 2 0.03% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 1 0.02% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 1 0.02% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 1 0.02% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 3 0.05% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 3 0.05% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6648 # Writes before turning the bus around for reads
system.physmem.totQLat 2744374251 # Total ticks spent queuing
system.physmem.totMemAccLat 6027218001 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 875425000 # Total ticks spent in databus transfers
system.physmem.avgQLat 15674.53 # Average queueing delay per DRAM burst
2015-09-25 13:27:03 +02:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2015-12-05 01:11:25 +01:00
system.physmem.avgMemAccLat 34424.53 # Average memory access latency per DRAM burst
2015-09-25 13:27:03 +02:00
system.physmem.avgRdBW 3.97 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.96 # Average system read bandwidth in MiByte/s
2015-12-05 01:11:25 +01:00
system.physmem.avgWrBWSys 2.99 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-07-03 16:15:03 +02:00
system.physmem.busUtil 0.05 # Data bus utilization in percentage
2014-10-30 05:18:29 +01:00
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
2015-07-03 16:15:03 +02:00
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
2015-11-06 09:26:50 +01:00
system.physmem.avgRdQLen 1.46 # Average read queue length when enqueuing
2015-12-05 01:11:25 +01:00
system.physmem.avgWrQLen 12.80 # Average write queue length when enqueuing
system.physmem.readRowHits 144084 # Number of row buffer hits during reads
system.physmem.writeRowHits 97542 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.29 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 73.78 # Row buffer hit rate for writes
system.physmem.avgGap 9069767.32 # Average gap between requests
system.physmem.pageHitRate 78.63 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 256420080 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 139911750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 698263800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 436453920 # Energy for write commands per rank (pJ)
2015-11-06 09:26:50 +01:00
system.physmem_0.refreshEnergy 184417078560 # Energy for refresh commands per rank (pJ)
2015-12-05 01:11:25 +01:00
system.physmem_0.actBackEnergy 80050894335 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1623878080500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1889877102945 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.339172 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2701352401000 # Time in different power states
2015-11-06 09:26:50 +01:00
system.physmem_0.memoryStateTime::REF 94282760000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-12-05 01:11:25 +01:00
system.physmem_0.memoryStateTime::ACT 27861791500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-12-05 01:11:25 +01:00
system.physmem_1.actEnergy 239697360 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 130787250 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 667383600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 419988240 # Energy for write commands per rank (pJ)
2015-11-06 09:26:50 +01:00
system.physmem_1.refreshEnergy 184417078560 # Energy for refresh commands per rank (pJ)
2015-12-05 01:11:25 +01:00
system.physmem_1.actBackEnergy 79252079805 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1624578795000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1889705809815 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.278505 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2702525049250 # Time in different power states
2015-11-06 09:26:50 +01:00
system.physmem_1.memoryStateTime::REF 94282760000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-12-05 01:11:25 +01:00
system.physmem_1.memoryStateTime::ACT 26691828250 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-07-03 16:15:03 +02:00
system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory
2015-09-25 13:27:03 +02:00
system.realview.nvmem.bw_read::cpu0.inst 249 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 249 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 249 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 249 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 249 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 249 # Total bandwidth to/from this memory (bytes/s)
2013-01-07 19:05:52 +01:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
2014-10-30 05:18:29 +01:00
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
2015-12-05 01:11:25 +01:00
system.cpu0.branchPred.lookups 26559789 # Number of BP lookups
system.cpu0.branchPred.condPredicted 13713833 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 501635 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 15976864 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 12419776 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2015-12-05 01:11:25 +01:00
system.cpu0.branchPred.BTBHitPct 77.736006 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 6636189 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 27705 # Number of incorrect RAS predictions.
2014-11-12 15:05:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-12-23 15:31:20 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.walker.walks 56617 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 56617 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17206 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 13819 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 25592 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 31025 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean 854.665592 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 5277.318433 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-16383 30569 98.53% 98.53% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-32767 316 1.02% 99.55% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-49151 76 0.24% 99.79% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::49152-65535 28 0.09% 99.88% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-81919 17 0.05% 99.94% # Table walker wait (enqueue to first request) latency
2015-11-06 09:26:50 +01:00
system.cpu0.dtb.walker.walkWaitTime::81920-98303 4 0.01% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::98304-114687 5 0.02% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::114688-131071 5 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-147455 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::147456-163839 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.walker.walkWaitTime::total 31025 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 12676 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 13504.851688 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 10947.656823 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 9228.518750 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383 9308 73.43% 73.43% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767 3112 24.55% 97.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151 228 1.80% 99.78% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::49152-65535 10 0.08% 99.86% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-81919 2 0.02% 99.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-147455 13 0.10% 99.98% # Table walker service (enqueue to completion) latency
2015-09-25 13:27:03 +02:00
system.cpu0.dtb.walker.walkCompletionTime::147456-163839 3 0.02% 100.00% # Table walker service (enqueue to completion) latency
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.walker.walkCompletionTime::total 12676 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 91900678744 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.634073 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.504786 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1 91817596744 99.91% 99.91% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3 56432500 0.06% 99.97% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5 12685500 0.01% 99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7 5058000 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9 2486500 0.00% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11 1667000 0.00% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13 978500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15 2452500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17 399500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::18-19 440000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::20-21 77000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::22-23 47000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::24-25 115000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::26-27 26500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::28-29 31000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::30-31 185500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 91900678744 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 3474 69.04% 69.04% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M 1558 30.96% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 5032 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 56617 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 56617 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5032 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5032 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 61649 # Table walker requests started/completed, data/inst
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.read_hits 13956888 # DTB read hits
system.cpu0.dtb.read_misses 47161 # DTB read misses
system.cpu0.dtb.write_hits 10502014 # DTB write hits
system.cpu0.dtb.write_misses 9456 # DTB write misses
2015-11-06 09:26:50 +01:00
system.cpu0.dtb.flush_tlb 179 # Number of times complete TLB was flushed
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.flush_tlb_mva 479 # Number of times TLB was flushed by MVA
2014-10-30 05:18:29 +01:00
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.flush_entries 3284 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 763 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 1265 # Number of TLB faults due to prefetch
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.perms_faults 602 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 14004049 # DTB read accesses
system.cpu0.dtb.write_accesses 10511470 # DTB write accesses
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.hits 24458902 # DTB hits
system.cpu0.dtb.misses 56617 # DTB misses
system.cpu0.dtb.accesses 24515519 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-12-05 01:11:25 +01:00
system.cpu0.itb.walker.walks 7529 # Table walker walks requested
system.cpu0.itb.walker.walksShort 7529 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2281 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5094 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore 154 # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples 7375 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean 1792 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 7463.239883 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-16383 7070 95.86% 95.86% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-32767 234 3.17% 99.04% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-49151 37 0.50% 99.54% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::49152-65535 16 0.22% 99.76% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-81919 7 0.09% 99.85% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::81920-98303 5 0.07% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-114687 1 0.01% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::114688-131071 2 0.03% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-147455 3 0.04% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 7375 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 2396 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 13984.557596 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11758.733193 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 8144.466175 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-16383 1749 73.00% 73.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-32767 606 25.29% 98.29% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-49151 39 1.63% 99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
2015-09-25 13:27:03 +02:00
system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
2015-12-05 01:11:25 +01:00
system.cpu0.itb.walker.walkCompletionTime::total 2396 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 23180931508 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 0.845594 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev 0.362375 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 3585102000 15.47% 15.47% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 19591754508 84.52% 99.98% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2 3051000 0.01% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3 602000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4 249500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::5 48000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::6 124500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 23180931508 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 1680 74.93% 74.93% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M 562 25.07% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 2242 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 7529 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 7529 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2242 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2242 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 9771 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 20127989 # ITB inst hits
system.cpu0.itb.inst_misses 7529 # ITB inst misses
2013-01-07 19:05:52 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
2015-11-06 09:26:50 +01:00
system.cpu0.itb.flush_tlb 179 # Number of times complete TLB was flushed
2015-12-05 01:11:25 +01:00
system.cpu0.itb.flush_tlb_mva 479 # Number of times TLB was flushed by MVA
2014-10-30 05:18:29 +01:00
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-12-05 01:11:25 +01:00
system.cpu0.itb.flush_entries 2165 # Number of entries that have been flushed from TLB
2013-01-07 19:05:52 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2015-12-05 01:11:25 +01:00
system.cpu0.itb.perms_faults 1248 # Number of TLB faults due to permissions restrictions
2013-01-07 19:05:52 +01:00
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
2015-12-05 01:11:25 +01:00
system.cpu0.itb.inst_accesses 20135518 # ITB inst accesses
system.cpu0.itb.hits 20127989 # DTB hits
system.cpu0.itb.misses 7529 # DTB misses
system.cpu0.itb.accesses 20135518 # DTB accesses
system.cpu0.numCycles 111773750 # number of cpu cycles simulated
2013-01-07 19:05:52 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-12-05 01:11:25 +01:00
system.cpu0.fetch.icacheStallCycles 39404734 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 103901347 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 26559789 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 19055965 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 67172503 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 3105480 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 123475 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 4254 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles 446 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles 188702 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 117718 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 813 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 20126932 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 348923 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 3603 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 108565347 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 1.150440 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.270106 # Number of instructions fetched each cycle (Total)
2013-01-07 19:05:52 +01:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2015-12-05 01:11:25 +01:00
system.cpu0.fetch.rateDist::0 80009058 73.70% 73.70% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 3809201 3.51% 77.21% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 2394359 2.21% 79.41% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 7998409 7.37% 86.78% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 1537996 1.42% 88.19% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 1087909 1.00% 89.20% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 6040532 5.56% 94.76% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 1033019 0.95% 95.71% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 4654864 4.29% 100.00% # Number of instructions fetched each cycle (Total)
2013-01-07 19:05:52 +01:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2015-12-05 01:11:25 +01:00
system.cpu0.fetch.rateDist::total 108565347 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.237621 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.929568 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 26883025 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 63349855 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 15403629 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 1519503 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 1408994 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 1872503 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 145749 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 86293156 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 470873 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 1408994 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 27735944 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 6700023 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 45856628 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 16066730 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 10796686 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 82579979 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 2391 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 1108634 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 252112 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 8668459 # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands 84779937 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 381537510 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 92587970 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 5626 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 72263854 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 12516075 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 1563295 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 1465928 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 8829402 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 14730052 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 11675597 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 2115179 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 2832097 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 79532292 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1117477 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 76533618 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 87406 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 10386047 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 23162950 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 102669 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 108565347 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.704954 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.405780 # Number of insts issued each cycle
2013-01-07 19:05:52 +01:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2015-12-05 01:11:25 +01:00
system.cpu0.iq.issued_per_cycle::0 77871483 71.73% 71.73% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 10453105 9.63% 81.36% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 7708495 7.10% 88.46% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 6443405 5.94% 94.39% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 2343404 2.16% 96.55% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 1520676 1.40% 97.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 1477584 1.36% 99.31% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 486752 0.45% 99.76% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 260443 0.24% 100.00% # Number of insts issued each cycle
2013-01-07 19:05:52 +01:00
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2015-12-05 01:11:25 +01:00
system.cpu0.iq.issued_per_cycle::total 108565347 # Number of insts issued each cycle
2013-01-07 19:05:52 +01:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2015-12-05 01:11:25 +01:00
system.cpu0.iq.fu_full::IntAlu 112393 9.83% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 1 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 527099 46.11% 55.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 503655 44.06% 100.00% # attempts to use FU when none available
2013-01-07 19:05:52 +01:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2015-11-06 09:26:50 +01:00
system.cpu0.iq.FU_type_0::No_OpClass 225 0.00% 0.00% # Type of FU issued
2015-12-05 01:11:25 +01:00
system.cpu0.iq.FU_type_0::IntAlu 50981056 66.61% 66.61% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 56862 0.07% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 4067 0.01% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.69% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 14347373 18.75% 85.44% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 11144026 14.56% 100.00% # Type of FU issued
2013-01-07 19:05:52 +01:00
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2015-12-05 01:11:25 +01:00
system.cpu0.iq.FU_type_0::total 76533618 # Type of FU issued
system.cpu0.iq.rate 0.684719 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 1143148 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.014937 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 262850677 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 91081899 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 74283043 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 12460 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 6644 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 5511 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 77669867 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 6674 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 356195 # Number of loads that had data forwarded from stores
2013-01-07 19:05:52 +01:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2015-12-05 01:11:25 +01:00
system.cpu0.iew.lsq.thread0.squashedLoads 1995192 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 2360 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 53884 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 1081117 # Number of stores squashed
2013-01-07 19:05:52 +01:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2015-12-05 01:11:25 +01:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 202683 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 121039 # Number of times an access to memory failed due to the cache being blocked
2013-01-07 19:05:52 +01:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2015-12-05 01:11:25 +01:00
system.cpu0.iew.iewSquashCycles 1408994 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 5274240 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 1210190 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 80780073 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 118682 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 14730052 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 11675597 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 571348 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 46022 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 1152002 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 53884 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 221496 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 202557 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 424053 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 75976302 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 14126659 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 500836 # Number of squashed instructions skipped in execute
2013-01-07 19:05:52 +01:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
2015-12-05 01:11:25 +01:00
system.cpu0.iew.exec_nop 130304 # number of nop insts executed
system.cpu0.iew.exec_refs 25168197 # number of memory reference insts executed
system.cpu0.iew.exec_branches 14063788 # Number of branches executed
system.cpu0.iew.exec_stores 11041538 # Number of stores executed
system.cpu0.iew.exec_rate 0.679733 # Inst execution rate
system.cpu0.iew.wb_sent 75420123 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 74288554 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 38930485 # num instructions producing a value
system.cpu0.iew.wb_consumers 68286780 # num instructions consuming a value
system.cpu0.iew.wb_rate 0.664633 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.570103 # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts 10422530 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 1014808 # The number of times commit has been forced to stall to communicate backwards
2015-11-06 09:26:50 +01:00
system.cpu0.commit.branchMispredicts 357851 # The number of times a branch was mispredicted
2015-12-05 01:11:25 +01:00
system.cpu0.commit.committed_per_cycle::samples 106167071 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.662547 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.559914 # Number of insts commited each cycle
2013-01-07 19:05:52 +01:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2015-12-05 01:11:25 +01:00
system.cpu0.commit.committed_per_cycle::0 78816600 74.24% 74.24% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 12394656 11.67% 85.91% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 6095585 5.74% 91.65% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 2659364 2.50% 94.16% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 1364551 1.29% 95.44% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 834490 0.79% 96.23% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 1723865 1.62% 97.85% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 420734 0.40% 98.25% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1857226 1.75% 100.00% # Number of insts commited each cycle
2013-01-07 19:05:52 +01:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2015-12-05 01:11:25 +01:00
system.cpu0.commit.committed_per_cycle::total 106167071 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 57989505 # Number of instructions committed
system.cpu0.commit.committedOps 70340708 # Number of ops (including micro ops) committed
2013-01-07 19:05:52 +01:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
2015-12-05 01:11:25 +01:00
system.cpu0.commit.refs 23329340 # Number of memory references committed
system.cpu0.commit.loads 12734860 # Number of loads committed
system.cpu0.commit.membars 416180 # Number of memory barriers committed
system.cpu0.commit.branches 13372532 # Number of branches committed
2015-11-06 09:26:50 +01:00
system.cpu0.commit.fp_insts 5482 # Number of committed floating point instructions.
2015-12-05 01:11:25 +01:00
system.cpu0.commit.int_insts 61754724 # Number of committed integer instructions.
system.cpu0.commit.function_calls 2627334 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2015-12-05 01:11:25 +01:00
system.cpu0.commit.op_class_0::IntAlu 46951986 66.75% 66.75% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 55316 0.08% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 4066 0.01% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.83% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 12734860 18.10% 84.94% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 10594480 15.06% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2015-12-05 01:11:25 +01:00
system.cpu0.commit.op_class_0::total 70340708 # Class of committed instruction
system.cpu0.commit.bw_lim_events 1857226 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 172725039 # The number of ROB reads
system.cpu0.rob.rob_writes 163928651 # The number of ROB writes
system.cpu0.timesIdled 382167 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 3208403 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 2095470503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 57912515 # Number of Instructions Simulated
system.cpu0.committedOps 70263718 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.930045 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.930045 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.518123 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.518123 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 82944906 # number of integer regfile reads
system.cpu0.int_regfile_writes 47313800 # number of integer regfile writes
system.cpu0.fp_regfile_reads 16399 # number of floating regfile reads
system.cpu0.fp_regfile_writes 13366 # number of floating regfile writes
system.cpu0.cc_regfile_reads 268363191 # number of cc regfile reads
system.cpu0.cc_regfile_writes 27733780 # number of cc regfile writes
system.cpu0.misc_regfile_reads 150032753 # number of misc regfile reads
system.cpu0.misc_regfile_writes 778510 # number of misc regfile writes
system.cpu0.dcache.tags.replacements 855432 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.968774 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 42360074 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 855944 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 49.489305 # Average number of references to valid blocks.
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.tags.warmup_cycle 186702500 # Cycle when the warmup percentage was hit.
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 250.285909 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 261.682865 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.488840 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.511099 # Average percentage of cache occupancy
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.tags.occ_percent::total 0.999939 # Average percentage of cache occupancy
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.tags.tag_accesses 189283631 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 189283631 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 12299336 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 12887121 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 25186457 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 7940771 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 7960315 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 15901086 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 183903 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 180299 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 364202 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 230031 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 215903 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 445934 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236508 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 222797 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 459305 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 20240107 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 20847436 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 41087543 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 20424010 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 21027735 # number of overall hits
system.cpu0.dcache.overall_hits::total 41451745 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 436616 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 404052 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 840668 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1879075 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 1817736 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 3696811 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 117503 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 66969 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 184472 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13695 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14214 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 27909 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 35 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 35 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 70 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 2315691 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 2221788 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 4537479 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 2433194 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 2288757 # number of overall misses
system.cpu0.dcache.overall_misses::total 4721951 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7223531500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 7393293500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 14616825000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 137673616868 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 114952576008 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 252626192876 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 218177000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 196691000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 414868000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 902000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 1175500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 2077500 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 144897148368 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 122345869508 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 267243017876 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 144897148368 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 122345869508 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 267243017876 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 12735952 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 13291173 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 26027125 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 9819846 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 9778051 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 19597897 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 301406 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 247268 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 548674 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 243726 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 230117 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 473843 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236543 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 222832 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 459375 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 22555798 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 23069224 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 45625022 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 22857204 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 23316492 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 46173696 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.034282 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.030400 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.032300 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.191355 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.185900 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.188633 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.389850 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.270836 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.336214 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056190 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.061769 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058899 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000148 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000157 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000152 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.102665 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.096310 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.099452 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.106452 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.098160 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.102265 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16544.358200 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18297.876263 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17387.155215 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 73266.696044 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 63239.423111 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 68336.247884 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15931.142753 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13837.835936 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14865.025619 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25771.428571 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 33585.714286 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 29678.571429 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 62571.883886 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 55066.401253 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 58896.805445 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 59550.183162 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 53455.159070 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 56595.889681 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 1672747 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 343360 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 52819 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 3007 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 31.669418 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 114.186897 # average number of cycles each access was blocked
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.writebacks::writebacks 705176 # number of writebacks
system.cpu0.dcache.writebacks::total 705176 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 227433 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 186404 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 413837 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1727395 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1669692 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 3397087 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 8981 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 9780 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18761 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1954828 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 1856096 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 3810924 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1954828 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 1856096 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 3810924 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 209183 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 217648 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 426831 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 151680 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 148044 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 299724 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 74197 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 48897 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 123094 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4714 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4434 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9148 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 35 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 35 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 70 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 360863 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 365692 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 726555 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 435060 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 414589 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 849649 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 14753 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16376 # number of ReadReq MSHR uncacheable
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31129 # number of ReadReq MSHR uncacheable
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15226 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 12362 # number of WriteReq MSHR uncacheable
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27588 # number of WriteReq MSHR uncacheable
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 29979 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 28738 # number of overall MSHR uncacheable misses
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58717 # number of overall MSHR uncacheable misses
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3331281500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 3387836500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6719118000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11202793385 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 9855220460 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 21058013845 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1114883500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 753687500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1868571000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 93837000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 59852000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 153689000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 867000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 1140500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2007500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 14534074885 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 13243056960 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 27777131845 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15648958385 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 13996744460 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 29645702845 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2963039000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3337977000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6301016000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2592772424 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2491429952 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5084202376 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5555811424 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5829406952 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11385218376 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016425 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016375 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016399 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015446 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015140 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015294 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.246170 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.197749 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224348 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.019341 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019268 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019306 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000148 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000157 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000152 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015999 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015852 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.015924 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019034 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017781 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.018401 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15925.201857 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15565.667959 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15741.869733 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 73858.078751 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 66569.536489 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70258.016859 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15025.991617 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15413.777941 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15180.033145 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 19906.024608 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13498.421290 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16800.284215 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24771.428571 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 32585.714286 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 28678.571429 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40275.880002 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 36213.690647 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38231.285787 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35969.655645 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 33760.530212 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34891.705687 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200843.150546 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 203833.475818 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202416.267789 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170285.854722 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 201539.391037 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184290.357257 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 185323.440542 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 202846.647366 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193899.865048 # average overall mshr uncacheable latency
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-12-05 01:11:25 +01:00
system.cpu0.icache.tags.replacements 1935670 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.471469 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 38837356 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1936182 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 20.058732 # Average number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.cpu0.icache.tags.warmup_cycle 11154875500 # Cycle when the warmup percentage was hit.
2015-12-05 01:11:25 +01:00
system.cpu0.icache.tags.occ_blocks::cpu0.inst 205.076991 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 306.394478 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.400541 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.598427 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.998968 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-12-05 01:11:25 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 230 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 140 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
2014-11-12 15:05:25 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-12-05 01:11:25 +01:00
system.cpu0.icache.tags.tag_accesses 42857903 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 42857903 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 19118560 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 19718796 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 38837356 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 19118560 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 19718796 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 38837356 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 19118560 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 19718796 # number of overall hits
system.cpu0.icache.overall_hits::total 38837356 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 1007700 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 1076592 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 2084292 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 1007700 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 1076592 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 2084292 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 1007700 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 1076592 # number of overall misses
system.cpu0.icache.overall_misses::total 2084292 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14294399976 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 15401560487 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 29695960463 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 14294399976 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 15401560487 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 29695960463 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 14294399976 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 15401560487 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 29695960463 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 20126260 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 20795388 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 40921648 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 20126260 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 20795388 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 40921648 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 20126260 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 20795388 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 40921648 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050069 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.051771 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.050934 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050069 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.051771 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.050934 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050069 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.051771 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.050934 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14185.174135 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14305.847050 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14247.504890 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14185.174135 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14305.847050 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14247.504890 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14185.174135 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14305.847050 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14247.504890 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 21497 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-12-05 01:11:25 +01:00
system.cpu0.icache.blocked::no_mshrs 838 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
2015-12-05 01:11:25 +01:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.652745 # average number of cycles each access was blocked
2014-11-12 15:05:25 +01:00
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
2015-12-05 01:11:25 +01:00
system.cpu0.icache.writebacks::writebacks 1935670 # number of writebacks
system.cpu0.icache.writebacks::total 1935670 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 71379 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 76657 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 148036 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 71379 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst 76657 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 148036 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 71379 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst 76657 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 148036 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 936321 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 999935 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 1936256 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 936321 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 999935 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 1936256 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 936321 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 999935 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 1936256 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 668 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 668 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 668 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 668 # number of overall MSHR uncacheable misses
2015-12-05 01:11:25 +01:00
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12542067979 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 13487008993 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 26029076972 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12542067979 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 13487008993 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 26029076972 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12542067979 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 13487008993 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 26029076972 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 86506500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 86506500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 86506500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 86506500 # number of overall MSHR uncacheable cycles
2015-12-05 01:11:25 +01:00
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.046522 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.048084 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047316 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.046522 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.048084 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.047316 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.046522 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.048084 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.047316 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13395.051461 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13487.885706 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13442.993577 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13395.051461 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13487.885706 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13442.993577 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13395.051461 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13487.885706 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13442.993577 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 129500.748503 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 129500.748503 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 129500.748503 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 129500.748503 # average overall mshr uncacheable latency
2014-11-12 15:05:25 +01:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-12-05 01:11:25 +01:00
system.cpu1.branchPred.lookups 27854639 # Number of BP lookups
system.cpu1.branchPred.condPredicted 14561380 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 548025 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 17333975 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 13131194 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2015-12-05 01:11:25 +01:00
system.cpu1.branchPred.BTBHitPct 75.754084 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 6850254 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 29025 # Number of incorrect RAS predictions.
2014-12-23 15:31:20 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.walker.walks 58019 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 58019 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19126 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 13648 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 25245 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 32774 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 718.053945 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 4822.223013 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-16383 32332 98.65% 98.65% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-32767 325 0.99% 99.64% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-49151 64 0.20% 99.84% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::49152-65535 24 0.07% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-81919 11 0.03% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::81920-98303 5 0.02% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::98304-114687 5 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::114688-131071 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
2015-11-06 09:26:50 +01:00
system.cpu1.dtb.walker.walkWaitTime::147456-163839 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.walker.walkWaitTime::total 32774 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 13276 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 14765.931003 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 12384.741759 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 8664.538551 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767 12938 97.45% 97.45% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535 331 2.49% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-98303 4 0.03% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-163839 2 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 13276 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 91470687244 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.764325 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.447298 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1 91383080744 99.90% 99.90% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3 61332500 0.07% 99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5 13710000 0.01% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7 4721500 0.01% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9 2367000 0.00% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11 1504000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13 818000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15 2160000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17 464000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::18-19 210500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::20-21 81000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::22-23 75000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::24-25 60500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::26-27 14500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::28-29 18500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::30-31 69500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 91470687244 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 3730 68.50% 68.50% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M 1715 31.50% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 5445 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 58019 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 58019 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5445 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5445 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 63464 # Table walker requests started/completed, data/inst
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.read_hits 14422648 # DTB read hits
system.cpu1.dtb.read_misses 50091 # DTB read misses
system.cpu1.dtb.write_hits 10474825 # DTB write hits
system.cpu1.dtb.write_misses 7928 # DTB write misses
2015-11-06 09:26:50 +01:00
system.cpu1.dtb.flush_tlb 185 # Number of times complete TLB was flushed
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.flush_tlb_mva 438 # Number of times TLB was flushed by MVA
2014-10-30 05:18:29 +01:00
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.flush_entries 3615 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 797 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 1273 # Number of TLB faults due to prefetch
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.perms_faults 633 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 14472739 # DTB read accesses
system.cpu1.dtb.write_accesses 10482753 # DTB write accesses
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.hits 24897473 # DTB hits
system.cpu1.dtb.misses 58019 # DTB misses
system.cpu1.dtb.accesses 24955492 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-12-05 01:11:25 +01:00
system.cpu1.itb.walker.walks 7961 # Table walker walks requested
system.cpu1.itb.walker.walksShort 7961 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2709 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2 5049 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore 203 # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples 7758 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean 1605.503996 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 7035.957070 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-8191 7284 93.89% 93.89% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::8192-16383 191 2.46% 96.35% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::16384-24575 155 2.00% 98.35% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::24576-32767 42 0.54% 98.89% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-40959 32 0.41% 99.30% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::40960-49151 13 0.17% 99.47% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::49152-57343 14 0.18% 99.65% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::57344-65535 8 0.10% 99.76% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-73727 6 0.08% 99.83% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::73728-81919 4 0.05% 99.88% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::81920-90111 5 0.06% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::90112-98303 1 0.01% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::98304-106495 2 0.03% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::106496-114687 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 7758 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 2633 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 14904.291682 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 12612.038197 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 8468.527051 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-16383 1843 70.00% 70.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-32767 736 27.95% 97.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-49151 45 1.71% 99.66% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-65535 6 0.23% 99.89% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-81919 1 0.04% 99.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::81920-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 2633 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 35622983396 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean 0.863018 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev 0.344487 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 4885377500 13.71% 13.71% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1 30733731396 86.28% 99.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2 2597000 0.01% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3 833500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4 365000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::5 79000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 35622983396 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 1847 76.01% 76.01% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M 583 23.99% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 2430 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7961 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7961 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2430 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2430 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 10391 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 20797463 # ITB inst hits
system.cpu1.itb.inst_misses 7961 # ITB inst misses
2013-01-07 19:05:52 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
2015-11-06 09:26:50 +01:00
system.cpu1.itb.flush_tlb 185 # Number of times complete TLB was flushed
2015-12-05 01:11:25 +01:00
system.cpu1.itb.flush_tlb_mva 438 # Number of times TLB was flushed by MVA
2014-10-30 05:18:29 +01:00
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-12-05 01:11:25 +01:00
system.cpu1.itb.flush_entries 2393 # Number of entries that have been flushed from TLB
2013-01-07 19:05:52 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2015-11-06 09:26:50 +01:00
system.cpu1.itb.perms_faults 1472 # Number of TLB faults due to permissions restrictions
2013-01-07 19:05:52 +01:00
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
2015-12-05 01:11:25 +01:00
system.cpu1.itb.inst_accesses 20805424 # ITB inst accesses
system.cpu1.itb.hits 20797463 # DTB hits
system.cpu1.itb.misses 7961 # DTB misses
system.cpu1.itb.accesses 20805424 # DTB accesses
system.cpu1.numCycles 114307464 # number of cpu cycles simulated
2013-01-07 19:05:52 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-12-05 01:11:25 +01:00
system.cpu1.fetch.icacheStallCycles 41243432 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 107322713 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 27854639 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 19981448 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 67441487 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 3261241 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 132708 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 6649 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles 428 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles 247804 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 128164 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 421 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 20795394 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 377977 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 3632 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 110831676 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.164555 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.274676 # Number of instructions fetched each cycle (Total)
2013-01-07 19:05:52 +01:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2015-12-05 01:11:25 +01:00
system.cpu1.fetch.rateDist::0 81234051 73.29% 73.29% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 3972250 3.58% 76.88% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 2466525 2.23% 79.10% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 8240157 7.43% 86.54% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 1682835 1.52% 88.06% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 1118017 1.01% 89.07% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 6328104 5.71% 94.78% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 1164123 1.05% 95.83% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 4625614 4.17% 100.00% # Number of instructions fetched each cycle (Total)
2013-01-07 19:05:52 +01:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2015-12-05 01:11:25 +01:00
system.cpu1.fetch.rateDist::total 110831676 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.243682 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.938895 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 28301754 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 63497891 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 15850723 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 1704776 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 1476204 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 1967399 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 156467 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 89087170 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 506464 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 1476204 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 29234593 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 7013474 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 46686266 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 16610559 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 9810257 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 85239039 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 4158 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 1678441 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 295156 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 7089576 # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands 88402024 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 391987455 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 94729150 # Number of integer rename lookups
2015-11-06 09:26:50 +01:00
system.cpu1.rename.fp_rename_lookups 6205 # Number of floating rename lookups
2015-12-05 01:11:25 +01:00
system.cpu1.rename.CommittedMaps 74414781 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 13987243 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 1570718 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 1473274 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 9797771 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 15295971 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 11557906 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 2126909 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 2757513 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 82041945 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 1095184 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 78547336 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 91731 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 11502328 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 25183489 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 115903 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 110831676 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.708708 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.399992 # Number of insts issued each cycle
2013-01-07 19:05:52 +01:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2015-12-05 01:11:25 +01:00
system.cpu1.iq.issued_per_cycle::0 79311031 71.56% 71.56% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 10467239 9.44% 81.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 8143760 7.35% 88.35% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 6716432 6.06% 94.41% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 2458249 2.22% 96.63% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 1495385 1.35% 97.98% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 1551990 1.40% 99.38% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 479300 0.43% 99.81% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 208290 0.19% 100.00% # Number of insts issued each cycle
2013-01-07 19:05:52 +01:00
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2015-12-05 01:11:25 +01:00
system.cpu1.iq.issued_per_cycle::total 110831676 # Number of insts issued each cycle
2013-01-07 19:05:52 +01:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2015-12-05 01:11:25 +01:00
system.cpu1.iq.fu_full::IntAlu 101407 9.05% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 6 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 524965 46.83% 55.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 494582 44.12% 100.00% # attempts to use FU when none available
2013-01-07 19:05:52 +01:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2015-11-06 09:26:50 +01:00
system.cpu1.iq.FU_type_0::No_OpClass 2112 0.00% 0.00% # Type of FU issued
2015-12-05 01:11:25 +01:00
system.cpu1.iq.FU_type_0::IntAlu 52635037 67.01% 67.01% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 59537 0.08% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 1 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 4516 0.01% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.09% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 14823039 18.87% 85.97% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 11023089 14.03% 100.00% # Type of FU issued
2013-01-07 19:05:52 +01:00
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2015-12-05 01:11:25 +01:00
system.cpu1.iq.FU_type_0::total 78547336 # Type of FU issued
system.cpu1.iq.rate 0.687158 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 1120960 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.014271 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 269124936 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 94683536 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 76208716 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 14103 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 7328 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 6023 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 79658545 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 7639 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 355195 # Number of loads that had data forwarded from stores
2013-01-07 19:05:52 +01:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2015-12-05 01:11:25 +01:00
system.cpu1.iew.lsq.thread0.squashedLoads 2229396 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 2459 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 52609 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 1115131 # Number of stores squashed
2013-01-07 19:05:52 +01:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2015-12-05 01:11:25 +01:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 209977 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 80421 # Number of times an access to memory failed due to the cache being blocked
2013-01-07 19:05:52 +01:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2015-12-05 01:11:25 +01:00
system.cpu1.iew.iewSquashCycles 1476204 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 5662909 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 1045252 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 83270672 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 132429 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 15295971 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 11557906 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 563484 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 44736 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 987233 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 52609 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 252467 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 221077 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 473544 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 77944038 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 14582258 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 545399 # Number of squashed instructions skipped in execute
2013-01-07 19:05:52 +01:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
2015-12-05 01:11:25 +01:00
system.cpu1.iew.exec_nop 133543 # number of nop insts executed
system.cpu1.iew.exec_refs 25500080 # number of memory reference insts executed
system.cpu1.iew.exec_branches 14792660 # Number of branches executed
system.cpu1.iew.exec_stores 10917822 # Number of stores executed
system.cpu1.iew.exec_rate 0.681881 # Inst execution rate
system.cpu1.iew.wb_sent 77398935 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 76214739 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 39907228 # num instructions producing a value
system.cpu1.iew.wb_consumers 69371500 # num instructions consuming a value
system.cpu1.iew.wb_rate 0.666752 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.575268 # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts 11478700 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 979281 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 393571 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 108251137 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.662466 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.546689 # Number of insts commited each cycle
2013-01-07 19:05:52 +01:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2015-12-05 01:11:25 +01:00
system.cpu1.commit.committed_per_cycle::0 80272291 74.15% 74.15% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 12448333 11.50% 85.65% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 6524108 6.03% 91.68% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 2657086 2.45% 94.13% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 1374916 1.27% 95.40% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 919571 0.85% 96.25% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 1942028 1.79% 98.05% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 407210 0.38% 98.42% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 1705594 1.58% 100.00% # Number of insts commited each cycle
2013-01-07 19:05:52 +01:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2015-12-05 01:11:25 +01:00
system.cpu1.commit.committed_per_cycle::total 108251137 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 59076825 # Number of instructions committed
system.cpu1.commit.committedOps 71712716 # Number of ops (including micro ops) committed
2013-01-07 19:05:52 +01:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
2015-12-05 01:11:25 +01:00
system.cpu1.commit.refs 23509350 # Number of memory references committed
system.cpu1.commit.loads 13066575 # Number of loads committed
system.cpu1.commit.membars 397868 # Number of memory barriers committed
system.cpu1.commit.branches 14004120 # Number of branches committed
2015-11-06 09:26:50 +01:00
system.cpu1.commit.fp_insts 5946 # Number of committed floating point instructions.
2015-12-05 01:11:25 +01:00
system.cpu1.commit.int_insts 62678118 # Number of committed integer instructions.
system.cpu1.commit.function_calls 2708748 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2015-12-05 01:11:25 +01:00
system.cpu1.commit.op_class_0::IntAlu 48141082 67.13% 67.13% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 57769 0.08% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.21% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 4515 0.01% 67.22% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.22% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.22% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.22% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 13066575 18.22% 85.44% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 10442775 14.56% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2015-12-05 01:11:25 +01:00
system.cpu1.commit.op_class_0::total 71712716 # Class of committed instruction
system.cpu1.commit.bw_lim_events 1705594 # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads 176973973 # The number of ROB reads
system.cpu1.rob.rob_writes 168967567 # The number of ROB writes
system.cpu1.timesIdled 411783 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 3475788 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 3325418218 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 58998910 # Number of Instructions Simulated
system.cpu1.committedOps 71634801 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 1.937450 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.937450 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.516142 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.516142 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 84572142 # number of integer regfile reads
system.cpu1.int_regfile_writes 48524924 # number of integer regfile writes
system.cpu1.fp_regfile_reads 17041 # number of floating regfile reads
2015-11-06 09:26:50 +01:00
system.cpu1.fp_regfile_writes 13376 # number of floating regfile writes
2015-12-05 01:11:25 +01:00
system.cpu1.cc_regfile_reads 275577121 # number of cc regfile reads
system.cpu1.cc_regfile_writes 29280900 # number of cc regfile writes
system.cpu1.misc_regfile_reads 152549282 # number of misc regfile reads
system.cpu1.misc_regfile_writes 741444 # number of misc regfile writes
2015-11-06 09:26:50 +01:00
system.iobus.trans_dist::ReadReq 30172 # Transaction distribution
system.iobus.trans_dist::ReadResp 30172 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72894 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72894 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 178372 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321016 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321016 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480141 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer0.occupancy 49495000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer2.occupancy 333500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 86000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer8.occupancy 612500 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 19000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer16.occupancy 48000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer18.occupancy 8500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer23.occupancy 6442000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer24.occupancy 38187000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer25.occupancy 186272549 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iocache.tags.replacements 36413 # number of replacements
2015-12-05 01:11:25 +01:00
system.iocache.tags.tagsinuse 1.069649 # Cycle average of tags in use
2015-09-25 13:27:03 +02:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.iocache.tags.sampled_refs 36429 # Sample count of references to valid blocks.
2015-09-25 13:27:03 +02:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2015-12-05 01:11:25 +01:00
system.iocache.tags.warmup_cycle 236542797000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 1.069649 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.066853 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.066853 # Average percentage of cache occupancy
2014-10-30 05:18:29 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2015-11-06 09:26:50 +01:00
system.iocache.tags.tag_accesses 328023 # Number of tag accesses
system.iocache.tags.data_accesses 328023 # Number of data accesses
system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses
system.iocache.ReadReq_misses::total 223 # number of ReadReq misses
2015-09-25 13:27:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2015-11-06 09:26:50 +01:00
system.iocache.demand_misses::realview.ide 223 # number of demand (read+write) misses
system.iocache.demand_misses::total 223 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 223 # number of overall misses
system.iocache.overall_misses::total 223 # number of overall misses
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_miss_latency::realview.ide 28108377 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 28108377 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 4720216172 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4720216172 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 28108377 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 28108377 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 28108377 # number of overall miss cycles
system.iocache.overall_miss_latency::total 28108377 # number of overall miss cycles
2015-11-06 09:26:50 +01:00
system.iocache.ReadReq_accesses::realview.ide 223 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 223 # number of ReadReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2015-11-06 09:26:50 +01:00
system.iocache.demand_accesses::realview.ide 223 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 223 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 223 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 223 # number of overall (read+write) accesses
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2015-09-25 13:27:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 126046.533632 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 126046.533632 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130306.321003 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 130306.321003 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 126046.533632 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 126046.533632 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 126046.533632 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 126046.533632 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 748 # number of cycles access was blocked
2013-01-07 19:05:52 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-12-05 01:11:25 +01:00
system.iocache.blocked::no_mshrs 92 # number of cycles access was blocked
2013-01-07 19:05:52 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2015-12-05 01:11:25 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 8.130435 # average number of cycles each access was blocked
2013-01-07 19:05:52 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
2013-01-07 19:05:52 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
2015-09-25 13:27:03 +02:00
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
2015-11-06 09:26:50 +01:00
system.iocache.ReadReq_mshr_misses::realview.ide 223 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses
2015-09-25 13:27:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2015-11-06 09:26:50 +01:00
system.iocache.demand_mshr_misses::realview.ide 223 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 223 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 223 # number of overall MSHR misses
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_mshr_miss_latency::realview.ide 16958377 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 16958377 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2909016172 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2909016172 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 16958377 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 16958377 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 16958377 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 16958377 # number of overall MSHR miss cycles
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2015-09-25 13:27:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76046.533632 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 76046.533632 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80306.321003 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80306.321003 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 76046.533632 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 76046.533632 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 76046.533632 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76046.533632 # average overall mshr miss latency
2013-01-07 19:05:52 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-12-05 01:11:25 +01:00
system.l2c.tags.replacements 104282 # number of replacements
system.l2c.tags.tagsinuse 65109.864542 # Cycle average of tags in use
system.l2c.tags.total_refs 5144491 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 169597 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 30.333620 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 74702530500 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 48974.636998 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 36.118428 # Average occupied blocks per requestor
2015-11-06 09:26:50 +01:00
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000314 # Average occupied blocks per requestor
2015-12-05 01:11:25 +01:00
system.l2c.tags.occ_blocks::cpu0.inst 4878.666588 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2907.615962 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 60.909548 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 5701.864987 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 2550.051717 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.747294 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000551 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
2015-12-05 01:11:25 +01:00
system.l2c.tags.occ_percent::cpu0.inst 0.074443 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.044367 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000929 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.087004 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.038911 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.993498 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 84 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 65231 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 84 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.l2c.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
2015-12-05 01:11:25 +01:00
system.l2c.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.l2c.tags.age_task_id_blocks_1024::2 3229 # Occupied blocks per task id
2015-12-05 01:11:25 +01:00
system.l2c.tags.age_task_id_blocks_1024::3 8999 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 52641 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.001282 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.995346 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 45471419 # Number of tag accesses
system.l2c.tags.data_accesses 45471419 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 34274 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 7651 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 36811 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 8292 # number of ReadReq hits
system.l2c.ReadReq_hits::total 87028 # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks 705176 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 705176 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 1895159 # number of WritebackClean hits
system.l2c.WritebackClean_hits::total 1895159 # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data 43 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 48 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 91 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 29 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 25 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 54 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 74922 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 82000 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 156922 # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 926497 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 988644 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 1915141 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 279817 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 263870 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 543687 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker 34274 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 7651 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 926497 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 354739 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 36811 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 8292 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 988644 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 345870 # number of demand (read+write) hits
system.l2c.demand_hits::total 2702778 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 34274 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 7651 # number of overall hits
system.l2c.overall_hits::cpu0.inst 926497 # number of overall hits
system.l2c.overall_hits::cpu0.data 354739 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 36811 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 8292 # number of overall hits
system.l2c.overall_hits::cpu1.inst 988644 # number of overall hits
system.l2c.overall_hits::cpu1.data 345870 # number of overall hits
system.l2c.overall_hits::total 2702778 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 57 # number of ReadReq misses
2014-11-12 15:05:25 +01:00
system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
2015-12-05 01:11:25 +01:00
system.l2c.ReadReq_misses::cpu1.dtb.walker 80 # number of ReadReq misses
system.l2c.ReadReq_misses::total 138 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 1424 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1307 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2731 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 6 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 10 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 16 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 75305 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 64706 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 140011 # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst 9683 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst 11141 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total 20824 # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 8263 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 7092 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 15355 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker 57 # number of demand (read+write) misses
2014-11-12 15:05:25 +01:00
system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
2015-12-05 01:11:25 +01:00
system.l2c.demand_misses::cpu0.inst 9683 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 83568 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 80 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 11141 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 71798 # number of demand (read+write) misses
system.l2c.demand_misses::total 176328 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 57 # number of overall misses
2014-11-12 15:05:25 +01:00
system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
2015-12-05 01:11:25 +01:00
system.l2c.overall_misses::cpu0.inst 9683 # number of overall misses
system.l2c.overall_misses::cpu0.data 83568 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 80 # number of overall misses
system.l2c.overall_misses::cpu1.inst 11141 # number of overall misses
system.l2c.overall_misses::cpu1.data 71798 # number of overall misses
system.l2c.overall_misses::total 176328 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 7993500 # number of ReadReq miss cycles
2015-09-25 13:27:03 +02:00
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 132500 # number of ReadReq miss cycles
2015-12-05 01:11:25 +01:00
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 10773500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 18899500 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 1555000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 1963000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 3518000 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 245000 # number of SCUpgradeReq miss cycles
2015-11-06 09:26:50 +01:00
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 644500 # number of SCUpgradeReq miss cycles
2015-12-05 01:11:25 +01:00
system.l2c.SCUpgradeReq_miss_latency::total 889500 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 10060663000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 8652600500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 18713263500 # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1288661500 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 1478928499 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total 2767589999 # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 1116500000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 978509000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 2095009000 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 7993500 # number of demand (read+write) miss cycles
2015-09-25 13:27:03 +02:00
system.l2c.demand_miss_latency::cpu0.itb.walker 132500 # number of demand (read+write) miss cycles
2015-12-05 01:11:25 +01:00
system.l2c.demand_miss_latency::cpu0.inst 1288661500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 11177163000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 10773500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 1478928499 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 9631109500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 23594761999 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 7993500 # number of overall miss cycles
2015-09-25 13:27:03 +02:00
system.l2c.overall_miss_latency::cpu0.itb.walker 132500 # number of overall miss cycles
2015-12-05 01:11:25 +01:00
system.l2c.overall_miss_latency::cpu0.inst 1288661500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 11177163000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 10773500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 1478928499 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 9631109500 # number of overall miss cycles
system.l2c.overall_miss_latency::total 23594761999 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 34331 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 7652 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 36891 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 8292 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 87166 # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks 705176 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 705176 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks 1895159 # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total 1895159 # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 1467 # number of UpgradeReq accesses(hits+misses)
2015-11-06 09:26:50 +01:00
system.l2c.UpgradeReq_accesses::cpu1.data 1355 # number of UpgradeReq accesses(hits+misses)
2015-12-05 01:11:25 +01:00
system.l2c.UpgradeReq_accesses::total 2822 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 35 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 35 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 70 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 150227 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 146706 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 296933 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst 936180 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst 999785 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total 1935965 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 288080 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 270962 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 559042 # number of ReadSharedReq accesses(hits+misses)
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system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.028683 # miss rate for ReadSharedReq accesses
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system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 140236.842105 # average ReadReq miss latency
2015-09-25 13:27:03 +02:00
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 132500 # average ReadReq miss latency
2015-12-05 01:11:25 +01:00
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 134668.750000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 136952.898551 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1091.994382 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1501.912777 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 1288.172830 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 40833.333333 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 64450 # average SCUpgradeReq miss latency
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system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 137973.632262 # average ReadSharedReq miss latency
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2015-09-25 13:27:03 +02:00
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2015-12-05 01:11:25 +01:00
system.l2c.demand_avg_miss_latency::cpu0.inst 133084.942683 # average overall miss latency
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system.l2c.demand_avg_miss_latency::cpu1.inst 132746.476887 # average overall miss latency
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2015-09-25 13:27:03 +02:00
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 132500 # average overall miss latency
2015-12-05 01:11:25 +01:00
system.l2c.overall_avg_miss_latency::cpu0.inst 133084.942683 # average overall miss latency
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system.l2c.overall_avg_miss_latency::total 133811.771239 # average overall miss latency
2014-11-12 15:05:25 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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2015-12-05 01:11:25 +01:00
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2015-11-06 09:26:50 +01:00
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2015-12-05 01:11:25 +01:00
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2015-11-06 09:26:50 +01:00
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2015-12-05 01:11:25 +01:00
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2015-11-06 09:26:50 +01:00
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2015-12-05 01:11:25 +01:00
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2014-11-12 15:05:25 +01:00
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2015-12-05 01:11:25 +01:00
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2015-12-05 01:11:25 +01:00
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2015-12-05 01:11:25 +01:00
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2015-09-25 13:27:03 +02:00
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2015-12-05 01:11:25 +01:00
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2015-07-03 16:15:03 +02:00
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2015-12-05 01:11:25 +01:00
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2015-09-25 13:27:03 +02:00
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2015-12-05 01:11:25 +01:00
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2015-09-25 13:27:03 +02:00
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2015-12-05 01:11:25 +01:00
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2015-09-25 13:27:03 +02:00
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2015-12-05 01:11:25 +01:00
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2015-09-25 13:27:03 +02:00
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2015-12-05 01:11:25 +01:00
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2015-09-25 13:27:03 +02:00
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2015-12-05 01:11:25 +01:00
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2015-11-06 09:26:50 +01:00
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2015-12-05 01:11:25 +01:00
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2015-11-06 09:26:50 +01:00
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2015-12-05 01:11:25 +01:00
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system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.010333 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011139 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010750 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.028461 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.025878 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.027209 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001660 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000131 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010333 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.190515 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.002169 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011139 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.171711 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.061189 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001660 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000131 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010333 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.190515 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.002169 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011139 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.171711 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.061189 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 130236.842105 # average ReadReq mshr miss latency
2015-09-25 13:27:03 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 122500 # average ReadReq mshr miss latency
2015-12-05 01:11:25 +01:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 124668.750000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 126952.898551 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70823.384831 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70782.707728 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70803.917613 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71250 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 70600 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70843.750000 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 123598.871257 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123721.764597 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 123655.666341 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123142.753773 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122754.960851 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122935.226515 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 125259.726796 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128143.111808 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126588.915916 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130236.842105 # average overall mshr miss latency
2015-09-25 13:27:03 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 122500 # average overall mshr miss latency
2015-12-05 01:11:25 +01:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123142.753773 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123761.945536 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 124668.750000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122754.960851 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124154.047798 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 123826.407292 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130236.842105 # average overall mshr miss latency
2015-09-25 13:27:03 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 122500 # average overall mshr miss latency
2015-12-05 01:11:25 +01:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123142.753773 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123761.945536 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 124668.750000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122754.960851 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124154.047798 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 123826.407292 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113784.426647 # average ReadReq mshr uncacheable latency
2015-12-05 01:11:25 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188341.659324 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191332.162921 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 188315.501368 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158646.886904 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 190033.327940 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172710.943164 # average WriteReq mshr uncacheable latency
2015-11-06 09:26:50 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113784.426647 # average overall mshr uncacheable latency
2015-12-05 01:11:25 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173260.015344 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 190773.453267 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 181066.220376 # average overall mshr uncacheable latency
2014-11-12 15:05:25 +01:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::ReadReq 31797 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.membus.trans_dist::ReadResp 68179 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::WriteReq 27588 # Transaction distribution
system.membus.trans_dist::WriteResp 27588 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.membus.trans_dist::WritebackDirty 131704 # Transaction distribution
system.membus.trans_dist::CleanEvict 8781 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4622 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 16 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4638 # Transaction distribution
system.membus.trans_dist::ReadExReq 138120 # Transaction distribution
system.membus.trans_dist::ReadExResp 138120 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 36383 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2082 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 473019 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 580601 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108889 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 108889 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.membus.pkt_count::total 689490 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4164 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17310428 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 17474421 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.membus.pkt_size::total 19791541 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 494 # Total snoops (count)
system.membus.snoop_fanout::samples 415457 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2015-12-05 01:11:25 +01:00
system.membus.snoop_fanout::1 415457 100.00% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2015-12-05 01:11:25 +01:00
system.membus.snoop_fanout::total 415457 # Request fanout histogram
system.membus.reqLayer0.occupancy 95427000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-07-03 16:15:03 +02:00
system.membus.reqLayer1.occupancy 17812 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.membus.reqLayer2.occupancy 1716000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.membus.reqLayer5.occupancy 922382161 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.membus.respLayer2.occupancy 1017668838 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.membus.respLayer3.occupancy 64149362 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2014-11-12 15:05:25 +01:00
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2015-12-05 01:11:25 +01:00
system.toL2Bus.snoop_filter.tot_requests 5623218 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 2831016 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 48178 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2015-11-06 09:26:50 +01:00
system.toL2Bus.snoop_filter.tot_snoops 419 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 419 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2015-12-05 01:11:25 +01:00
system.toL2Bus.trans_dist::ReadReq 148339 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2643775 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.toL2Bus.trans_dist::WriteReq 27588 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 27588 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.toL2Bus.trans_dist::WritebackDirty 836888 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 1895159 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 151681 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 2822 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 70 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 2892 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 296933 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 296933 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 1936256 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 559265 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5768715 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2683173 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41220 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 162488 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 8655596 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 245234624 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 100105653 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 63776 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 284888 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 345688941 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 206956 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 3148204 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.027216 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.162713 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-12-05 01:11:25 +01:00
system.toL2Bus.snoop_fanout::0 3062522 97.28% 97.28% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 85682 2.72% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2015-12-05 01:11:25 +01:00
system.toL2Bus.snoop_fanout::total 3148204 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 5535720994 # Layer occupancy (ticks)
2015-11-06 09:26:50 +01:00
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.toL2Bus.snoopLayer0.occupancy 269377 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.toL2Bus.respLayer0.occupancy 2907347058 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.toL2Bus.respLayer1.occupancy 1330807539 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.toL2Bus.respLayer2.occupancy 25313424 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.toL2Bus.respLayer3.occupancy 91701122 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2013-01-07 19:05:52 +01:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
2015-09-25 13:27:03 +02:00
system.cpu0.kern.inst.quiesce 3037 # number of quiesce instructions executed
2013-01-07 19:05:52 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
