Commit graph

127 commits

Author SHA1 Message Date
Nilay Vaish
c4e7e18eeb ruby: add option for number of transitions per cycle
The number of transitions per cycle that a controller can carry out is
a proxy for the number of ports that a controller has. This value is
currently 32 which is way too high. The patch introduces an option
for the number of ports and uses this option in the protocol files
to set the number of transitions. The default value is being set to
4. None of the se regressions change. Ruby stats for the fs regression
change and are being updated.
2013-08-20 11:32:31 -05:00
Andreas Hansson
49d88f08b0 mem: Change AbstractMemory defaults to match the common case
This patch changes the default parameter value of conf_table_reported
to match the common case. It also simplifies the regression and config
scripts to reflect this change.
2013-08-19 03:52:33 -04:00
Akash Bagdia
e7e17f92db power: Add voltage domains to the clock domains
This patch adds the notion of voltage domains, and groups clock
domains that operate under the same voltage (i.e. power supply) into
domains. Each clock domain is required to be associated with a voltage
domain, and the latter requires the voltage to be explicitly set.

A voltage domain is an independently controllable voltage supply being
provided to section of the design. Thus, if you wish to perform
dynamic voltage scaling on a CPU, its clock domain should be
associated with a separate voltage domain.

The current implementation of the voltage domain does not take into
consideration cases where there are derived voltage domains running at
ratio of native voltage domains, as with the case where there can be
on-chip buck/boost (charge pumps) voltage regulation logic.

The regression and configuration scripts are updated with a generic
voltage domain for the system, and one for the CPUs.
2013-08-19 03:52:28 -04:00
Andreas Hansson
a8480fe1c3 config: Move the memory instantiation outside FSConfig
This patch moves the instantiation of the memory controller outside
FSConfig and instead relies on the mem_ranges to pass the information
to the caller (e.g. fs.py or one of the regression scripts). The main
motivation for this change is to expose the structural composition of
the memory system and allow more tuning and configuration without
adding a large number of options to the makeSystem functions.

The patch updates the relevant example scripts to maintain the current
functionality. As the order that ports are connected to the memory bus
changes (in certain regresisons), some bus stats are shuffled
around. For example, what used to be layer 0 is now layer 1.

Going forward, options will be added to support the addition of
multi-channel memory controllers.
2013-08-19 03:52:27 -04:00
Nilay Vaish
af58313fd6 regressions: update a couple of configs
The configs for pc-simple-timing-ruby, t1000-simple-atomic had not been
updated correctly in the patch 6e6cefc1db1f.
2013-07-02 10:10:58 -05:00
Akash Bagdia
7d7ab73862 sim: Add the notion of clock domains to all ClockedObjects
This patch adds the notion of source- and derived-clock domains to the
ClockedObjects. As such, all clock information is moved to the clock
domain, and the ClockedObjects are grouped into domains.

The clock domains are either source domains, with a specific clock
period, or derived domains that have a parent domain and a divider
(potentially chained). For piece of logic that runs at a derived clock
(a ratio of the clock its parent is running at) the necessary derived
clock domain is created from its corresponding parent clock
domain. For now, the derived clock domain only supports a divider,
thus ensuring a lower speed compared to its parent. Multiplier
functionality implies a PLL logic that has not been modelled yet
(create a separate clock instead).

The clock domains should be used as a mechanism to provide a
controllable clock source that affects clock for every clocked object
lying beneath it. The clock of the domain can (in a future patch) be
controlled by a handler responsible for dynamic frequency scaling of
the respective clock domains.

All the config scripts have been retro-fitted with clock domains. For
the System a default SrcClockDomain is created. For CPUs that run at a
different speed than the system, there is a seperate clock domain
created. This domain incorporates the CPU and the associated
caches. As before, Ruby runs under its own clock domain.

The clock period of all domains are pre-computed, such that no virtual
functions or multiplications are needed when calling
clockPeriod. Instead, the clock period is pre-computed when any
changes occur. For this to be possible, each clock domain tracks its
children.
2013-06-27 05:49:49 -04:00
Andreas Hansson
4de3205afa config: Add a BaseSESystem builder for re-use in regressions
This patch extends the existing system builders to also include a
syscall-emulation builder. This builder is deployed in all
syscall-emulation regressions that do not involve Ruby,
i.e. o3-timing, simple-timing and simple-atomic, as well as the
multi-processor regressions o3-timing-mp, simple-timing-mp and
simple-atomic-mp (the latter are only used by SPARC at this point).

The values chosen for the cache sizes match those that were used in
the existing config scripts (despite being on the large
side). Similarly, a mem_class parameter is added to the builder base
class to enable simple-atomic to use SimpleMemory and o3-timing to use
the default DDR3 configuration.

Due to the different order the ports are connected, the bus stats get
shuffled around for the multi-processor regressions. A separate patch
bumps the port indices. Besides this, all behaviour is exactly the
same.
2013-06-27 05:49:49 -04:00
Akash Bagdia
076d04a653 config: Add a system clock command-line option
This patch adds a 'sys_clock' command-line option and use it to assign
clocks to the system during instantiation.

As part of this change, the default clock in the System class is
removed and whenever a system is instantiated a system clock value
must be set. A default value is provided for the command-line option.

The configs and tests are updated accordingly.
2013-06-27 05:49:49 -04:00
Akash Bagdia
7eccb1b779 config: Remove redundant explicit setting of default clocks
This patch removes the explicit setting of the clock period for
certain instances of CoherentBus, NonCoherentBus and IOCache where the
specified clock is same as the default value of the system clock. As
all the values used are the defaults, there are no performance
changes. There are similar cases where the toL2Bus is set to use the
parent CPU clock which is already the default behaviour.

The main motivation for these simplifications is to ease the
introduction of clock domains.
2013-06-27 05:49:49 -04:00
Andreas Hansson
3bc4ecdcb4 mem: More descriptive DRAM config names
This patch changes the class names of the variuos DRAM configurations
to better reflect what memory they are based on. The speed and
interface width is now part of the name, and also the alias that is
used to select them on the command line.

Some minor changes are done to the actual parameters, to better
reflect the named configurations. As a result of these changes the
regressions change slightly and the stats will be bumped in a separate
patch.
2013-05-30 12:54:14 -04:00
Andreas Hansson
9f8b1aec49 config: Added memory type to t1000 regression
This patch adds the memory type parameter to the t1000 regression.
2013-04-28 17:14:39 -04:00
Nilay Vaish
c2d799c6b0 x86: regressions: add switcher full test 2013-04-23 00:03:09 -05:00
Andreas Hansson
3477d60d5c config: Add a mem-type config option to se/fs scripts
This patch enables selection of the memory controller class through a
mem-type command-line option. Behind the scenes, this option is
treated much like the cpu-type, and a similar framework is used to
resolve the valid options, and translate the short-hand description to
a valid class.

The regression scripts are updated with a hardcoded memory class for
the moment. The best solution going forward is probably to get the
memory out of the makeSystem functions, but Ruby complicates things as
it does not connect the memory controller to the membus.

--HG--
rename : configs/common/CpuConfig.py => configs/common/MemConfig.py
2013-04-22 13:20:33 -04:00
Andreas Sandberg
dc83d23425 tests: Add support for testing KVM-based CPUs
This changeset adds support for initializing a KVM VM in the
BaseSystem test class and adds the following methods in run.py:

require_file -- Test if a file exists and abort/skip if not.
require_kvm -- Test if KVM support has been compiled into gem5 (i.e.,
	       BaseKvmCPU exists) and the KVM device exists on the
	       host.
2013-04-22 13:20:32 -04:00
Andreas Sandberg
5f2361f3af arm: Enable support for triggering a sim panic on kernel panics
Add the options 'panic_on_panic' and 'panic_on_oops' to the
LinuxArmSystem SimObject. When these option are enabled, the simulator
panics when the guest kernel panics or oopses. Enable panic on panic
and panic on oops in ARM-based test cases.
2013-04-22 13:20:31 -04:00
Nilay Vaish
c061819890 ruby: remove the functional copy of memory in se mode
This patch removes the functional copy of the memory that was maintained in
the se mode. Now ruby itself will provide the data.
2013-03-06 21:53:57 -06:00
Andreas Sandberg
e5dca84c3f config: Move CPU handover logic to m5.switchCpus()
CPU switching consists of the following steps:
 1. Drain the system
 2. Switch out old CPUs (cpu.switchOut())
 3. Change the system timing mode to the mode the new CPUs require
 4. Flush caches if switching to hardware virtualization
 5. Inform new CPUs of the handover (cpu.takeOverFrom())
 6. Resume the system

m5.switchCpus() previously only did step 2 & 5. Since information
about the new processors' memory system requirements is now exposed,
do all of the steps above.

This patch adds automatic memory system switching and flush (if
needed) to switchCpus(). Additionally, it adds optional draining to
switchCpus(). This has the following implications:

* changeToTiming and changeToAtomic are no longer needed, so they have
  been removed.

* changeMemoryMode is only used internally, so it is has been renamed
  to be private.

* switchCpus requires a reference to the system containing the CPUs as
  its first parameter.

WARNING: This changeset breaks compatibility with existing
configuration scripts since it changes the signature of
m5.switchCpus().
2013-02-15 17:40:08 -05:00
Andreas Hansson
c4898b15bc mem: Add DDR3 and LPDDR2 DRAM controller configurations
This patch moves the default DRAM parameters from the SimpleDRAM class
to two different subclasses, one for DDR3 and one for LPDDR2. More can
be added as we go forward.

The regressions that previously used the SimpleDRAM are now using
SimpleDDR3 as this is the most similar configuration.
2013-01-31 07:49:14 -05:00
Andreas Sandberg
5fb00e1df6 tests: Add CPU switching tests
This changeset adds a set of tests that stress the CPU switching
code. It adds the following test configurations:

 * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3)
 * realview-switcheroo-atomic -- ARM system (atomic<->atomic)
 * realview-switcheroo-timing -- ARM system (timing<->timing)
 * realview-switcheroo-o3 -- ARM system (O3<->O3)
 * realview-switcheroo-full -- ARM system (atomic, timing, O3)

Reference data is provided for the 10.linux-boot test case. All of the
tests trigger a CPU switch once per millisecond during the boot
process.

The in-order CPU model was not included in any of the tests as it does
not support CPU handover.
2013-01-07 13:05:52 -05:00
Andreas Hansson
e65de3f5ca config: Do not use hardcoded physmem in fs script
This patch generalises the address range resolution for the I/O cache
and I/O bridge such that they do not assume a single memory. The patch
involves adding a parameter to the system which is then defined based
on the memories that are to be visible from the I/O subsystem, whether
behind a cache or a bridge.

The change is needed to allow interleaved memory controllers in the
system.
2013-01-07 13:05:38 -05:00
Andreas Hansson
1da209140c cpu: Add support for protobuf input for the trace generator
This patch adds support for reading input traces encoded using
protobuf according to what is done in the CommMonitor.

A follow-up patch adds a Python script that can be used to convert the
previously used ASCII traces to protobuf equivalents. The appropriate
regression input is updated as part of this patch.
2013-01-07 13:05:37 -05:00
Andreas Hansson
f456c7983d mem: Add tracing support in the communication monitor
This patch adds packet tracing to the communication monitor using a
protobuf as the mechanism for creating the trace.

If no file is specified, then the tracing is disabled. If a file is
specified, then for every packet that is successfully sent, a protobuf
message is serialized to the file.
2013-01-07 13:05:37 -05:00
Ali Saidi
90bd20aae2 tests: Always specify memory mode in every test system.
Previous to this change we didn't always set the memory mode which worked as
long as we never attempted to switch CPUs or checked that a CPU was in a
memory system with the correct mode. Future changes will make CPUs verify
that they're operating in the correct mode and thus we need to always set it.
2013-01-07 13:05:33 -05:00
Andreas Sandberg
f32f372455 tests: Create base classes to encapsulate common test configurations
Most of the test cases currently contain a large amount of duplicated
boiler plate code. This changeset introduces a set of classes that
encapsulates most of the functionality when setting up a test
configuration.

The following base classes are introduced:
* BaseSystem - Basic system configuration that can be used for both
               SE and FS simulation.

* BaseFSSystem - Basic FS configuration uni-processor and multi-processor
                 configurations.

* BaseFSSystemUniprocessor - Basic FS configuration for uni-processor
                             configurations. This is provided as a way
			     to make existing test cases backwards
			     compatible.

Architecture specific implementations are provided for ARM, Alpha, and
X86.
2013-01-07 13:05:33 -05:00
Andreas Hansson
4e984e0962 stats: Update stats for fixed simple-atomic-mp config
This patch updates the stats for the regressions that were affected by
the typo in the simple-atomic-mp configuration.
2012-10-31 08:39:45 -04:00
Andreas Hansson
ab0bd51315 config: Fix a typo in the simple-atomic-mp configuration
This patch fixes a minor typo that managed to sneak into the
simple-atomic-mp regression configuration.
2012-10-31 08:39:43 -04:00
Andreas Hansson
9cbe1cb653 config: Unify caches used in regressions and adjust L2 MSHRs
This patch unified the L1 and L2 caches used throughout the
regressions instead of declaring different, but very similar,
configurations in the different scripts.

The patch also changes the default L2 configuration to match what it
used to be for the fs and se scripts (until the last patch that
updated the regressions to also make use of the cache config). The
MSHRs and targets per MSHR are now set to a more realistic default of
20 and 12, respectively.

As a result of both the aforementioned changes, many of the regression
stats are changed. A follow-on patch will bump the stats.
2012-10-30 07:44:08 -04:00
Andreas Hansson
651de2d9af config: Fix the cache class naming in regression scripts
This patch unifies the naming of the default L1 and L2 caches in the
regression configs to be in line with what is used in the se and fs
scripts.
2012-10-26 06:42:42 -04:00
Andreas Hansson
66e331c7bb config: Use SimpleDRAM in full-system, and with o3 and inorder
This patch favours using SimpleDRAM with the default timing instead of
SimpleMemory for all regressions that involve the o3 or inorder CPU,
or are full system (in other words, where the actual performance of
the memory is important for the overall performance).

Moving forward, the solution for FSConfig and the users of fs.py and
se.py is probably something similar to what we use to choose the CPU
type. I envision a few pre-set configurations SimpleLPDDR2,
SimpleDDR3, etc that can be choosen by a dram_type option. Feedback on
this part is welcome.

This patch changes plenty stats and adds all the DRAM controller
related stats. A follow-on patch updates the relevant statistics. The
total run-time for the entire regression goes up with ~5% with this
patch due to the added complexity of the SimpleDRAM model. This is a
concious trade-off to ensure that the model is properly tested.
2012-10-25 13:14:38 -04:00
Andreas Hansson
d22796c03c config: Use shared cache config for regressions
This patch uses the common L1, L2 and IOCache configuration for the
regressions that all share the same cache parameters. There are a few
regressions that use a slightly different configuration (memtest,
o3-timing=mp, simple-atomic-mp and simple-timing-mp), and the latter
are not changed in this patch. They will be updated in a future patch.

The common cache configurations are changed to match the ones used in
the regressions, and are slightly changed with respect to what they
were. Hopefully this means we can converge on a common base
configuration, used both in the normal user configurations and
regressions.

As only regressions that shared the same cache configuration are
updated, no regressions are affected.
2012-10-25 04:32:44 -04:00
Andreas Hansson
88554790c3 Mem: Use cycles to express cache-related latencies
This patch changes the cache-related latencies from an absolute time
expressed in Ticks, to a number of cycles that can be scaled with the
clock period of the caches. Ultimately this patch serves to enable
future work that involves dynamic frequency scaling. As an immediate
benefit it also makes it more convenient to specify cache performance
without implicitly assuming a specific CPU core operating frequency.

The stat blocked_cycles that actually counter in ticks is now updated
to count in cycles.

As the timing is now rounded to the clock edges of the cache, there
are some regressions that change. Plenty of them have very minor
changes, whereas some regressions with a short run-time are perturbed
quite significantly. A follow-on patch updates all the statistics for
the regressions.
2012-10-15 08:10:54 -04:00
Andreas Hansson
072a91ee51 Configs: Set the memtest clock to a reasonable value
This patch changes the memtest clock from 1THz (the default) to 2GHz,
similar to the CPUs in the other regressions. This is useful as the
caches will adopt the same clock as the CPU. The bus clock rate is
scaled accordingly, and the L1-L2 bus is kept at the CPU clock while
the memory bus is at half that frequency.

A separate patch updates the affected stats.
2012-10-15 08:09:57 -04:00
Andreas Hansson
3cf733bcc0 Regression: Use addTwoLevelCacheHierarchy in configs
This patch unifies the full-system regression config scripts and uses
the BaseCPU convenience method addTwoLevelCacheHierarchy to connect up
the L1s and L2, and create the bus inbetween.

The patch is a step on the way to use the clock period to express the
cache latencies, as the CPU is now the parent of the L1, L2 and L1-L2
bus, and these modules thus use the CPU clock.

The patch does not change the value of any stats, but plenty names,
and a follow-up patch contains the update to the stats, chaning
system.l2c to system.cpu.l2cache.
2012-10-15 08:07:09 -04:00
Mrinmoy Ghosh
6fc0094337 Cache: add a response latency to the caches
In the current caches the hit latency is paid twice on a miss. This patch lets
a configurable response latency be set of the cache for the backward path.
2012-09-25 11:49:41 -05:00
Andreas Hansson
103a4a049c Regression: Set the clock for twosys-tsunami CPUs
This patch merely adds a clock other than the default 1 Tick for the
CPUs of both the test system and drive system for the twosys-tsunami
regression.

The CPU frequency of the driver system is choosed to be twice that of
the test system to ensure it is not the bottleneck (although in this
case it mostly serves as a demonstration of a two-system setup),
2012-09-24 18:03:41 -04:00
Andreas Hansson
6427342318 SimpleDRAM: A basic SimpleDRAM regression
--HG--
rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py
rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg
rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc
2012-09-21 11:48:14 -04:00
Andreas Hansson
efea870fce TrafficGen: Add a basic traffic generator regression
This patch adds a basic regression for the traffic generator. The
regression also serves as an example of the file formats used. More
complex regressions that make use of a DRAM controller model will
follow shortly.
2012-09-21 11:48:11 -04:00
Andreas Hansson
a6074016e2 Bridge: Remove NACKs in the bridge and unify with packet queue
This patch removes the NACKing in the bridge, as the split
request/response busses now ensure that protocol deadlocks do not
occur, i.e. the message-dependency chain is broken by always allowing
responses to make progress without being stalled by requests. The
NACKs had limited support in the system with most components ignoring
their use (with a suitable call to panic), and as the NACKs are no
longer needed to avoid protocol deadlocks, the cleanest way is to
simply remove them.

The bridge is the starting point as this is the only place where the
NACKs are created. A follow-up patch will remove the code that deals
with NACKs in the endpoints, e.g. the X86 table walker and DMA
port. Ultimately the type of packet can be complete removed (until
someone sees a need for modelling more complex protocols, which can
now be done in parts of the system since the port and interface is
split).

As a consequence of the NACK removal, the bridge now has to send a
retry to a master if the request or response queue was full on the
first attempt. This change also makes the bridge ports very similar to
QueuedPorts, and a later patch will change the bridge to use these. A
first step in this direction is taken by aligning the name of the
member functions, as done by this patch.

A bit of tidying up has also been done as part of the simplifications.

Surprisingly, this patch has no impact on any of the
regressions. Hence, there was never any NACKs issued. In a follow-up
patch I would suggest changing the size of the bridge buffers set in
FSConfig.py to also test the situation where the bridge fills up.
2012-08-22 11:39:58 -04:00
Andreas Hansson
5e7f174b74 Regression: Fix topologies path in failing pc-simple-timing-ruby
This patch updates the path to the Ruby topologies and thus fixes a
failing regression.
2012-07-21 17:24:01 -04:00
Andreas Hansson
f00cba34eb Mem: Make SimpleMemory single ported
This patch changes the simple memory to have a single slave port
rather than a vector port. The simple memory makes no attempts at
modelling the contention between multiple ports, and any such
multiplexing and demultiplexing could be done in a bus (or crossbar)
outside the memory controller. This scenario also matches with the
ongoing work on a SimpleDRAM model, which will be a single-ported
single-channel controller that can be used in conjunction with a bus
(or crossbar) to create a multi-port multi-channel controller.

There are only very few regressions that make use of the vector port,
and these are all for functional accesses only. To facilitate these
cases, memtest and memtest-ruby have been updated to also have a
"functional" bus to perform the (de)multiplexing of the functional
memory accesses.
2012-07-12 12:56:13 -04:00
Brad Beckmann
b00fe08cc9 regress: ruby stat additions and config changes 2012-07-10 22:51:55 -07:00
Marc Orr
02f8178b44 Regression: Fix some bugs in simple-timing-mp-ruby.py. 2012-06-11 03:16:43 -04:00
Andreas Hansson
0d32940711 Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.

A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.

A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.

The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.

A bit of minor tidying up has also been done.

--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 13:30:04 -04:00
Nilay Vaish
86f248e2a7 Regression: Add a test for x86 timing full system ruby simulation 2012-04-25 22:43:36 -05:00
Brad Beckmann
697fd8987b regress: ruby random tester and hammer stats updates 2012-04-06 16:16:24 -07:00
Brad Beckmann
f050ebe3a8 MOESI_hammer: fixed bug with single cpu + flushes, then modified the regression tester to check this functionality 2012-04-06 13:47:06 -07:00
Andreas Hansson
b00949d88b MEM: Enable multiple distributed generalized memories
This patch removes the assumption on having on single instance of
PhysicalMemory, and enables a distributed memory where the individual
memories in the system are each responsible for a single contiguous
address range.

All memories inherit from an AbstractMemory that encompasses the basic
behaviuor of a random access memory, and provides untimed access
methods. What was previously called PhysicalMemory is now
SimpleMemory, and a subclass of AbstractMemory. All future types of
memory controllers should inherit from AbstractMemory.

To enable e.g. the atomic CPU and RubyPort to access the now
distributed memory, the system has a wrapper class, called
PhysicalMemory that is aware of all the memories in the system and
their associated address ranges. This class thus acts as an
infinitely-fast bus and performs address decoding for these "shortcut"
accesses. Each memory can specify that it should not be part of the
global address map (used e.g. by the functional memories by some
testers). Moreover, each memory can be configured to be reported to
the OS configuration table, useful for populating ATAG structures, and
any potential ACPI tables.

Checkpointing support currently assumes that all memories have the
same size and organisation when creating and resuming from the
checkpoint. A future patch will enable a more flexible
re-organisation.

--HG--
rename : src/mem/PhysicalMemory.py => src/mem/AbstractMemory.py
rename : src/mem/PhysicalMemory.py => src/mem/SimpleMemory.py
rename : src/mem/physical.cc => src/mem/abstract_mem.cc
rename : src/mem/physical.hh => src/mem/abstract_mem.hh
rename : src/mem/physical.cc => src/mem/simple_mem.cc
rename : src/mem/physical.hh => src/mem/simple_mem.hh
2012-04-06 13:46:31 -04:00
Nilay Vaish
390cfc7be9 Config: Change the way options are added
I am not too happy with the way options are added in files se.py and fs.py
currently. This patch moves all the options to the file Options.py, functions
from which are called when required.
2012-03-28 11:01:53 -05:00
Geoffrey Blake
da0d67c3d6 CheckerCPU: Make some basic regression tests for CheckerCPU
Adds regression tests for the CheckerCPU. ARM ISA support
only at this point.
2012-03-09 09:59:28 -05:00
Ali Saidi
eaa994e7f6 cache: Allow main memory to be at disjoint address ranges. 2012-03-09 09:59:25 -05:00