Andreas Hansson f00cba34eb Mem: Make SimpleMemory single ported ... This patch changes the simple memory to have a single slave port rather than a vector port. The simple memory makes no attempts at modelling the contention between multiple ports, and any such multiplexing and demultiplexing could be done in a bus (or crossbar) outside the memory controller. This scenario also matches with the ongoing work on a SimpleDRAM model, which will be a single-ported single-channel controller that can be used in conjunction with a bus (or crossbar) to create a multi-port multi-channel controller. There are only very few regressions that make use of the vector port, and these are all for functional accesses only. To facilitate these cases, memtest and memtest-ruby have been updated to also have a "functional" bus to perform the (de)multiplexing of the functional memory accesses.		2012-07-12 12:56:13 -04:00
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inorder-timing.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
memtest-ruby.py	Mem: Make SimpleMemory single ported	2012-07-12 12:56:13 -04:00
memtest.py	Mem: Make SimpleMemory single ported	2012-07-12 12:56:13 -04:00
o3-timing-checker.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
o3-timing-mp-ruby.py	regress: ruby stat additions and config changes	2012-07-10 22:51:55 -07:00
o3-timing-mp.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
o3-timing-ruby.py	regress: ruby stat additions and config changes	2012-07-10 22:51:55 -07:00
o3-timing.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
pc-o3-timing.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
pc-simple-atomic.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
pc-simple-timing-ruby.py	regress: ruby stat additions and config changes	2012-07-10 22:51:55 -07:00
pc-simple-timing.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
realview-o3-checker.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
realview-o3-dual.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
realview-o3.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
realview-simple-atomic-dual.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
realview-simple-atomic.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
realview-simple-timing-dual.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
realview-simple-timing.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
rubytest-ruby.py	regress: ruby stat additions and config changes	2012-07-10 22:51:55 -07:00
simple-atomic-dummychecker.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
simple-atomic-mp-ruby.py	regress: ruby stat additions and config changes	2012-07-10 22:51:55 -07:00
simple-atomic-mp.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
simple-atomic.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
simple-timing-mp-ruby.py	regress: ruby stat additions and config changes	2012-07-10 22:51:55 -07:00
simple-timing-mp.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
simple-timing-ruby.py	regress: ruby stat additions and config changes	2012-07-10 22:51:55 -07:00
simple-timing.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
t1000-simple-atomic.py	Fix the SPARC fs regression by adding a call to createInterruptController.	2012-03-08 02:10:03 -08:00
tsunami-inorder.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
tsunami-o3-dual.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
tsunami-o3.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
tsunami-simple-atomic-dual.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
tsunami-simple-atomic.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
tsunami-simple-timing-dual.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
tsunami-simple-timing.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
twosys-tsunami-simple-atomic.py	CPU: Check that the interrupt controller is created when needed	2012-03-02 09:21:48 -05:00