ruby: add option for number of transitions per cycle
The number of transitions per cycle that a controller can carry out is a proxy for the number of ports that a controller has. This value is currently 32 which is way too high. The patch introduces an option for the number of ports and uses this option in the protocol files to set the number of transitions. The default value is being set to 4. None of the se regressions change. Ruby stats for the fs regression change and are being updated.
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8 changed files with 25 additions and 0 deletions
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@ -98,6 +98,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
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options.cpu_type == "detailed"),
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prefetcher = prefetcher,
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ruby_system = ruby_system,
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transitions_per_cycle=options.ports,
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enable_prefetch = False)
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cpu_seq = RubySequencer(version = i,
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@ -133,6 +134,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
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l2_cntrl = L2Cache_Controller(version = i,
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cntrl_id = cntrl_count,
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L2cache = l2_cache,
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transitions_per_cycle=options.ports,
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ruby_system = ruby_system)
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exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
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@ -172,6 +174,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
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use_map =
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options.use_map),
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memBuffer = mem_cntrl,
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transitions_per_cycle = options.ports,
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ruby_system = ruby_system)
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exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
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@ -189,6 +192,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
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dma_cntrl = DMA_Controller(version = i,
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cntrl_id = cntrl_count,
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dma_sequencer = dma_seq,
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transitions_per_cycle = options.ports,
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ruby_system = ruby_system)
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exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
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@ -84,6 +84,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
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cacheMemory = cache,
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send_evictions = (
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options.cpu_type == "detailed"),
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transitions_per_cycle = options.ports,
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ruby_system = ruby_system)
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cpu_seq = RubySequencer(version = i,
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@ -139,6 +140,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
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map_levels = \
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options.map_levels),
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memBuffer = mem_cntrl,
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transitions_per_cycle = options.ports,
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ruby_system = ruby_system)
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exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
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@ -156,6 +158,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
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dma_cntrl = DMA_Controller(version = i,
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cntrl_id = cntrl_count,
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dma_sequencer = dma_seq,
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transitions_per_cycle = options.ports,
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ruby_system = ruby_system)
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exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
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@ -94,6 +94,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
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l2_select_num_bits = l2_bits,
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send_evictions = (
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options.cpu_type == "detailed"),
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transitions_per_cycle = options.ports,
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ruby_system = ruby_system)
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cpu_seq = RubySequencer(version = i,
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@ -128,6 +129,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
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l2_cntrl = L2Cache_Controller(version = i,
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cntrl_id = cntrl_count,
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L2cache = l2_cache,
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transitions_per_cycle = options.ports,
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ruby_system = ruby_system)
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exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
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@ -166,6 +168,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
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size = dir_size,
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use_map = options.use_map),
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memBuffer = mem_cntrl,
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transitions_per_cycle = options.ports,
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ruby_system = ruby_system)
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exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
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@ -183,6 +186,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
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dma_cntrl = DMA_Controller(version = i,
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cntrl_id = cntrl_count,
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dma_sequencer = dma_seq,
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transitions_per_cycle = options.ports,
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ruby_system = ruby_system)
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exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
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@ -114,6 +114,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
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options.allow_atomic_migration,
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send_evictions = (
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options.cpu_type == "detailed"),
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transitions_per_cycle = options.ports,
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ruby_system = ruby_system)
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cpu_seq = RubySequencer(version = i,
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@ -149,6 +150,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
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cntrl_id = cntrl_count,
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L2cache = l2_cache,
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N_tokens = n_tokens,
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transitions_per_cycle = options.ports,
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ruby_system = ruby_system)
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exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
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@ -188,6 +190,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
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size = dir_size),
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memBuffer = mem_cntrl,
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l2_select_num_bits = l2_bits,
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transitions_per_cycle = options.ports,
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ruby_system = ruby_system)
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exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
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@ -205,6 +208,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
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dma_cntrl = DMA_Controller(version = i,
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cntrl_id = cntrl_count,
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dma_sequencer = dma_seq,
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transitions_per_cycle = options.ports,
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ruby_system = ruby_system)
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exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
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@ -107,6 +107,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
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options.allow_atomic_migration,
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send_evictions = (
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options.cpu_type == "detailed"),
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transitions_per_cycle = options.ports,
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ruby_system = ruby_system)
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cpu_seq = RubySequencer(version = i,
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@ -196,6 +197,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
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memBuffer = mem_cntrl,
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probe_filter_enabled = options.pf_on,
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full_bit_dir_enabled = options.dir_on,
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transitions_per_cycle = options.ports,
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ruby_system = ruby_system)
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if options.recycle_latency:
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@ -216,6 +218,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
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dma_cntrl = DMA_Controller(version = i,
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cntrl_id = cntrl_count,
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dma_sequencer = dma_seq,
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transitions_per_cycle = options.ports,
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ruby_system = ruby_system)
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exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
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@ -52,6 +52,11 @@ def define_options(parser):
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default='2GHz',
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help="Clock for blocks running at Ruby system's speed")
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# Options related to cache structure
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parser.add_option("--ports", action="store", type="int", default=4,
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help="used of transitions per cycle which is a proxy \
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for the number of ports.")
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# ruby network options
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parser.add_option("--topology", type="string", default="Crossbar",
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help="check src/mem/ruby/network/topologies for complete set")
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@ -64,6 +64,7 @@ options.l1d_assoc=2
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options.l1i_assoc=2
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options.l2_assoc=2
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options.l3_assoc=2
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options.ports=32
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#MAX CORES IS 8 with the fals sharing method
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nb_cores = 8
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@ -65,6 +65,7 @@ options.l1d_assoc=2
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options.l1i_assoc=2
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options.l2_assoc=2
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options.l3_assoc=2
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options.ports=32
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# Turn on flush check for the hammer protocol
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check_flush = False
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