Commit graph

350 commits

Author SHA1 Message Date
Gabe Black
2939a7089a byte_swap.hh was removed from arch/alpha/, and replaced by sim/byteswap.hh. The new file uses LittleEndianGuest and BigEndianGuest namespaces to allow selecting the appropriate functions.
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
    Added the endianness namespace. This may change.
cpu/exec_context.hh:
    Changed the include path for byteswap, and forced LittleEndianness for lack of a better solution.
cpu/o3/alpha_cpu.hh:
    Forced LittleEndianness, for lack of a better solution.
cpu/o3/alpha_cpu_impl.hh:
    Cleared away some commented out code.
cpu/o3/fetch_impl.hh:
    Changed the include patch for byteswap, and forced LittleEndianness for lack of a better solution.
cpu/simple/cpu.cc:
    Added an include for byteswap.hh, and fixed the SimpleCPU to LittleEndian. This cpu only does alpha, so that's fine.
dev/disk_image.cc:
    Changed the include path of byteswap.hh
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
    Added an include for byteswap.hh, and forced LittleEndianness for lack of a better solution.
sim/system.cc:
    Forced LittleEndianness for lack of a better solution.

--HG--
extra : convert_revision : b95d3e1265a825e04bd77622a3ac09fbac6bd206
2006-02-03 00:16:44 -05:00
Steve Reinhardt
03a2aca9a9 Changes for Process object initialization in merged-memory environment.
System object now exists for both fullsys and syscall emulation, as the
latter needs it so that Process objects can find the shared PhysicalMemory
for initialization.
Changes are incomplete: still need to fix up Process (& EioProcess) memory
initialization and syscall emulation code for new mem interface.

arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/alpha_tru64_process.hh:
cpu/base.cc:
cpu/base.hh:
    Take System argument in constructor.
cpu/exec_context.cc:
    Take System argument in constructor.
    Merge two constructors into a single one.
cpu/exec_context.hh:
    Take System argument in constructor.
    Merge two constructors into a single one.
    Replace dummy translation with lookup in Process object's page table.
python/m5/objects/Process.py:
    Add System parameter to Process object (& subobjects).
python/m5/objects/System.py:
    Segregate full-system only Process parameters (most of them!).
sim/process.cc:
    Take System argument in constructor.
    Move initialization to startup() callback to occur after system & cpus
    are initialized.
    Generate ProxyMemory object to pass to loader for transparent
    virtual page allocation.
sim/process.hh:
    Take System argument in constructor.
    Move initialization to startup() callback to occur after system & cpus
    are initialized.
sim/system.cc:
sim/system.hh:
    Enable System object for non-full-system too.
    Basically involved putting most of the existing code
    inside '#ifdef FULL_SYSTEM'.
    Key thing needed for syscall emulation at this point is
    the PhysicalMemory object (for Process initialization).

--HG--
extra : convert_revision : f0f34b47bd4f77b502191affd3d03b4d6d9bcdd8
2006-01-28 00:08:22 -05:00
Gabe Black
89596f0cfa Some stuff aparently didn't get committed which was from before the new repository was created.
SConscript:
    There is a new SConscript in the arch/alpha directory which has the alpha specific files. To add files for an arch, a similar file should be created.
arch/isa_parser.py:
    The isa parser now supports include directives. These are done with ##include
build/SConstruct:
    The target directory is passed on so that the architecture specific SConscript can have it. Also, sparc was added as a valid architecture type.
arch/alpha/SConscript:
    This SConscript adds the alpha specific source
arch/sparc/isa_desc/operands.h:
    This sets up the operand types that the sparc isa uses
arch/sparc/isa_traits.cc:
    Implementation of sparc specific things, like a register file with windows
build/build_options/default/SPARC_SE:
    The default options for a sparc syscall emulation build.

--HG--
extra : convert_revision : 1afedae61dc8cae0d59d3bf1d41420d929be2efd
2006-01-24 19:57:17 -05:00
Steve Reinhardt
0cdcb08d90 Change base/intmath.{cc,hh} to follow m5 style.
arch/alpha/alpha_tru64_process.cc:
base/intmath.hh:
base/statistics.cc:
base/str.cc:
cpu/o3/btb.cc:
sim/process.cc:
sim/syscall_emul.hh:
    Rename intmath.hh functions to follow m5 style
    (RoundUp -> roundUp, etc.).
base/intmath.cc:
    Rename intmath.hh functions to follow m5 style
    (RoundUp -> roundUp, etc.).
    Also reindent code in m5 style.

--HG--
extra : convert_revision : 57b853002bc3c9911e122599d9062b41a06d8e6a
2005-12-23 13:32:31 -05:00
Kevin Lim
6da93ea526 Apply patch for syscall emulation provided by Antti Miettinen (apm@brigitte.dna.fi). It provides support for more syscalls in syscall emulation mode.
arch/alpha/alpha_linux_process.cc:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Apply patch for syscall emulation provided by Antti Miettinen (apm@brigitte.dna.fi).

--HG--
extra : convert_revision : 37fbc78a927110b7798343afd2c5f37a269e42b4
2005-11-22 12:08:08 -05:00
Nathan Binkert
0dcb288365 Cleanup the StackTrace interfaces and profile interfaces so they
are more efficient and reduce the number of new/delete calls

arch/alpha/stacktrace.cc:
    - Change the StackTrace code so that the class can more easily be
    cleaned out and reused to avoid extra allocations.
    - Allow trace() to accept a static instruction pointer so it can
    determine if the instruction is worth tracing.  This is moved from
    the CPU.
    - provide constants for special meaning PCs (user, console, unknown),
    instead of magic numbers
    - switch to using kernelSymtab instead of allSymtab which will be
    going away
    - if the stack adjustment doesn't make any sense, exit and push
    unknown so we don't get into an infinite loop or record garbage.
    - check to see if we've made too many iterations through the stack
    and panic to avoid an infinite loop
arch/alpha/stacktrace.hh:
    - Change the StackTrace code so that the class can more easily be
    cleaned out and reused to avoid extra allocations.
    - Allow trace() to accept a static instruction pointer so it can
    determine if the instruction is worth tracing.  This is moved from
    the CPU.
    - provide constants for special meaning PCs (user, console, unknown),
    instead of magic numbers
cpu/base.cc:
    only clear the profile if we have one
    include profile.hh here since base.hh doesn't do it anymore
cpu/base.hh:
    no need to include cpu/profile.hh here
cpu/profile.cc:
    use ProfileNode pointers instead of objects in the ChildList
    Consume a vector of addresses since that's really all we
    care about.
cpu/profile.hh:
    Keep pointers to ProfileNodes to reduce the size of these structures
    keep a StackTrace around so that we may reuse it.
    provide consume functions that use the new StackTrace trace interface
    one consume function is inline and tries to fastpath the no trace
    condition, it calls the outlined consume function if a trace is generated.
cpu/simple/cpu.cc:
    include cpu/profile.hh here since base.hh no longer does
    use the new FunctionProfile::consume interface
    (which contains the tracing functions)

--HG--
extra : convert_revision : 5a1d9265289a75f67a497b322926be1f8c2d8eb3
2005-11-20 17:44:58 -05:00
Ali Saidi
ccae5838fd add symbol opcode
--HG--
extra : convert_revision : e050d2c4fec33c41ac21b6f17b3be329b9521429
2005-11-19 01:25:34 -05:00
Steve Reinhardt
e701cf48d9 A couple of FP-related fixes (prompted by Adam having trouble
running SPEC FP codes).

arch/alpha/isa_desc:
    Don't warn about non-standard trapping modes more than
    once per static instruction.  (Had the flag to suppress
    these but forgot to check it!)
build/SConstruct:
    Add USE_SSE2 option to enable compiling w/SSE2 (important
    for getting IEEE-compliant FP on x86).

--HG--
extra : convert_revision : eac69efb28cce7b48035480d8b7cb004782969f4
2005-11-09 09:52:07 -05:00
Nathan Binkert
e999645caf define a couple more abi regiesters
--HG--
extra : convert_revision : 2b909cc784d4fdd4833a70e86d13c207a7c1dd23
2005-10-18 20:02:23 -04:00
Nathan Binkert
a81c03737a Add new function profiling stuff, wrap the pc_sample stuff into it.
SConscript:
    Get rid of the pc_sample stuff and move to the new profiling stuff
base/traceflags.py:
    DPRINTF Stack stuff
cpu/base.cc:
cpu/base.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple/cpu.cc:
    Add profiling stuff
kern/kernel_stats.hh:
    Use a smart pointer
sim/system.cc:
sim/system.hh:
    Create a new symbol table that has all of the symbols for a
    particular system
util/stats/categories.py:
    change around the categories, add categories for function
    profiling stuff
util/stats/profile.py:
    No profile parsing and display code to deal with function
    profiling stuff, graph, dot, and text outputs.

--HG--
extra : convert_revision : b3de0cdc8bd468e42647966e2640ae009bda9eb8
2005-10-18 19:07:42 -04:00
Steve Reinhardt
310f608757 Clean up indentation in isa_desc.
arch/alpha/isa_desc:
    Little bit of re-ordering and indentation clean-up.

--HG--
extra : convert_revision : e538ff89d8b507c3e1aa68a032578fcaa645d7ee
2005-09-24 18:17:51 -04:00
Steve Reinhardt
11cb904ad7 Explicitly handle rounding on FP-to-integer conversions.
Seems to avoid the significant problems on platforms w/o fenv.h.

arch/alpha/isa_desc:
    Explicitly handle rounding on FP-to-integer conversions.
    Seems to avoid the significant problems on platforms w/o fenv.h.
    Get rid of FP "Fast" vs "General" distinction... more headache than
    it's worth.
arch/isa_parser.py:
    Fix bug with "%s" in C++ templates (must escape properly to
    pass through Python string interpolation).

--HG--
extra : convert_revision : de964d764e67e0934ac0ef535f53c974640731fb
2005-09-11 19:29:41 -04:00
Steve Reinhardt
39ce4fbaf9 Bug fix: can't increment an iterator after you erase
the thing it points to.  Somehow Linux doesn't care,
but Cygwin sure does.

--HG--
extra : convert_revision : 1209a75831f080f17a95433e546d7074f9f07332
2005-09-02 14:38:11 -04:00
Steve Reinhardt
c4793184bd Build options are set via a build_options file in the
build directory instead of being inferred from the name
of the build directory.
Options are passed to C++ via config/*.hh files instead of
via the command line.  Build option flags are now always
defined to 0 or 1, so checks must use '#if' rather than
'#ifdef'.

SConscript:
    MySQL detection moved to SConstruct.
    Add config/*.hh files (via ConfigFile builder).
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/isa_traits.hh:
base/fast_alloc.hh:
base/statistics.cc:
base/statistics.hh:
base/stats/events.cc:
base/stats/events.hh:
cpu/base.cc:
cpu/base.hh:
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/alpha_params.hh:
cpu/o3/commit_impl.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/fetch_impl.hh:
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
cpu/o3/regfile.hh:
cpu/o3/rename_impl.hh:
cpu/o3/rob_impl.hh:
cpu/ozone/cpu.hh:
cpu/pc_event.cc:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
sim/process.cc:
sim/process.hh:
    Convert compile flags from def/undef to 0/1.
    Set via #include config/*.hh instead of command line.
arch/alpha/isa_desc:
    Convert compile flags from def/undef to 0/1.
    Set via #include config/*.hh instead of command line.
    Revamp fenv.h support... most of the ugliness is hidden
    in base/fenv.hh now.
base/mysql.hh:
    Fix typo in #ifndef guard.
build/SConstruct:
    Build options are set via a build_options file in the
    build directory instead of being inferred from the name
    of the build directory.
    Options are passed to C++ via config/*.hh files instead of
    via the command line.
python/SConscript:
    Generate m5_build_env directly from scons options
    instead of indirectly via CPPDEFINES.
python/m5/convert.py:
    Allow '0' and '1' for booleans.
    Rewrite toBool to use dict.
base/fenv.hh:
    Revamp <fenv.h> support to make it a compile option
    (so we can test w/o it even if it's present) and to
    make isa_desc cleaner.

--HG--
extra : convert_revision : 8f97dc11185bef5e1865b3269c7341df8525c9ad
2005-08-30 13:18:54 -04:00
Benjamin Nash
bc76a807af Merge m5read@m5.eecs.umich.edu:/bk/m5
into zed.eecs.umich.edu:/z/benash/bk/m5

--HG--
extra : convert_revision : 453615c8194ae9ca96330b7493c6b19fc89c3a72
2005-06-28 14:03:04 -04:00
Nathan Binkert
036a8ceb8d Don't hard code the location of m5AlphaAccess. Instead, move the
code into a function that can be called by the AlphaConsole class.
AlphaConsole will pass in its address.

arch/alpha/ev5.hh:
    Move Phys2K0Seg to ev5.hh and fixup the TSUNAMI uncacheable
    bits so that they will be converted correctly.
dev/alpha_access.h:
    Do not hard code the location of the AlphaConsole
dev/alpha_console.cc:
    fixup #includes
    tell the system where the alpha console is
sim/system.hh:
    Provide a function that will tell the system where the AlphaAccess
    structure (device) lives

--HG--
extra : convert_revision : 92d70ca926151a32eebe9925de597459ac58013e
2005-06-28 12:42:15 -04:00
Benjamin Nash
f4e5776df4 I/O changes and SkipFuncEvents to increase FreeBSD compatibility.
SConscript:
    Added kern/freebsd/freebsd_events.cc.
arch/alpha/isa_traits.hh:
    Added Argument to support replacement of calibrate_clocks function in FreeBSD.
dev/ns_gige.hh:
    Fixed NIC model number typo.
dev/tsunami_io.cc:
    Added support for RTC writes and PIC 2 mask reads.  Made RTC static member.
dev/tsunami_io.hh:
    Made RTC static member.
kern/freebsd/freebsd_system.cc:
    Added events to skip functions in FreeBSD.
kern/freebsd/freebsd_system.hh:
    Added events to skip certain functions.

--HG--
extra : convert_revision : 8aaca51d3f9b1bb601722a5bae240aae77b445db
2005-06-17 18:08:05 -04:00
Steve Reinhardt
ad8b9636f8 Many files:
Update copyright dates and author list

SConscript:
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/alpha_tru64_process.hh:
arch/alpha/aout_machdep.h:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/faults.cc:
arch/alpha/faults.hh:
arch/alpha/isa_desc:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/osfpal.hh:
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
arch/alpha/vptr.hh:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/bitfield.hh:
base/callback.hh:
base/circlebuf.cc:
base/circlebuf.hh:
base/cprintf.cc:
base/cprintf.hh:
base/cprintf_formats.hh:
base/crc.hh:
base/date.cc:
base/dbl_list.hh:
base/endian.hh:
base/fast_alloc.cc:
base/fast_alloc.hh:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/hashmap.hh:
base/hostinfo.cc:
base/hostinfo.hh:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/inet.cc:
base/inet.hh:
base/inifile.cc:
base/inifile.hh:
base/intmath.cc:
base/intmath.hh:
base/match.cc:
base/match.hh:
base/misc.cc:
base/misc.hh:
base/mod_num.hh:
base/mysql.cc:
base/mysql.hh:
base/output.cc:
base/output.hh:
base/pollevent.cc:
base/pollevent.hh:
base/predictor.hh:
base/random.cc:
base/random.hh:
base/range.cc:
base/range.hh:
base/refcnt.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/res_list.hh:
base/sat_counter.cc:
base/sat_counter.hh:
base/sched_list.hh:
base/socket.cc:
base/socket.hh:
base/statistics.cc:
base/statistics.hh:
base/compression/lzss_compression.cc:
base/compression/lzss_compression.hh:
base/compression/null_compression.hh:
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.cc:
base/loader/object_file.hh:
base/loader/symtab.cc:
base/loader/symtab.hh:
base/stats/events.cc:
base/stats/events.hh:
base/stats/flags.hh:
base/stats/mysql.cc:
base/stats/mysql.hh:
base/stats/mysql_run.hh:
base/stats/output.hh:
base/stats/statdb.cc:
base/stats/statdb.hh:
base/stats/text.cc:
base/stats/text.hh:
base/stats/types.hh:
base/stats/visit.cc:
base/stats/visit.hh:
base/str.cc:
base/str.hh:
base/time.cc:
base/time.hh:
base/timebuf.hh:
base/trace.cc:
base/trace.hh:
base/userinfo.cc:
base/userinfo.hh:
build/SConstruct:
cpu/base.cc:
cpu/base.hh:
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/exetrace.cc:
cpu/exetrace.hh:
cpu/inst_seq.hh:
cpu/intr_control.cc:
cpu/intr_control.hh:
cpu/memtest/memtest.cc:
cpu/pc_event.cc:
cpu/pc_event.hh:
cpu/smt.hh:
cpu/static_inst.cc:
cpu/static_inst.hh:
cpu/memtest/memtest.hh:
cpu/o3/sat_counter.cc:
cpu/o3/sat_counter.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
cpu/trace/opt_cpu.cc:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/ibm_reader.cc:
cpu/trace/reader/ibm_reader.hh:
cpu/trace/reader/itx_reader.cc:
cpu/trace/reader/itx_reader.hh:
cpu/trace/reader/m5_reader.cc:
cpu/trace/reader/m5_reader.hh:
cpu/trace/reader/mem_trace_reader.cc:
cpu/trace/reader/mem_trace_reader.hh:
cpu/trace/trace_cpu.cc:
cpu/trace/trace_cpu.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/baddev.cc:
dev/baddev.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
dev/io_device.cc:
dev/io_device.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/pcireg.h:
dev/pktfifo.cc:
dev/pktfifo.hh:
dev/platform.cc:
dev/platform.hh:
dev/simconsole.cc:
dev/simconsole.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
dev/sinic.cc:
dev/sinic.hh:
dev/sinicreg.hh:
dev/tsunami.cc:
dev/tsunami.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunamireg.h:
dev/uart.cc:
dev/uart.hh:
dev/uart8250.cc:
dev/uart8250.hh:
docs/stl.hh:
encumbered/cpu/full/op_class.hh:
kern/kernel_stats.cc:
kern/kernel_stats.hh:
kern/linux/linux.hh:
kern/linux/linux_syscalls.cc:
kern/linux/linux_syscalls.hh:
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/linux/linux_threadinfo.hh:
kern/linux/printk.cc:
kern/linux/printk.hh:
kern/system_events.cc:
kern/system_events.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/dump_mbuf.hh:
kern/tru64/mbuf.hh:
kern/tru64/printf.cc:
kern/tru64/printf.hh:
kern/tru64/tru64.hh:
kern/tru64/tru64_events.cc:
kern/tru64/tru64_events.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
python/SConscript:
python/m5/__init__.py:
python/m5/config.py:
python/m5/convert.py:
python/m5/multidict.py:
python/m5/smartdict.py:
sim/async.hh:
sim/builder.cc:
sim/builder.hh:
sim/debug.cc:
sim/debug.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/host.hh:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/process.cc:
sim/process.hh:
sim/root.cc:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/startup.cc:
sim/startup.hh:
sim/stat_control.cc:
sim/stat_control.hh:
sim/stats.hh:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
sim/system.cc:
sim/system.hh:
test/bitvectest.cc:
test/circletest.cc:
test/cprintftest.cc:
test/genini.py:
test/initest.cc:
test/lru_test.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/sized_test.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
test/tracetest.cc:
util/ccdrv/devtime.c:
util/m5/m5.c:
util/oprofile-top.py:
util/rundiff:
util/m5/m5op.h:
util/m5/m5op.s:
util/stats/db.py:
util/stats/dbinit.py:
util/stats/display.py:
util/stats/info.py:
util/stats/print.py:
util/stats/stats.py:
util/tap/tap.cc:
    Update copyright dates and author list

--HG--
extra : convert_revision : 0faba08fc0fc0146f1efb7f61e4b043c020ff9e4
2005-06-05 05:16:00 -04:00
Steve Reinhardt
39d8c49479 Fix a few broken or inconsistently formatted copyrights
that the script doesn't deal with.
Don't bother with copyright notices in generated files.

LICENSE:
    Fix author list.
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
    Fix inconsistently formatted copyright.
arch/isa_parser.py:
base/traceflags.py:
    Fix copyright & author list.
    Don't bother with copyrights in generated files.
dev/rtcreg.h:
    Fix broken copyright.

--HG--
extra : convert_revision : d628e63c495960e2b129cef0aa8fddbdd4dabd45
2005-06-05 05:08:37 -04:00
Steve Reinhardt
18115a4d67 Many files:
Remove RCS Id string

arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/aout_machdep.h:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/ecoff_machdep.h:
arch/isa_parser.py:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/faults.cc:
arch/alpha/faults.hh:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/osfpal.hh:
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
arch/alpha/vptr.hh:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/bitfield.hh:
base/callback.hh:
base/circlebuf.cc:
base/circlebuf.hh:
base/cprintf.cc:
base/cprintf.hh:
base/cprintf_formats.hh:
base/crc.cc:
base/crc.hh:
base/date.cc:
base/dbl_list.hh:
base/endian.hh:
base/fast_alloc.cc:
base/fast_alloc.hh:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/hashmap.hh:
base/hostinfo.cc:
base/hostinfo.hh:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/inet.cc:
base/inet.hh:
base/inifile.cc:
base/inifile.hh:
base/intmath.cc:
base/intmath.hh:
base/kgdb.h:
base/match.cc:
base/match.hh:
base/misc.cc:
base/misc.hh:
base/mod_num.hh:
base/mysql.cc:
base/mysql.hh:
base/output.cc:
base/output.hh:
base/pollevent.cc:
base/pollevent.hh:
base/predictor.hh:
base/random.cc:
base/random.hh:
base/range.cc:
base/range.hh:
base/refcnt.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/res_list.hh:
base/sat_counter.cc:
base/sat_counter.hh:
base/sched_list.hh:
base/socket.cc:
base/socket.hh:
base/statistics.cc:
base/statistics.hh:
base/compression/lzss_compression.cc:
base/compression/lzss_compression.hh:
base/compression/null_compression.hh:
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/coff_sym.h:
base/loader/coff_symconst.h:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/exec_aout.h:
base/loader/exec_ecoff.h:
base/loader/symtab.cc:
base/loader/symtab.hh:
base/stats/events.cc:
base/stats/events.hh:
base/stats/flags.hh:
base/stats/mysql.cc:
base/stats/mysql.hh:
base/stats/mysql_run.hh:
base/stats/output.hh:
base/stats/statdb.cc:
base/stats/statdb.hh:
base/stats/text.cc:
base/stats/text.hh:
base/stats/types.hh:
base/stats/visit.cc:
base/stats/visit.hh:
base/str.cc:
base/str.hh:
base/time.cc:
base/time.hh:
base/timebuf.hh:
base/trace.cc:
base/trace.hh:
base/traceflags.py:
base/userinfo.cc:
base/userinfo.hh:
cpu/base.cc:
cpu/base.hh:
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/exetrace.cc:
cpu/exetrace.hh:
cpu/inst_seq.hh:
cpu/intr_control.cc:
cpu/intr_control.hh:
cpu/pc_event.cc:
cpu/pc_event.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
cpu/o3/2bit_local_pred.cc:
cpu/o3/2bit_local_pred.hh:
cpu/o3/alpha_cpu.cc:
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_dyn_inst.cc:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/alpha_impl.hh:
cpu/o3/alpha_params.hh:
cpu/o3/bpred_unit.cc:
cpu/o3/bpred_unit.hh:
cpu/o3/bpred_unit_impl.hh:
cpu/o3/btb.cc:
cpu/o3/btb.hh:
cpu/o3/comm.hh:
cpu/o3/commit.cc:
cpu/o3/commit.hh:
cpu/o3/commit_impl.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/cpu_policy.hh:
cpu/o3/decode.cc:
cpu/o3/decode.hh:
cpu/o3/decode_impl.hh:
cpu/o3/fetch.cc:
cpu/o3/fetch.hh:
cpu/o3/fetch_impl.hh:
cpu/o3/free_list.cc:
cpu/o3/free_list.hh:
cpu/o3/iew.cc:
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
cpu/o3/inst_queue.cc:
cpu/o3/inst_queue.hh:
cpu/o3/inst_queue_impl.hh:
cpu/o3/mem_dep_unit.cc:
cpu/o3/mem_dep_unit.hh:
cpu/o3/mem_dep_unit_impl.hh:
cpu/o3/ras.cc:
cpu/o3/ras.hh:
cpu/o3/regfile.hh:
cpu/o3/rename.cc:
cpu/o3/rename.hh:
cpu/o3/rename_impl.hh:
cpu/o3/rename_map.cc:
cpu/o3/rename_map.hh:
cpu/o3/rob.hh:
cpu/o3/rob_impl.hh:
cpu/o3/sat_counter.cc:
cpu/o3/sat_counter.hh:
cpu/o3/store_set.cc:
cpu/o3/store_set.hh:
cpu/o3/tournament_pred.cc:
cpu/o3/tournament_pred.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
cpu/smt.hh:
cpu/static_inst.cc:
cpu/static_inst.hh:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/ibm_reader.cc:
cpu/trace/reader/ibm_reader.hh:
cpu/trace/reader/itx_reader.cc:
cpu/trace/reader/itx_reader.hh:
cpu/trace/reader/m5_reader.cc:
cpu/trace/reader/m5_reader.hh:
cpu/trace/reader/mem_trace_reader.cc:
cpu/trace/reader/mem_trace_reader.hh:
cpu/trace/trace_cpu.cc:
cpu/trace/trace_cpu.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/baddev.cc:
dev/baddev.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
dev/io_device.cc:
dev/io_device.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/pcireg.h:
dev/pktfifo.cc:
dev/pktfifo.hh:
dev/platform.cc:
dev/platform.hh:
dev/simconsole.cc:
dev/simconsole.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
dev/sinic.cc:
dev/sinic.hh:
dev/sinicreg.hh:
dev/tsunami.cc:
dev/tsunami.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/uart.cc:
dev/uart.hh:
dev/uart8250.cc:
dev/uart8250.hh:
docs/stl.hh:
encumbered/cpu/full/op_class.hh:
kern/kernel_stats.cc:
kern/kernel_stats.hh:
kern/linux/linux.hh:
kern/system_events.cc:
kern/system_events.hh:
kern/linux/linux_syscalls.cc:
kern/linux/linux_syscalls.hh:
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/linux/printk.cc:
kern/linux/printk.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/dump_mbuf.hh:
kern/tru64/mbuf.hh:
kern/tru64/printf.cc:
kern/tru64/printf.hh:
kern/tru64/tru64.hh:
kern/tru64/tru64_events.cc:
kern/tru64/tru64_events.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/async.hh:
sim/builder.cc:
sim/builder.hh:
sim/debug.cc:
sim/debug.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/host.hh:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/root.cc:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/startup.cc:
sim/startup.hh:
sim/stat_control.cc:
sim/stat_control.hh:
sim/stats.hh:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
sim/system.cc:
sim/system.hh:
test/Makefile:
test/bitvectest.cc:
test/circletest.cc:
test/cprintftest.cc:
test/initest.cc:
test/lru_test.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/sized_test.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
test/tracetest.cc:
util/m5/m5.c:
util/m5/m5op.h:
util/m5/m5op.s:
util/tap/Makefile:
util/tap/tap.cc:
util/term/Makefile:
util/term/term.c:
    Remove RCS Id string

--HG--
extra : convert_revision : fc5b0a6ee2a213785bd58c51ce82eb2f769d6b88
2005-06-05 04:21:22 -04:00
Ali Saidi
5070f27c69 added copyright
kern/linux/sched.hh:
kern/linux/thread_info.hh:
    got rid of everything but exactly what we needed
util/categories.py:
    newest version from one of my repositories

--HG--
extra : convert_revision : c4328e5938d421d60493c0da07022bfa9e92c404
2005-06-05 04:08:05 -04:00
Steve Reinhardt
550003e1b7 Change SamplingCPU to Sampler.
--HG--
extra : convert_revision : ddba327a572804954adcebfff1182b97d474c020
2005-06-05 02:59:43 -04:00
Nathan Binkert
13c005a8af shuffle files around for new directory structure
--HG--
rename : cpu/base_cpu.cc => cpu/base.cc
rename : cpu/base_cpu.hh => cpu/base.hh
rename : cpu/beta_cpu/2bit_local_pred.cc => cpu/o3/2bit_local_pred.cc
rename : cpu/beta_cpu/2bit_local_pred.hh => cpu/o3/2bit_local_pred.hh
rename : cpu/beta_cpu/alpha_full_cpu.cc => cpu/o3/alpha_cpu.cc
rename : cpu/beta_cpu/alpha_full_cpu.hh => cpu/o3/alpha_cpu.hh
rename : cpu/beta_cpu/alpha_full_cpu_builder.cc => cpu/o3/alpha_cpu_builder.cc
rename : cpu/beta_cpu/alpha_full_cpu_impl.hh => cpu/o3/alpha_cpu_impl.hh
rename : cpu/beta_cpu/alpha_dyn_inst.cc => cpu/o3/alpha_dyn_inst.cc
rename : cpu/beta_cpu/alpha_dyn_inst.hh => cpu/o3/alpha_dyn_inst.hh
rename : cpu/beta_cpu/alpha_dyn_inst_impl.hh => cpu/o3/alpha_dyn_inst_impl.hh
rename : cpu/beta_cpu/alpha_impl.hh => cpu/o3/alpha_impl.hh
rename : cpu/beta_cpu/alpha_params.hh => cpu/o3/alpha_params.hh
rename : cpu/beta_cpu/bpred_unit.cc => cpu/o3/bpred_unit.cc
rename : cpu/beta_cpu/bpred_unit.hh => cpu/o3/bpred_unit.hh
rename : cpu/beta_cpu/bpred_unit_impl.hh => cpu/o3/bpred_unit_impl.hh
rename : cpu/beta_cpu/btb.cc => cpu/o3/btb.cc
rename : cpu/beta_cpu/btb.hh => cpu/o3/btb.hh
rename : cpu/beta_cpu/comm.hh => cpu/o3/comm.hh
rename : cpu/beta_cpu/commit.cc => cpu/o3/commit.cc
rename : cpu/beta_cpu/commit.hh => cpu/o3/commit.hh
rename : cpu/beta_cpu/commit_impl.hh => cpu/o3/commit_impl.hh
rename : cpu/beta_cpu/full_cpu.cc => cpu/o3/cpu.cc
rename : cpu/beta_cpu/full_cpu.hh => cpu/o3/cpu.hh
rename : cpu/beta_cpu/cpu_policy.hh => cpu/o3/cpu_policy.hh
rename : cpu/beta_cpu/decode.cc => cpu/o3/decode.cc
rename : cpu/beta_cpu/decode.hh => cpu/o3/decode.hh
rename : cpu/beta_cpu/decode_impl.hh => cpu/o3/decode_impl.hh
rename : cpu/beta_cpu/fetch.cc => cpu/o3/fetch.cc
rename : cpu/beta_cpu/fetch.hh => cpu/o3/fetch.hh
rename : cpu/beta_cpu/fetch_impl.hh => cpu/o3/fetch_impl.hh
rename : cpu/beta_cpu/free_list.cc => cpu/o3/free_list.cc
rename : cpu/beta_cpu/free_list.hh => cpu/o3/free_list.hh
rename : cpu/beta_cpu/iew.cc => cpu/o3/iew.cc
rename : cpu/beta_cpu/iew.hh => cpu/o3/iew.hh
rename : cpu/beta_cpu/iew_impl.hh => cpu/o3/iew_impl.hh
rename : cpu/beta_cpu/inst_queue.cc => cpu/o3/inst_queue.cc
rename : cpu/beta_cpu/inst_queue.hh => cpu/o3/inst_queue.hh
rename : cpu/beta_cpu/inst_queue_impl.hh => cpu/o3/inst_queue_impl.hh
rename : cpu/beta_cpu/mem_dep_unit.cc => cpu/o3/mem_dep_unit.cc
rename : cpu/beta_cpu/mem_dep_unit.hh => cpu/o3/mem_dep_unit.hh
rename : cpu/beta_cpu/mem_dep_unit_impl.hh => cpu/o3/mem_dep_unit_impl.hh
rename : cpu/beta_cpu/ras.cc => cpu/o3/ras.cc
rename : cpu/beta_cpu/ras.hh => cpu/o3/ras.hh
rename : cpu/beta_cpu/regfile.hh => cpu/o3/regfile.hh
rename : cpu/beta_cpu/rename.cc => cpu/o3/rename.cc
rename : cpu/beta_cpu/rename.hh => cpu/o3/rename.hh
rename : cpu/beta_cpu/rename_impl.hh => cpu/o3/rename_impl.hh
rename : cpu/beta_cpu/rename_map.cc => cpu/o3/rename_map.cc
rename : cpu/beta_cpu/rename_map.hh => cpu/o3/rename_map.hh
rename : cpu/beta_cpu/rob.cc => cpu/o3/rob.cc
rename : cpu/beta_cpu/rob.hh => cpu/o3/rob.hh
rename : cpu/beta_cpu/rob_impl.hh => cpu/o3/rob_impl.hh
rename : cpu/beta_cpu/sat_counter.cc => cpu/o3/sat_counter.cc
rename : cpu/beta_cpu/sat_counter.hh => cpu/o3/sat_counter.hh
rename : cpu/beta_cpu/store_set.cc => cpu/o3/store_set.cc
rename : cpu/beta_cpu/store_set.hh => cpu/o3/store_set.hh
rename : cpu/beta_cpu/tournament_pred.cc => cpu/o3/tournament_pred.cc
rename : cpu/beta_cpu/tournament_pred.hh => cpu/o3/tournament_pred.hh
rename : cpu/ooo_cpu/ooo_cpu.cc => cpu/ozone/cpu.cc
rename : cpu/ooo_cpu/ooo_cpu.hh => cpu/ozone/cpu.hh
rename : cpu/ooo_cpu/ooo_impl.hh => cpu/ozone/cpu_impl.hh
rename : cpu/ooo_cpu/ea_list.cc => cpu/ozone/ea_list.cc
rename : cpu/ooo_cpu/ea_list.hh => cpu/ozone/ea_list.hh
rename : cpu/simple_cpu/simple_cpu.cc => cpu/simple/cpu.cc
rename : cpu/simple_cpu/simple_cpu.hh => cpu/simple/cpu.hh
rename : cpu/full_cpu/smt.hh => cpu/smt.hh
rename : cpu/full_cpu/op_class.hh => encumbered/cpu/full/op_class.hh
extra : convert_revision : c4a891d8d6d3e0e9e5ea56be47d851da44d8c032
2005-06-04 20:50:10 -04:00
Nathan Binkert
6b6445eeb9 more portable
arch/alpha/alpha_tru64_process.cc:
    Sort #includes
    Make code more portable. g++ doesn't seem to always like
    struct ::stat (and others). So, we typedef stat outside of
    the namespace as something else and use the typedef
base/hostinfo.cc:
    use snprintf to quell warning
base/inifile.cc:
    use strncpy to quell warning
base/stats/events.cc:
    don't use strcpy
cpu/beta_cpu/btb.cc:
    use FloorLog2 instead of log2
cpu/beta_cpu/comm.hh:
cpu/beta_cpu/inst_queue.hh:
cpu/beta_cpu/sat_counter.hh:
    use sim/host.hh instead of stdint.h

--HG--
extra : convert_revision : 59bd9235dda74e72a8b6a70b3f3a981840384f3f
2005-06-04 14:16:04 -04:00
Steve Reinhardt
22eccce34b Additions/fixes for Tru64 syscall emulation.
We can now run the SimpleScalar wupwise binary
to completion on the test input.
Didn't have time to do more testing, but I fixed
a major problem w/getdirentries that should help
a lot more programs run.

arch/alpha/alpha_tru64_process.cc:
    Add truncate, ftruncate, statfs, and fstatfs.
    Add v4.x (pre-F64) stat, fstat, and lstat.
    Add setsysinfo (though all it does is provide more
    specific warning messages).
    Fix subtle but major bug in getdirentries.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Add truncate, ftruncate, statfs, and fstatfs.

--HG--
extra : convert_revision : 9037393d00dc49b0074a41603ea647587f5a9ec7
2005-06-03 16:19:34 -04:00
Steve Reinhardt
62fa781fee Rename sim/universe.{cc,hh} to root.{cc,hh} (since the
object defined there was renamed Root long ago).

SConscript:
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
base/misc.cc:
base/pollevent.cc:
base/pollevent.hh:
base/stats/events.cc:
base/trace.hh:
cpu/beta_cpu/fetch_impl.hh:
cpu/beta_cpu/full_cpu.cc:
cpu/beta_cpu/inst_queue_impl.hh:
cpu/pc_event.cc:
cpu/static_inst.cc:
dev/etherbus.cc:
dev/etherdump.cc:
dev/etherlink.cc:
dev/ide_disk.cc:
dev/pcidev.cc:
sim/builder.cc:
sim/eventq.cc:
sim/main.cc:
sim/root.cc:
sim/stat_control.cc:
    Rename sim/universe.{cc,hh} to root.{cc,hh}.

--HG--
rename : sim/universe.cc => sim/root.cc
extra : convert_revision : b8699e81e285253d66da75412e7bb2c251c0389a
2005-06-01 21:59:27 -04:00
Kevin Lim
61d95de4c8 Large update of several parts of my code. The most notable change is the inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version.
SConscript:
arch/isa_parser.py:
cpu/base_dyn_inst.cc:
    Remove OOO CPU stuff.
arch/alpha/faults.hh:
    Add fake memory fault.  This will be removed eventually.
arch/alpha/isa_desc:
    Change EA comp and Mem accessor to be const StaticInstPtrs.
cpu/base_dyn_inst.hh:
    Update read/write calls to use load queue and store queue indices.
cpu/beta_cpu/alpha_dyn_inst.hh:
    Change to const StaticInst in the register accessors.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
    Update syscall code with thread numbers.
cpu/beta_cpu/alpha_full_cpu.hh:
    Alter some of the full system code so it will compile without errors.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
    Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
    Update some of the full system code so it compiles.
cpu/beta_cpu/alpha_params.hh:
cpu/beta_cpu/fetch_impl.hh:
    Remove asid.
cpu/beta_cpu/comm.hh:
    Remove global history field.
cpu/beta_cpu/commit.hh:
    Comment out rename map.
cpu/beta_cpu/commit_impl.hh:
    Update some of the full system code so it compiles.  Also change it so that it handles memory instructions properly.
cpu/beta_cpu/cpu_policy.hh:
    Removed IQ from the IEW template parameter to make it more uniform.
cpu/beta_cpu/decode.hh:
    Add debug function.
cpu/beta_cpu/decode_impl.hh:
    Slight updates for decode in the case where it causes a squash.
cpu/beta_cpu/fetch.hh:
cpu/beta_cpu/rob.hh:
    Comment out unneccessary code.
cpu/beta_cpu/full_cpu.cc:
    Changed some of the full system code so it compiles.  Updated exec contexts and so forth to hopefully make multithreading easier.
cpu/beta_cpu/full_cpu.hh:
    Updated some of the full system code to make it compile.
cpu/beta_cpu/iew.cc:
    Removed IQ from template parameter to IEW.
cpu/beta_cpu/iew.hh:
    Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue.
cpu/beta_cpu/iew_impl.hh:
    New handling of memory instructions through the Load/Store queue.
cpu/beta_cpu/inst_queue.hh:
    Updated comment.
cpu/beta_cpu/inst_queue_impl.hh:
    Slightly different handling of memory instructions due to Load/Store queue.
cpu/beta_cpu/regfile.hh:
    Updated full system code so it compiles.
cpu/beta_cpu/rob_impl.hh:
    Moved some code around; no major functional changes.
cpu/ooo_cpu/ooo_cpu.hh:
    Slight updates to OOO CPU; still does not work.
cpu/static_inst.hh:
    Remove OOO CPU stuff.  Change ea comp and mem acc to return const StaticInst.
kern/kernel_stats.hh:
    Extra forward declares added due to compile error.

--HG--
extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
2005-05-03 10:56:47 -04:00
Kevin Lim
6191d3e444 Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : ac0788599c365b2d7fe0870f0fea4b62c3b3ef22
2005-05-02 14:16:33 -04:00
Nathan Binkert
5a7ee2b495 Make code more portable and port to cygwin
arch/alpha/alpha_tru64_process.cc:
    getdirent isn't implemented by cygwin.  panic if this function is
    executed.  (It shouldn't be too much to emulate it using opendir,
    readdir, etc.)
arch/alpha/pseudo_inst.cc:
    Use lseek once and read instead pread.
base/intmath.hh:
    we want int, long, and long long variations of FloorLog2 instead
    of int32_t, int64_t.  Otherwise, we leave one out.
base/socket.cc:
    Fix define that seems to be for apple
sim/serialize.cc:
    don't use the intXX_t stuff, instead, use the real types
    so we're sure that we cover all of them.

--HG--
extra : convert_revision : 9fccaff583100b06bbaafd95a162c4e19beed59e
2005-04-22 13:12:03 -04:00
Kevin Lim
26d6d97f5d Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : 0baadd8d68bfa6f8e96307eb2d4426b0d9e0b8b4
2005-04-14 16:06:34 -04:00
Nathan Binkert
5eab6c4b41 Make the notion of a global event tick independent of the actual
CPU cycle ticks.  This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency.  For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.

arch/alpha/ev5.cc:
    The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
    frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
    frequency isn't the cpu parameter anymore, cycleTime is.
    create several public functions for getting the cpu frequency
    and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
    Now that ticks aren't cpu cycles, fixup code to advance
    by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
    Provide a function to get the number of ticks for a given
    number of cycles.
dev/alpha_console.cc:
    Update for changes in the way that frequencies and latencies are
    accessed.  Move some stuff to init()
dev/alpha_console.hh:
    Need a pointer to the system and the cpu to get the frequency
    so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
    update for changes in the way bandwidths are passed from
    python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
    update for changes in the way bandwidths are passed from
    python to C++ to accomidate the new way that ticks works.
    Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
    outline the constructor and destructor
dev/platform.hh:
    outline the constructor and destructor.
    don't keep track of the interrupt frequency.  Only provide the
    accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
    outline the constructor and destructor
    Don't set the interrupt frequency here.  Get it from the actual device
    that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
    Make the interrupt interval a configuration parameter.  (And convert
    the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
    update for changes in the way bandwidths are passed from
    python to C++ to accomidate the new way that ticks works.
    For now, we must get the boot cpu's frequency as a parameter
    since allowing the system to have a pointer to the boot cpu would
    cause a cycle.
kern/tru64/tru64_system.cc:
    For now, we must get the boot cpu's frequency as a parameter
    since allowing the system to have a pointer to the boot cpu would
    cause a cycle.
python/m5/config.py:
    Fix support for cycle_time relative latencies and frequencies.
    Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
    All CPUs now have a cycle_time.  The default is the global frequency,
    but it is now possible to set the global frequency to some large value
    (like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
    Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
    We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
    Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
    this frequency isn't needed.  We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
    The clock generator should hold the frequency
sim/eventq.hh:
    Need to remove this assertion because the writeback event
    queue is different from the CPU's event queue which can cause
    this assertion to fail.
sim/process.cc:
    Fix comment.
sim/system.hh:
    Struct member to hold the boot CPU's frequency.
sim/universe.cc:
    remove unneeded variable.

--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 15:32:06 -04:00
Kevin Lim
dcedd7866e Hand merge
base/traceflags.py:
    Include new flags

--HG--
extra : convert_revision : 8017cbe256860dce8b1efc1b4e1e81e883895b90
2005-04-07 16:34:02 -04:00
Nathan Binkert
43a9caa221 expose variables for number of global events per simulated second,
millisecond, microsecond, etc. so that the user can explicitly
convert between system ticks and time and know what sorts of
expensive operations are being used for that conversion.

arch/alpha/alpha_tru64_process.cc:
arch/alpha/pseudo_inst.cc:
dev/etherdump.cc:
dev/etherlink.cc:
dev/ns_gige.cc:
dev/sinic.cc:
dev/tsunami_io.cc:
dev/uart.cc:
sim/stat_control.cc:
sim/syscall_emul.hh:
    Use the new variables for getting the event clock
dev/etherdump.hh:
    delete variables that are no longer needed.

--HG--
extra : convert_revision : d95fc7d44909443e1b7952a24ef822ef051c7cf2
2005-03-29 07:55:44 -05:00
Kevin Lim
cfa4221e19 Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : cbf8da2fe5c4155d9ed8318597d543ff105449d3
2005-03-18 15:32:53 -05:00
Ron Dreslinski
d97590e29d Merge zizzer:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1

--HG--
extra : convert_revision : 848757d0f18cfb33620cfa4b084a9b102b2744c0
2005-03-16 10:31:22 -05:00
Ron Dreslinski
df012f26fa Fix the bad addr check to check for allowable addresses in the nxm address space
arch/alpha/alpha_tru64_process.cc:
sim/process.cc:
sim/process.hh:
    Add an address range for the nxm
sim/syscall_emul.hh:
    Check to make sure that if we have an nxm config space that the mmap hasn't grown into it

--HG--
extra : convert_revision : e479e5240080ae488080d228bafea488835d6e77
2005-03-16 10:30:33 -05:00
Kevin Lim
efdab1748f Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : ba27a3ba99b567f5a8a41d9cd3a09d38c820ed89
2005-03-14 18:01:07 -05:00
Kevin Lim
2adf334642 g++ 3.4 fixes.
arch/alpha/alpha_tru64_process.cc:
    g++ 3.4 fixes.  Must cast to an int prior to returning value.

--HG--
extra : convert_revision : d8ccfd7aa7ca00d9bc2d76cff014b9f142d10640
2005-03-14 18:00:46 -05:00
Kevin Lim
c12a665c31 Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : a58535776cf5a3d17f8d9f65144cdf8db54289aa
2005-03-10 15:53:27 -05:00
Ali Saidi
ad9b28f98e Removed unecessary constructor call at each return.
arch/alpha/isa_traits.hh:
    updated copyright date

--HG--
extra : convert_revision : 30c5fc0eb94138ebd4ee047ebdbff5121f95e5f1
2005-03-10 14:20:12 -05:00
Ali Saidi
9797eedeea fix typo in SyscallReturn Object
--HG--
extra : convert_revision : 97d34a02a29a9ac3e2256d92194e3a46b9e8021e
2005-03-10 02:01:43 -05:00
Ali Saidi
232134a816 Changed all syscalls to use syscall return object.
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
cpu/exec_context.hh:
sim/process.hh:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Changed all syscalls to use syscall return object
arch/alpha/isa_traits.hh:
    Added syscall return object that packages return value and return
    status into an object.
sim/process.cc:
    renamed variable name to nm so base class function name() can be called

--HG--
extra : convert_revision : 6609c5ffecc9e3519d7a0cd160879fd21d54abfc
2005-03-09 15:52:10 -05:00
Kevin Lim
2162b433ad Hand-merge static_inst.hh. These execute functions are within an external file in the new CPU case.
cpu/static_inst.hh:
    Hand-merge.  These execute functions are within an external file in the new CPU case.

--HG--
extra : convert_revision : a34112f471fa31bdd5bb53552ddd704b9571c110
2005-03-08 21:03:20 -05:00
Steve Reinhardt
50a4ed87d0 Two fixes to try and get TLB miss cost more in line with real platform:
1) Add fault_handler_delay param to FullCPU to wait N cycles after
committing faulting instruction before fetching fault handler.
2) Make hw_rei a serializing instruction (flushes pipe, basically).

arch/alpha/isa_desc:
    Make hw_rei a serializing instruction (guarantees previous insts
    complete before hw_rei will issue).

--HG--
extra : convert_revision : 704cef65b3869be9eee724055cedb22114a78359
2005-03-01 22:32:14 -05:00
Steve Reinhardt
58c29640b7 Add a new operation class for IPR accesses, and have IPR-accessing
instructions use it (instead of IntALU, as before).  Default config
has a single non-pipelined 3-cycle unit.  A bit conservative for the
ev6 (some are 1, some are 3).

arch/alpha/isa_desc:
    Make hw_mfpr and hw_mtpr use IprAccessOp op class.
cpu/full_cpu/op_class.hh:
    Add IprAccess.

--HG--
extra : convert_revision : d4103da3343a586936839e29981fd15d6930d442
2005-03-01 00:39:57 -05:00
Steve Reinhardt
89dc94f3bc Make all StaticInst methods const. StaticInst objects represent a
particular binary machine instruction and should be immutable after
they are constructed.

cpu/simple_cpu/simple_cpu.hh:
    Make StaticInst parameters const.

--HG--
extra : convert_revision : e535fa10c842ce173336323f39d9108c1847f8ba
2005-02-25 21:44:33 -05:00
Kevin Lim
bb41c21d6a Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : ba556bbc93275fcd920a0529383fd480bb7218de
2005-02-25 18:01:19 -05:00
Kevin Lim
5c4714c1a9 Initial light-weight OoO CPU checkin, along with gcc-3.4 fixes.
SConscript:
    Include new files.
arch/alpha/isa_desc:
    Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them.
arch/alpha/isa_traits.hh:
    Add enum for total number of data registers.
arch/isa_parser.py:
base/traceflags.py:
    Include new light-weight OoO CPU model.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
    Changes to abstract more away from the base dyn inst class.
cpu/beta_cpu/2bit_local_pred.cc:
cpu/beta_cpu/2bit_local_pred.hh:
cpu/beta_cpu/tournament_pred.cc:
cpu/beta_cpu/tournament_pred.hh:
    Remove redundant SatCounter class.
cpu/beta_cpu/alpha_dyn_inst.cc:
cpu/beta_cpu/alpha_full_cpu.cc:
cpu/beta_cpu/alpha_full_cpu.hh:
cpu/beta_cpu/bpred_unit.cc:
cpu/beta_cpu/inst_queue.cc:
cpu/beta_cpu/mem_dep_unit.cc:
cpu/beta_cpu/ras.cc:
cpu/beta_cpu/rename_map.cc:
cpu/beta_cpu/rename_map.hh:
cpu/beta_cpu/rob.cc:
    Fix for gcc-3.4
cpu/beta_cpu/alpha_dyn_inst.hh:
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
    Fixes for gcc-3.4.
    Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
    Make params match the current params inherited from BaseCPU.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
    Fixes for gcc-3.4
cpu/beta_cpu/full_cpu.cc:
    Use new params pointer in BaseCPU.
    Fix for gcc-3.4.
cpu/beta_cpu/full_cpu.hh:
    Use new params class from BaseCPU.
cpu/beta_cpu/iew_impl.hh:
    Remove unused function.
cpu/simple_cpu/simple_cpu.cc:
    Remove unused global variable.
cpu/static_inst.hh:
    Include OoODynInst for new lightweight OoO CPU

--HG--
extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa
2005-02-25 18:00:49 -05:00
Steve Reinhardt
368882a847 Fix timing modeling of faults: functionally the very next instruction after
a faulting instruction is the fault handler, which appears as an independent
instruction to the timing model.  New code will stall fetch and not fetch the
fault handler as long as there's a faulting instruction in the pipeline (i.e.,
the faulting inst has to commit first).

Also fix Ali's bad-address assertion that doesn't apply to full system.

Added some more debugging support in the process.  Hopefully we'll move to the new
cpu model soon and we won't need it anymore.

arch/alpha/alpha_memory.cc:
    Reorganize lookup() so we can trace the result of the lookup as well.
arch/alpha/isa_traits.hh:
    Add NoopMachInst (so we can insert them in the pipeline on ifetch faults).
base/traceflags.py:
    Replace "Dispatch" flag with "Pipeline" (since I added similar
    DPRINTFs in other pipe stages).
cpu/exetrace.cc:
    Change default for printing mis-speculated instructions to true (since
    that's often what we want, and right now you can't change it from the
    command line...).

--HG--
extra : convert_revision : a29a98a373076d62bbbb1d6f40ba51ecae436dbc
2005-02-25 12:41:08 -05:00
Kevin Lim
e8a564b0fd Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : 8a558785c64b7c33e64523d3d887ea6e760c3d2b
2005-02-22 16:03:30 -05:00
Ali Saidi
57482491c5 build mysql version if libraries exist
add dprintf on alignment faults
fix RR benchmark rcS script name
Add Dual test without rcS script
Update Monet to be closer to the real thing
Fix p4/monet configs
Add a way to read the DRIR register with at 32bit access for validation

SConscript:
build/SConstruct:
    always use mysql if the libraries are installed
arch/alpha/alpha_memory.cc:
    Add a DPRINTF to print alignment faults when they happen
dev/tsunami_cchip.cc:
    Add a way to read the DRIR for validation.

--HG--
extra : convert_revision : 8c112c958f36b785390c46e70a889a79c6bea015
2005-02-13 23:03:04 -05:00
Kevin Lim
1e7a744c09 Hand merge
--HG--
extra : convert_revision : 86c7399b79c17558041a73056745227f70fe8b3b
2005-02-04 18:25:49 -05:00
Steve Reinhardt
0aaf8ec6b8 Add support for CPU models to execute the effective
address calculation and memory access portions separately.
Not currently used by any CPU models, but Kevin says he needs this.

Also clean up handling of execution tracing for memory accesses
(move it all into isa_desc and out of CPU models).

Got rid of some ancient unused code too.

arch/alpha/isa_desc:
    Add execute() methods to EAComp and MemAcc portions of memory
    access instructions, to allow CPU models to execute the effective
    address calculation and memory access portions separately.

    Requires the execution context to remember the effective address
    across the two invocations.  Added setEA() and getEA() methods to
    execution context to support this.  A model that does not use the
    split execution model can panic if these methods are called.

    Also added hook to call traceData->setAddr() after EA computation
    on any load or store operation.
arch/isa_parser.py:
    Call traceData->setData() on memory writes (stores).
cpu/simple_cpu/simple_cpu.cc:
    Get rid of unused code.
cpu/simple_cpu/simple_cpu.hh:
    Add (non-functional) setEA() and getEA() methods for new
    split memory access execution support.

--HG--
extra : convert_revision : bc2d2c758c4ca753812b9fa81f21038e55929ff0
2005-02-03 20:47:11 -05:00
Kevin Lim
e6b99b0768 Merge zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5-patched/m5-new

--HG--
extra : convert_revision : e802c800a478c297d3aa780a9ea3c6701453d91d
2005-01-21 18:31:30 -05:00
Nathan Binkert
6cbce7631a Add a couple statistics contexts.
arch/alpha/pseudo_inst.cc:
    rename the context for consistency.
sim/pyconfig/m5config.py:
    Add a ParamContext class so that param contexts work with
    the new config stuff.

--HG--
extra : convert_revision : 3a6b583a25c86237baca7a2b4eccc9d12f86a384
2005-01-21 04:34:01 -05:00
Kevin Lim
f58d85128d Fixes so m5 compiles on gcc 3.4, which has much stricter syntax. Most changes come from templated code,
which is evaluated slightly differently than in previous versions of gcc.

arch/alpha/alpha_linux_process.cc:
    Alphabetize includes.
arch/alpha/vptr.hh:
    Change the constants that are being used for alpha pagebytes to come from the ISA.
base/random.hh:
cpu/static_inst.cc:
sim/param.cc:
    Fix up template syntax.
base/range.hh:
    Include iostream for << operator.
base/res_list.hh:
base/statistics.hh:
cpu/simple_cpu/simple_cpu.hh:
cpu/static_inst.hh:
sim/eventq.hh:
sim/param.hh:
    Fixup for templated code to resolve different scope lookup in gcc 3.4.  This defers the lookup of the
    function/variable until actual instantiation time by making it dependent on the templated class/function.
base/trace.cc:
    Fix call to new.
base/trace.hh:
    Fix up #define to have full path.
cpu/base_cpu.cc:
    Fix up call to new.
dev/etherlink.hh:
dev/ns_gige.hh:
dev/sinic.hh:
    Fixup for friend class/function declaration.  g++ 3.4 no longer allows typedefs to be declared as
    a friend class.
dev/pcidev.hh:
    Fix up re-definition of access level to params.
kern/linux/linux_syscalls.hh:
kern/tru64/tru64_syscalls.hh:
    Fix up header.  Fix up template syntax.
sim/serialize.cc:
    Include errno.h.
sim/startup.cc:
    Change startupq.  queue was getting destructed before all things had called ~StartupCallback(), which lead
    to a segfault.  This puts startupq in global space, and we allocate it ourselves.  Other code may be similar
    to this and may need changing in the future.
sim/syscall_emul.hh:
    Include cpu/exec_context.hh and sim/process.hh, as forward declarations are no longer sufficient.
sim/universe.cc:
    Include errno.h

--HG--
extra : convert_revision : e49d08ee89eb06a28351f02bafc028ca6652d5af
2005-01-14 18:34:56 -05:00
Kevin Lim
42f3b4ffb3 Merge changes.
base/traceflags.py:
    Merge extra new CPU flags
cpu/static_inst.hh:
    Include all the execute functions in static_inst_impl.hh

--HG--
extra : convert_revision : 78eb753bf709d37400e7c2418bb35d842d7c3f63
2005-01-11 19:00:16 -05:00
Nathan Binkert
425dda00df Macros are nasty, so let's get rid of them. Convert all
all macros in ev5.hh to inline functions or constant typed
variables and make them follow our style while we're at it.

All of the stuff in this file actually belongs in the ISA
traits code, but this is a first step at getting things done
in the right manner.

arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/ev5.cc:
arch/alpha/isa_desc:
dev/ns_gige.cc:
kern/tru64/tru64_events.cc:
    deal with changes in ev5.hh
arch/alpha/ev5.hh:
    Macros are nasty, so let's get rid of them.  Convert all
    all macros to inline functions or constant typed variables.
    Make them follow our style while we're at it.

    All of the stuff in this file actually belongs in the ISA
    traits code, but this is a first step at getting things done
    in the right manner.
arch/alpha/isa_traits.hh:
    move some of the ev5 specific code into the isa
arch/alpha/vtophys.cc:
base/remote_gdb.cc:
    deal with isa addition
cpu/exec_context.hh:
    be less isa specific and use the isa traits to figure out
    what we can.
dev/alpha_console.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
    deal with changes in ev5.hh
    I don't believe this masking is actually necessary.  We should
    look at removing it later.
dev/ide_ctrl.cc:
    sort #includes
    deal with changes in ev5.hh

--HG--
extra : convert_revision : c8a3adf0a4b1d198aefe38fc38b295abf289b08a
2004-11-13 14:01:38 -05:00
Nathan Binkert
bde7f4d121 defining SYSTEM_EV5 isn't all that necessary
--HG--
extra : convert_revision : 2ed4866db9483820d550bad00fdbc8dd027f95ba
2004-11-13 11:33:43 -05:00
Nathan Binkert
c4e5ef64b3 defining SYSTEM_EV5 isn't all that necessary
--HG--
extra : convert_revision : 7d39dd9f814434cb95ec769204d7f2426b0290fd
2004-11-13 11:32:17 -05:00
Nathan Binkert
338513c681 Use the inPalMode function instead of the PC_PAL macro
--HG--
extra : convert_revision : 58e0a19ba98777e5d2e2572ed02dee1914378ff7
2004-11-10 18:44:37 -05:00
Nathan Binkert
4328480b56 Don't use the global check_interrupts variable. Add a per-cpu
checkInterrupts variable and use that to determine whether an interrupt
can occur on a given cycle.

arch/alpha/ev5.cc:
    XC -> CPU (and xc -> CPU) since we're really talking about a CPU here
    Don't use the global check_interrupts variable.  Add a per-cpu
    checkInterrupts variable and use that to determine whether an interrupt
    can occur on a given cycle.

--HG--
extra : convert_revision : be4c0247e5834005c60a45796a222cffd327b64e
2004-11-10 18:37:19 -05:00
Nathan Binkert
d55eb90fc7 Don't use magic numbers.
arch/alpha/isa_traits.hh:
    Move defines to non full system code section so they can
    be used elsewhere
cpu/simple_cpu/simple_cpu.cc:
    Don't use magic numbers
cpu/simple_cpu/simple_cpu.hh:
    simple format nit

--HG--
extra : convert_revision : b8d492218340d41ab9420c6ad1e81a197db1c132
2004-10-25 16:23:22 -04:00
Nathan Binkert
224acc2abc get rid of pmap.h and make things variables and inline
functions instead of preprocessor macros.

arch/alpha/vtophys.cc:
    use new constants, functions and structs to clean up the
    vtophys code.
arch/alpha/vtophys.hh:
    Clean up a little bit and make the protypes match new changes.
base/remote_gdb.cc:
dev/ide_disk.cc:
kern/tru64/tru64_events.cc:
    use new constants from isa_traits.hh instead of ones from
    old pmap.h

--HG--
extra : convert_revision : 5dce34e3b0c84ba72cefca34e5999b99898edcef
2004-10-23 10:41:35 -04:00
Nathan Binkert
3ab83348d2 in the arch/alpha directory we should use arch/alpha, not
targetarch.

arch/alpha/alpha_memory.cc:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/faults.cc:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
    in the arch/alpha directory we should use arch/alpha, not
    targetarch.  sort includes while we're here.

--HG--
extra : convert_revision : 99a71540e2997173db5c1072cef910a26acc75b2
2004-10-23 00:39:15 -04:00
Steve Reinhardt
0da150b294 Make targetarch directory in build tree and copy arch/alpha files to it
instead of using symlink.  The symlink broke scons's built-in include
dependency tacking.

Interestingly once it was fixed scons discovered two circular dependency
problems which are also fixed now.

SConscript:
    Make targetarch directory in build tree and copy arch/alpha files to it
    instead of using symlink.  The symlink broke scons's built-in include
    dependency tacking.
arch/alpha/ev5.hh:
    Get rid of circular #include dependence.
kern/kernel_stats.cc:
    Add needed header file.
kern/linux/linux_syscalls.hh:
kern/tru64/tru64_syscalls.hh:
    Replace targetarch/syscalls.hh with single template class declaration.

--HG--
extra : convert_revision : b8551623c1d441c6eb8d0651387e97e373128814
2004-10-22 22:49:12 -04:00
Ali Saidi
3ef950abba Fixes for bigendian platforms
arch/alpha/vtophys.cc:
    PGOFSET -> ALPHA_PGOFSET to avoid include file problems
base/callback.hh:
    Added  a class to create a callback from a function
base/intmath.hh:
    make FloorLog2 inlined
dev/pcidev.cc:
    more work in getting pciconfig space happy with different endiannesses
dev/uart.cc:
    used an incorrect size for write uint64_t instead of uint8_t
sim/system.cc:
    when writing things into system data structures we need to pay
    attention to endianness

--HG--
extra : convert_revision : 52f441b5789c45db30ef2f6fd4975cbc7323a381
2004-10-16 19:10:51 -05:00
Ali Saidi
ac422ac949 Merge zizzer:/bk/m5 into zeep.eecs.umich.edu:/z/saidi/work/m5-smp
--HG--
extra : convert_revision : 19dc01e1c0d2c0ba6b4d804b902429fb0a6a5552
2004-09-22 18:39:37 -04:00
Ali Saidi
eb7d329076 fix unaligned memory offset and some small fixes to interrupt binning
code

arch/alpha/alpha_memory.cc:
    Fixed unaligned trap faults
arch/alpha/ev5.cc:
    little more verbose faulting information
kern/linux/linux_system.cc:
    more descriptive errors, and the correct offsets from symbols
sim/system.cc:
    load local pal symbols

--HG--
extra : convert_revision : 0c81badf77321d5e1a060dcae2d42204e5a1fc84
2004-09-22 18:25:06 -04:00
Erik Hallnor
15d08a3422 Update copies to work around alignment faults.
arch/alpha/isa_desc:
    whitespace fix.
cpu/simple_cpu/simple_cpu.cc:
    Add support to make sure we don't get alignment faults in copies. Warn if we go over an 8k page boundary.

--HG--
extra : convert_revision : 98b38da86a66215d80ea9eb6e6f1f68ee573cb57
2004-09-20 22:00:35 -04:00
Ali Saidi
af620e1187 added system option to bin interrupt code seperately.
arch/alpha/ev5.cc:
    set the mode explictly rather than having a bool user/notuser
cpu/simple_cpu/simple_cpu.hh:
    there is no class Kernel
kern/kernel_stats.cc:
    use cpu_mode_num
kern/kernel_stats.hh:
    add interrupt mode and use cpu_mode_num rather than constant
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/system_events.cc:
kern/system_events.hh:
    add events to change the mode to/from interrupt
sim/system.cc:
sim/system.hh:
    add a pal symbol table

--HG--
extra : convert_revision : 9d30e826b72122062a5ea12d094f94760e75c66a
2004-09-03 14:12:59 -04:00
Kevin Lim
04745696b6 Check in of new CPU. This checkin works under non-Fullsystem mode, with no caches.
SConscript:
    Added new CPU files to build.
arch/alpha/isa_desc:
    Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed.
arch/isa_parser.py:
    Added new CPU exec method.
base/statistics.hh:
    Minor change for namespace conflict.  Probably can change back one the new CPU files are cleaned up.
base/traceflags.py:
    Added new CPU trace flags.
cpu/static_inst.hh:
    Changed static inst to use a file that defines the execute functions.

--HG--
extra : convert_revision : bd4ce34361308280168324817fc1258dd253e519
2004-08-20 14:54:07 -04:00
Nathan Binkert
9023f5c96d - Clean up and factor out all of the binning code into a
single place so it's easier to work with.
-  Add support for binning kernel/user/idle time separately from
lisa's binning stuff, but make the two compatible.
-  KernelStats used to directly implement the pImpl idiom, but
it makes more sense to just remove the level of indirection and
make the exec context have a pointer to the stats.
-  Factor common code out of LinuxSystem and Tru64System and put
it into the System base class.  While doing that, make all
constructors take a pointer to a parameter struct instead of
naming the parameters individually to make it much easier to add
parameters to these classes.

SConscript:
    Move the function tracking and binning stuff around.
arch/alpha/ev5.cc:
    kernelStats is now a pointer
arch/alpha/pseudo_inst.cc:
    kernelStats is now a pointer
    the parameters to the system have been moved into their own
    struct
base/trace.hh:
    provide a little functor class for wrapping a string that
    can allow you to define name() in any scope very simply
    for use with DPRINTF
cpu/base_cpu.cc:
    New order of arguments for consistency.
cpu/exec_context.cc:
    kernelStats no longer has the level of indirection in it,
    execContext has the indirection now.  so, kernelStats is a pointer.
    We also need a pointer to the kernelBinning stuff from the system
    and we need to figure out if we want to do binning or not.
    Move a whole bunch of code into kern_binning.cc so it's all
    in the same place.
cpu/exec_context.hh:
    We want pointers to the kernel binning/stats stuff and we'll
    have the exec_context and system have the level of indirection
    instead of having the extra layer in the kernel stats class.
cpu/simple_cpu/simple_cpu.cc:
    call through the exec context to do the special binning
    stuff.
kern/kernel_stats.cc:
kern/kernel_stats.hh:
    Re-organize the stats stuff and remove the level of indirection
    (that was there to simplify building) and move the binning stuff
    into its own class/file.
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/system.cc:
sim/system.hh:
    move lots of common system code into the base system class so
    that it can be shared between linux, tru64, and whatever else
    we decide to support in the future.

    Make the constructor take a pointer to a parameter struct so that
    it is easier to pass parameters to the parent.
kern/system_events.cc:
    move the majority of the binning code into the Kernel::Binning class
    in the kern_binning file
kern/system_events.hh:
    FnEvents only need to know the bin
    create the Idle start event to find the PCBB of the idle
    process when it starts.
kern/tru64/tru64_events.cc:
    memCtrl -> memctrl
sim/process.cc:
sim/process.hh:
    re-order args for consistency

--HG--
extra : convert_revision : 86cb39738c41fcd680f2aad125c9dde000227b2b
2004-08-20 11:35:31 -04:00
Ali Saidi
8f19fd2cbe merged full_cpu.ini, system.ini and devtime.c
util/ccdrv/devtime.c:
    coding style

--HG--
extra : convert_revision : 972941e100ba13a2ece0986454c4a3485841d9cb
2004-08-02 17:16:54 -04:00
Ali Saidi
6c954de33e added m5 debug and m5 switch cpu instruction (doesn't work yet) and
a p4 memory/cpu config

arch/alpha/alpha_memory.cc:
    Added code to fault on an unaligned access
arch/alpha/isa_desc:
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
    Added m5debug break and m5switchcpu (the latter doesn't work)

--HG--
extra : convert_revision : 409e73adb151600a4fea49f35bf6f503f66fa916
2004-08-02 17:10:02 -04:00
Ali Saidi
b376c6f420 Added debug printk support
arch/alpha/ev5.hh:
    Added max address PAL code can be at
arch/alpha/vtophys.cc:
    Check max address pal can be at so we don't do the wrong conversion
    if gdb asks for an unaligned access.

--HG--
extra : convert_revision : b44f6a8fcd8582337a7d4033f28137c7e718a6a8
2004-07-30 17:13:24 -04:00
Ali Saidi
02dfbe92fc fixed a bad merge from linux<->tru64
--HG--
extra : convert_revision : d7a5acd89a2bdc013c8a2bd022cc7048a3920f01
2004-07-08 00:28:02 -04:00
Nathan Binkert
0e575e9f26 Need to #include <unistd.h> to build with pread
--HG--
extra : convert_revision : 1e5b3e5f1eaba3853d7d3da5546387c16932ab6a
2004-07-02 12:30:06 -04:00
Nathan Binkert
6083c8280b implement the readfile pseudo instruction that will read
a realworld file.

arch/alpha/isa_desc:
arch/alpha/pseudo_inst.hh:
    implement the readfile pseudo instruction that will read a
    chunk of a realworld file.
arch/alpha/pseudo_inst.cc:
    implement the readfile pseudo instruction that will read a
    chunk of a realworld file.  The filename is a per system
    parameter and comes from the system itself.
kern/linux/linux_system.cc:
sim/system.hh:
    Create a per-system readfile parameter for use by the readfile
    pseudo instruction.  That way each system can get its own file.

--HG--
extra : convert_revision : 941b3a3e20702a6252b219ca66a6d90da2944c50
2004-07-01 18:03:05 -04:00
Nathan Binkert
671cff5937 rename CopyData to CopyOut and implement CopyIn to copy data
from the simulator into the simulatee

kern/tru64/dump_mbuf.cc:
    rename CopyData -> CopyOut

--HG--
extra : convert_revision : e3ef27a5762dfc495dcb84a372470464c27557d2
2004-07-01 18:00:18 -04:00
Nathan Binkert
ee765958b4 add asn when tracing tlb stuff
--HG--
extra : convert_revision : abc774179b3d4c979efd98e32d1d071b142e7b48
2004-06-30 14:51:40 -04:00
Nathan Binkert
838273a196 fix up the recordEvent stuff to support ignoring events
arch/alpha/ev5.cc:
cpu/simple_cpu/simple_cpu.cc:
    update for new event interface
base/stats/events.cc:
    implement the ignore event function which matches sim objects from which
    to ignore events.

    Make insert event like insert data and make it able to insert many
    events in a single transaction with the database.
base/stats/events.hh:
    Make it possible to ignore events
sim/sim_object.cc:
    make recordEvent a member function of SimObject to implement
    the ignore function easily
sim/sim_object.hh:
    implement the ignore event stuff in the sim object.  This is a
    bit of a hack, but an easy place to put it.

--HG--
extra : convert_revision : ba3f25a14ad03662c53fb35514860d69be8cd4f0
2004-06-28 16:49:35 -04:00
Ali Saidi
f37eb6f5c7 ifdefed ev5 vs. ev6 differences so Tlaser can work in the linux tree
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.hh:
    Ifdefed TLASER code
arch/alpha/vtophys.cc:
    added back some code andrew removed and couldn't remember why.

--HG--
extra : convert_revision : f00d255f7a8a7bdb6e74f061dd014188e3b39e73
2004-06-22 17:20:19 -04:00
Ali Saidi
4deb819894 pull from head before pushing linux tree
--HG--
extra : convert_revision : 345f91c5c16c69db22035dc716e82fd77041380f
2004-06-22 13:48:49 -04:00
Steve Reinhardt
d53c6c168a Get software prefetching to work in full-system mode.
Mostly a matter of keeping prefetches to invalid addrs
from messing up VM IPRs.  Also discovered that wh64s were
not being treated as prefetches, when they really should be
(for the most part, anyway).

arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
    - Get rid of intrlock flag for locking VM fault regs (a la EV5);
    instead, just don't update regs on VPTE loads (a la EV6).
    - Add NO_FAULT MemReq flag to indicate references that should not
    cause page faults (i.e., prefetches).
arch/alpha/ev5.cc:
    - Get rid of intrlock flag for locking VM fault regs (a la EV5);
    instead, just don't update regs on VPTE loads (a la EV6).
    - Add Fault trace flag.
arch/alpha/isa_desc:
    - Add NO_FAULT MemReq flag to indicate references that should not
    cause page faults (i.e., prefetches).
    - Mark wh64 as a "data prefetch" instruction so it gets controlled
    properly by the FullCPU data prefetch control switch.
    - Align wh64 EA in decoder so issue stage doesn't need to worry about it.
arch/alpha/isa_traits.hh:
    - Get rid of intrlock flag for locking VM fault regs (a la EV5);
    instead, just don't update regs on VPTE loads (a la EV6).
base/traceflags.py:
    - Add Fault trace flag.
cpu/simple_cpu/simple_cpu.hh:
    - Pass MemReq flags to writeHint() operation.
cpu/static_inst.hh:
    Update comment re: prefetches.

--HG--
extra : convert_revision : 62e466b0f4c0ff9961796270fa2e371ec24bcbb6
2004-06-15 10:48:08 -07:00
Ali Saidi
02f69b94c5 Fixes for detailed boot, made cttz and ctlz instructions more compact,
and started cleaning up config files.

arch/alpha/isa_desc:
    Made implementation of cttz and ctlz more compact
base/remote_gdb.cc:
    Added comment about PALcode debugger accesses
dev/baddev.cc:
dev/baddev.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunami_uart.cc:
dev/tsunami_uart.hh:
    Cleaned up includes and changed device from FunctionalMemory to
    PioDevice for detailed boot
dev/ns_gige.cc:
    The ethernet dev uses two BARs, and the first bars size was being set
    incorrectly.
dev/tsunamireg.h:
    I don't know why we were using the superpage as the PCI memory addr.
    Changed and works correctly with detailed boot.

--HG--
extra : convert_revision : b535e76612cb90b544305dc1aa8c5e0e774564bd
2004-06-10 13:30:58 -04:00
Ali Saidi
2f316082e4 Updated Copyright with information in bitkeeper changelogs
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/alpha_tru64_process.hh:
arch/alpha/aout_machdep.h:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/faults.cc:
arch/alpha/faults.hh:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/osfpal.hh:
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
arch/alpha/vptr.hh:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/bitfield.hh:
base/callback.hh:
base/circlebuf.cc:
base/circlebuf.hh:
base/compression/lzss_compression.cc:
base/compression/lzss_compression.hh:
base/compression/null_compression.hh:
base/cprintf.cc:
base/cprintf.hh:
base/cprintf_formats.hh:
base/date.cc:
base/dbl_list.hh:
base/endian.hh:
base/fast_alloc.cc:
base/fast_alloc.hh:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/hashmap.hh:
base/hostinfo.cc:
base/hostinfo.hh:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/inet.cc:
base/inet.hh:
base/inifile.cc:
base/inifile.hh:
base/intmath.cc:
base/intmath.hh:
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.cc:
base/loader/object_file.hh:
base/loader/symtab.cc:
base/loader/symtab.hh:
base/misc.cc:
base/misc.hh:
base/mod_num.hh:
base/mysql.cc:
base/mysql.hh:
base/pollevent.cc:
base/pollevent.hh:
base/predictor.hh:
base/random.cc:
base/random.hh:
base/range.cc:
base/range.hh:
base/refcnt.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/res_list.hh:
base/sat_counter.cc:
base/sat_counter.hh:
base/sched_list.hh:
base/socket.cc:
base/socket.hh:
base/statistics.cc:
base/statistics.hh:
base/stats/events.cc:
base/stats/events.hh:
base/stats/flags.hh:
base/stats/mysql.cc:
base/stats/mysql.hh:
base/stats/mysql_run.hh:
base/stats/output.hh:
base/stats/statdb.cc:
base/stats/statdb.hh:
base/stats/text.cc:
base/stats/text.hh:
base/stats/types.hh:
base/stats/visit.cc:
base/stats/visit.hh:
base/str.cc:
base/str.hh:
base/time.cc:
base/time.hh:
base/trace.cc:
base/trace.hh:
base/userinfo.cc:
base/userinfo.hh:
cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/exetrace.cc:
cpu/exetrace.hh:
cpu/full_cpu/op_class.hh:
cpu/full_cpu/smt.hh:
cpu/inst_seq.hh:
cpu/intr_control.cc:
cpu/intr_control.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
cpu/pc_event.cc:
cpu/pc_event.hh:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/static_inst.cc:
cpu/static_inst.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/baddev.cc:
dev/baddev.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
dev/io_device.cc:
dev/io_device.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/pcireg.h:
dev/platform.cc:
dev/platform.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
dev/tsunami.cc:
dev/tsunami.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunami_uart.hh:
dev/tsunamireg.h:
docs/stl.hh:
kern/linux/linux.hh:
kern/linux/linux_syscalls.cc:
kern/linux/linux_syscalls.hh:
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/system_events.cc:
kern/system_events.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/dump_mbuf.hh:
kern/tru64/mbuf.hh:
kern/tru64/printf.cc:
kern/tru64/printf.hh:
kern/tru64/tru64.hh:
kern/tru64/tru64_events.cc:
kern/tru64/tru64_events.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/async.hh:
sim/builder.cc:
sim/builder.hh:
sim/debug.cc:
sim/debug.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/host.hh:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/process.cc:
sim/process.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/stat_control.cc:
sim/stat_control.hh:
sim/stats.hh:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
sim/system.cc:
sim/system.hh:
sim/universe.cc:
test/bitvectest.cc:
test/circletest.cc:
test/cprintftest.cc:
test/initest.cc:
test/lru_test.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/sized_test.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
test/tracetest.cc:
util/m5/m5.c:
util/m5/m5op.h:
util/tap/tap.cc:
    Updated Copyright
dev/console.cc:
dev/console.hh:
    This code isn't ours, and shouldn't have our copyright

--HG--
extra : convert_revision : 598f2e5eab5d5d3de2c1e862b389086e3212f7c4
2004-06-08 13:37:27 -04:00
Ali Saidi
e44fc6db33 Added ctlz and cttz instructions to isa_desc for use in the PAL code.
--HG--
extra : convert_revision : 74dec35113b795e792b7fc03947a05349a4ff669
2004-06-04 18:10:50 -04:00
Ali Saidi
caf5cad959 Merge saidi@zizzer:/z/m5/Bitkeeper/m5/
into zeep.eecs.umich.edu:/z/saidi/work/m5

--HG--
extra : convert_revision : 89e0bdd427b23a8f52b8ba53b18451df7be22f14
2004-06-01 16:03:16 -04:00
Steve Reinhardt
53dde8579b Renamed OpClass enum members: they all end in 'Op' now.
Got rid of two inconsistent sets of strings that corresponded
to this enum, and replaced with a single set that clearly
matches the enum names.

arch/alpha/isa_desc:
arch/isa_parser.py:
cpu/full_cpu/op_class.hh:
    Renamed OpClass enum members.

--HG--
extra : convert_revision : bf596f7568a20b2e77c07ac349f253135141aef4
2004-05-31 16:19:31 -07:00
Ali Saidi
93983de0cf Merged head into linux tree
base/stats/mysql.hh:
    Rename of Statsistics namespace to stats... merge from head

--HG--
extra : convert_revision : a5a7f6268b35e75fba1b1800a74fcd6dbd09d974
2004-05-31 18:58:54 -04:00
Kevin Lim
6964ecd1cf Updated FastCPU model with all the recent changes.
arch/alpha/ev5.cc:
    Updated to support new forms of setIntReg and setFloatRegDouble.  Will need to be cleaned up in the future.
arch/isa_parser.py:
    Added in FastCPU model.

--HG--
extra : convert_revision : 384a27efcb50729ea6c3cc11653f395c300e48db
2004-05-28 14:42:59 -04:00
Kevin Lim
67b5f6afc1 Merged in new FastCPU stuff with existing code.
arch/alpha/ev5.cc:
    Added templatized processInterrupts() function that can be used by all of the CPU models.
arch/alpha/isa_desc:
    Merged in changes to remove CPU dependence.
arch/isa_parser.py:
    Merged in changes.
cpu/static_inst.hh:
    Includes FastCPU execute methods.

--HG--
extra : convert_revision : fcaa1dca35a9b316c73982bec8680df564f50bd8
2004-05-28 11:41:52 -04:00
Kevin Lim
a896960cbf FastCPU model added. It's very similar to the SimpleCPU, just without a lot of the stats tracking.
Also various changes to make the CPU model less ISA dependent, which includes moving the code that checks for interrupts up to the ISA level, moving code that zeroes the zero registers up to the ISA level, and removing opcode and ra from the regfile.

arch/alpha/alpha_memory.cc:
    The regfile has been changed so it no longer has the opcode and ra.  Instead the xc holds the actual instruction, and from there the opcode and ra can be obtained with OPCODE() and RA().
arch/alpha/ev5.cc:
    Moved code that once existed within simpleCPU to ev5, and templatized it.
    This way the CPU models can call processInterrupts and the ISA specific interrupt handling is left to the ISA's code.
    Also moved ISA specific zero registers from simpleCPU to here.
arch/alpha/ev5.hh:
    Added macros for obtaining the opcode and ra from the instruction itself, as there is no longer opcode or ra in the regfile.
arch/alpha/isa_desc:
    Added in declarations for the FastCPU model.
arch/alpha/isa_traits.hh:
    Removed opcode and ra from the regfile.  The xc now holds the actual instruction, and the opcode and ra can be obtained through it.
    Also added the declaration for the templated zeroRegisters() function, which will set the zero registers to 0.
arch/isa_parser.py:
    Added in FastCPUExecContext so it will generate code for the FastCPU model as well.
cpu/exec_context.cc:
    Added in a more generic trap function so "ev5_trap" doesn't need to be called.  It currently still calls the old method, with plans for making this ISA dependent in the future.
cpu/exec_context.hh:
    Exec context now has the instruction within it.  Also added methods for exec context to read an instruction from memory, return the current instruction, and set the instruction if needed.
    Also has declaration for more generic trap() function.
cpu/simple_cpu/simple_cpu.cc:
    Removed references to opcode and ra, and instead sets the xc's instruction with the fetched instruction.
cpu/static_inst.hh:
    Added declaration for execute() using FastCPUExecContext.

--HG--
extra : convert_revision : 0441ea3700ac50b733e485395d4dd4ac83666f92
2004-05-27 17:46:16 -04:00
Nathan Binkert
f622d74f81 add a few statistics events
arch/alpha/ev5.cc:
    Add an event for faults
cpu/simple_cpu/simple_cpu.cc:
    add events for uncached reads/writes

--HG--
extra : convert_revision : 747bdf12761e2de6ebbf54fecc9e0b71915b3a02
2004-05-21 13:58:39 -04:00
Nathan Binkert
62d756f253 rename namespace Statistics to Stats
--HG--
extra : convert_revision : 28f1703f8d7d8cf33fb952ae450f66bdba860fb7
2004-05-21 13:39:20 -04:00
Nathan Binkert
b4405682d9 Change the namespace Statistics to Stats
--HG--
extra : convert_revision : 3084b292bbe2e8a392af8e99a31763ca0b0a9467
2004-05-21 13:03:17 -04:00
Andrew Schultz
f5c7b1358c Remove the uncacheable bit 39 check (needs to be merged in with head tree
if Tru64 is to continue to be supported on Turbolaser) and fixed
translation of physical addresses by clearing PA<42:35> when the real
uncachable bit (43) is set

arch/alpha/ev5.hh:
    Change to support 256 ASNs and seperate VA_SPACE checks for EV5 and EV6
    also add support proper translation of uncacheable physical addresses
dev/ide_ctrl.cc:
    Fix to work with real address translation

--HG--
extra : convert_revision : aa3d1c284b8271d4763a8da2509c91bbcf83189a
2004-05-19 15:58:24 -04:00
Steve Reinhardt
4c55d26e66 Replace explicit xc->misspeculating() tests in execute() methods
with an IsNonSpeculative flag.
No effect on results of non-full-system or SimpleCPU.
Very small impact on full-system FullCPU runs since old wrong-path
call_pal insts used to change the PC, where now they're treated
as no-ops.

arch/alpha/isa_desc:
    Get rid of xc->misspeculating() checks, use IsNonSpeculative flag instead.
cpu/static_inst.hh:
    Add IsNonSpeculative flag and isNonSpeculative() method to test it.

--HG--
extra : convert_revision : 7ec536bfc28b905c429c09eb920ed73ef2beeeba
2004-05-18 16:09:02 -07:00
Lisa Hsu
a0ccdf8aba merge m5 with linux for the event and binning lifting
--HG--
extra : convert_revision : 09d3678746c2e9a93a9982dc75d5e1ac309cb2fa
2004-05-18 01:40:03 -04:00
Steve Reinhardt
1d545281b9 Significant changes to ISA description to completely factor
out CPU model.  ISA description now generates multiple
output source files to (in theory) reduce compilation time.

arch/alpha/isa_desc:
    Update for parser changes.  Move most constructors
    out of class declarations (which are now in decoder.hh)
    and into decoder.cc.  Move all execute() methods into
    exec output.
arch/isa_parser.py:
    Significant changes to make ISA description completely
    independent of CPU model, and isolate model-dependent parts
    of parser into one little class (CpuModel).  Also split up code
    output into multiple files (a header, a main source file, and
    per-cpu execute() method files).

    Noticeable changes to language as a result.  See updated Doxygen
    documentation.
cpu/simple_cpu/simple_cpu.hh:
    SimpleCPUExecContext typedef no longer needed.
    Add forward declaration of Process.
cpu/static_inst.hh:
    SimpleCPUExecContext and FullCPUExecContext typedefs no longer needed.
    Make eaCompInst() and memAccInst() return const refs.

--HG--
extra : convert_revision : 71471f267804fafd0a881bac7445677e76334daf
2004-05-17 11:49:46 -07:00
Nathan Binkert
f13926c099 Add VPtr class that makes it possible to esentially create
a pointer to an object that lives inside simulated memory.
Useful for doing a bit of analysis of what's going on in
the running kernel.

--HG--
extra : convert_revision : d78089cce5ec4334483a710ba512eaf18d9b0319
2004-05-13 08:08:42 -04:00
Nathan Binkert
2d8777a79b remove the annotation junk
arch/alpha/isa_desc:
    remove the annotation junk
    Move some code to AlphaPseudo where it belongs
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
    remove the annotation junk
    add pseudo instruction code that was previously misplaced

--HG--
extra : convert_revision : 97db8402aa34e0bdf044b138c52331fc9e714986
2004-05-13 08:03:36 -04:00
Nathan Binkert
8bc3ce93cb pass the address of both the old an new pcbb on context
switches.  (Makes other uncommitted code easier to merge.)

arch/alpha/ev5.cc:
    pass the address of both the old an new pcbb on context
    switches

--HG--
extra : convert_revision : bff8c8d1b532ad5f9af6270169bbfb1b5c05256a
2004-05-13 07:28:54 -04:00
Lisa Hsu
16800971d0 successful merge, linux still builds and runs as far it used to, network device still transmit ARP packet.
arch/alpha/alpha_memory.cc:
    change to the main m5 tree convention for naming
base/traceflags.py:
    add ide and pciconfigall traceflags
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
    kill some old binning styled stuff

--HG--
extra : convert_revision : 0558878906817975a714b1c7c08f9ee405468535
2004-05-11 22:42:45 -04:00
Lisa Hsu
a5f90eba3b first pass at merging m5 with linux
--HG--
extra : convert_revision : dfe23349b80ae3b34d3cb95c5734e01ef62f700e
2004-05-11 01:15:18 -04:00
Steve Reinhardt
7cab07268f Do a better job of factoring out CPU model in ISA description.
(Still not perfect though.)

arch/alpha/isa_desc:
    Do a better job of factoring out CPU model.  (Still not perfect though.)
    Pull execute() methods out of class declarations into separate section
    of file, allowing (1) easier replication for different CPU models and
    (2) a path to putting them all in a separate file.  Force all instruction
    execution context into a single model-dependent class (SimpleCPU itself
    for SimpleCPU, DynInst for FullCPU).
arch/isa_parser.py:
    Do a better job of factoring out CPU model.  (Still not perfect though.)
    Pull execute() methods out of class declarations into separate section
    of file, allowing (1) easier replication for different CPU models and
    (2) a path to putting them all in a separate file.
    Also restructure top level to allow parser to run under interactive
    interpreter session for easier debugging.
cpu/exec_context.hh:
    Add a few new methods to clean up isa_desc.
cpu/simple_cpu/simple_cpu.cc:
cpu/static_inst.hh:
    StaticInst::execute no longer takes a CPU and an ExecContext,
    just a unified FooCPUExecContext.
cpu/simple_cpu/simple_cpu.hh:
    Add methods to redirect calls to ExecContext so SimpleCPU
    can act as sole instruction execution context for itself.
    Typedef SimpleCPU to SimpleCPUExecContext.

--HG--
extra : convert_revision : ecc445503bc585585da5663fe61796580e744da6
2004-05-10 16:10:47 -07:00
Ali Saidi
3c7071a6be Added ULL for 64bit ints
Added function to skip determine_cpu_caches(). We may have to update this in the
future: see note below.

arch/alpha/alpha_memory.cc:
dev/ide_ctrl.cc:
dev/tsunamireg.h:
    Added ULL for 64bit ints
kern/linux/linux_system.cc:
    Added a function to skip determine_cpu_caches, right now it is only used for
    printing in proc, however in the future we may either want to implement the SC_CTL
    IPR register or manually set alpha_l1i_cacheshape, alpha_l1d_cacheshape,
    alpha_l2_cacheshape, alpha_l3_cacheshape to ((size << 10) | (linesize>>1)<<4 | way)
kern/linux/linux_system.hh:
    added event to skip determine_cpu_caches()

--HG--
extra : convert_revision : 1065f2091bbe6832b730af490f5b4672c2afedce
2004-05-09 20:14:18 -04:00
Andrew Schultz
4a5dcc37bf Whole mess'o'changes.. see individual files
arch/alpha/vtophys.cc:
    Removed buggy code that tries to fix PAL addresses (may cause problems
    while trying to debug in PAL code, but that should do this fix outside
    of vtophys)
base/loader/symtab.cc:
base/loader/symtab.hh:
cpu/exetrace.cc:
    Changed InstExec traces to always print a symbol name
dev/ide_ctrl.cc:
dev/ide_disk.cc:
    Tabs
dev/ide_disk.hh:
    Change buffer size
dev/tsunami_pchip.cc:
    Fix translatePciToDma to support scatter gather mapping
kern/linux/linux_system.cc:
    Force simulator to wait until remote debugger attaches (should be removed
    or turned on/off with a flag)

--HG--
extra : convert_revision : 1d08aebe3f448c87a963dd613de3e2e0cff0d48d
2004-05-06 15:21:07 -04:00
Nathan Binkert
25a358983a Major stats package cleanup
Add support for generic visitors for stats and use them
to implement independent output functions.

Support for mysql output and some initial code for hacking
on mysql output with python

arch/alpha/pseudo_inst.cc:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/sat_counter.cc:
base/sat_counter.hh:
cpu/simple_cpu/simple_cpu.cc:
kern/tru64/tru64_events.cc:
sim/main.cc:
sim/process.cc:
sim/process.hh:
sim/sim_events.cc:
sim/sim_object.cc:
sim/system.hh:
    update for changes in stats package
base/statistics.cc:
    move the python output code to base/stats/puthon.(cc|hh)
    and reimplement it as a visitor.

    move the text output code to base/stats/text.(cc|hh) and
    reimplement it as a visitor.

    move the database stuff into base/stats/statdb.(cc|hh) and
    get rid of the class.  Put everything as globals in the
    Statistics::Database namespace.

    allocate unique ids for all stats.

    directly implement the check routine and get rid of the
    various dumping routines since they're now in separate files.

    make sure that no two stats have the same name

    clean up some loops
base/statistics.hh:
    major changes to the statistics package again

    lots of code was factored out of statistics.hh into several
    separate files in base/stats/ (this will continue)

    There are now two Stat package types Result and Counter that
    are specified to allow the user to keep the counted type
    separate from the result type.  They are currently both doubles
    but that's an experiment.  There is no more per stat ability to
    set the type.  Statistics::Counter is not the same as Counter!

    Implement a visitor for statistics output so that new output
    types can be implemented independently from the stats package
    itself.

    Add a unique id to each stat so that it can be used to keep
    track of stats more simply.  This number can also be used in
    debugging problems with stats.

    Tweak the bucket size stuff a bit to make it work better.

    fixed VectorDist size bug
cpu/memtest/memtest.cc:
    Fix up for changes in stats package
    Don't use value() since it doesn't work with binning.  If you
    want a number as a stat, and to use it in the program itself,
    you really want two separate variables, one that's a stat,
    and one that's not.
cpu/memtest/memtest.hh:
    Fix up for changes in stats package
test/Makefile:
    Try to build stuff now that directories matter
test/stattest.cc:
    test all new output types
    choose which one with command line options

--HG--
extra : convert_revision : e3a3f5f0828c67c0e2de415d936ad240adaddc89
2004-05-04 17:01:00 -04:00
Steve Reinhardt
d4069233eb Beta version of Python configuration tool. Generates .ini files from
Python script description.

arch/alpha/alpha_memory.cc:
dev/io_device.cc:
    Add DEFINE_SIM_OBJECT_CLASS_NAME for intermediate SimObjects.
test/paramtest.cc:
    Fix stupid spelling.

--HG--
extra : convert_revision : dc020208cb6507c1afb1ed771a7218daba678e09
2004-04-06 10:02:00 -07:00
Steve Reinhardt
65205b82ac More {Itb,Dtb} -> {ITB,DTB} renames (forgot to test build KERNEL).
Also missed renames in a bunch of config files somehow.
(See previous changeset for list of renames.)

arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/faults.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple_cpu/simple_cpu.hh:
    More {Itb,Dtb} -> {ITB,DTB} renames (forgot to test build KERNEL).

--HG--
extra : convert_revision : b2c6ca0916b72b59895520fcacaf028667560a0d
2004-04-03 13:46:10 -08:00
Steve Reinhardt
782fb42992 Basic cleanup pass to get rid of a few things that made the Python
configuration unnecessarily awkward.  Biggest changes are:

- External and internal object names now match in all cases.  The
macros still allow them to be different; the only reason I didn't
get rid of that is that the macros themselves should be going away
soon.  In the few conflicting cases, I sometimes renamed the C++ object
and sometimes renamed the config object.  The latter sets of substitions
are:

s/BaseBus/Bus/;
s/MemoryObject/FunctionalMemory/;
s/MemoryControl/MemoryController/;
s/FUPool/FuncUnitPool/;

- SamplingCPU is temporarily broken... we need to change the model
of how this works in the .ini file.  Having it as a CPU proxy is
really awkward.

arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
cpu/simple_cpu/simple_cpu.cc:
sim/process.cc:
    Rename objects to match config name.
cpu/base_cpu.cc:
    Uncomment SimObject define since SamplingCPU no longer
    does this for us.
dev/ethertap.cc:
    Use unsigned instead of uint16_t for params.
kern/tru64/tru64_system.cc:
    Use unsigned instead of uint64_t for init_param param.
test/paramtest.cc:
    Fix old SimObjectParam.

--HG--
extra : convert_revision : 378ebbc6a71ad0694501d09979a44d111a59e8dc
2004-04-02 22:57:08 -08:00
Nathan Binkert
832a0917cf ULL()
--HG--
extra : convert_revision : 543313ec248457e6cb2f8315881f030545e8cf45
2004-03-24 02:59:43 -05:00
Lisa Hsu
3bc8cffc75 merge with m5 head
--HG--
extra : convert_revision : c90339248d1ee74df1c6b90a77ec9ea41f646311
2004-03-11 18:52:29 -05:00
Erik Hallnor
1d09cd71a4 Reenable functioning copies.
arch/alpha/isa_desc:
    Reenable copies.

--HG--
extra : convert_revision : 99259c0ff65e742e617cba1c14f5d1bf4be2fee8
2004-03-04 20:03:38 -05:00
Erik Hallnor
8ad803058f Automerged
--HG--
extra : convert_revision : 7b56535ee32551f27db8d98172159f63e5099835
2004-03-04 15:06:34 -05:00
Erik Hallnor
7c089b2001 Copy implementations
arch/alpha/isa_desc:
    Need to return fault for copy operations.
cpu/exec_context.hh:
    Add temporary storage to pass source address from copy load to copy store
cpu/simple_cpu/simple_cpu.cc:
    Implement copy functions.
cpu/simple_cpu/simple_cpu.hh:
    Return fault

--HG--
extra : convert_revision : 98e5ce563449d6057ba45c70eece9235f1649a90
2004-03-04 14:57:57 -05:00
Erik Hallnor
cbc42f1d71 Remove copys from isa_desc, and implement a store and forward bus bridge
arch/alpha/isa_desc:
    Just to make sure, remove the new copy instructions until everything works.

--HG--
extra : convert_revision : cdd3d4c8fa415175aaee04f4a99340dcf82dbc3a
2004-02-29 22:41:11 -05:00
Nathan Binkert
27960f6d85 fix rpcc
arch/alpha/ev5.cc:
    actually implement the cycle count register
arch/alpha/isa_desc:
    the rpcc instruction really just reads the cycle count
    register

--HG--
extra : convert_revision : a0edec85672377a62b90950efc17b62b375220b1
2004-02-29 14:54:52 -05:00
Steve Reinhardt
c79deda8cd Fix handling of rpcc in full-system mode.
arch/alpha/ev5.cc:
    Handle writing IPR_CC and IPR_CC_CTL slightly more intelligently.
    (Very slightly).
arch/alpha/isa_desc:
    Upper half of rpcc result comes from value written
    to IPR_CC, not actual cycle counter.

--HG--
extra : convert_revision : 7161989db8a3f040d0558e2e5a1a162ed1cb4125
2004-02-28 17:21:32 -05:00
Erik Hallnor
cfb6f8fd01 Added copy instructions to the ISA. Well it didn't break anything yet...
arch/alpha/isa_desc:
    Add copy_load and copy_store insts (ldf and stf respectively)
cpu/simple_cpu/simple_cpu.hh:
    Add copy functions to SimpleCPU as well

--HG--
extra : convert_revision : 1fa041da582b418c47d4eefc22dabba978a50e2d
2004-02-27 02:40:43 -05:00
Erik Hallnor
c3784e37ce Initial copy support in the pipeline. Add copypal counting.
arch/alpha/osfpal.cc:
    Add a string for copypal.
arch/alpha/osfpal.hh:
    Add a code for copypal.
cpu/static_inst.hh:
    Add an IsCopy flag.

--HG--
extra : convert_revision : 19e3d90368454806029ad492eace19cd0924fe9f
2004-02-27 00:45:21 -05:00
Steve Reinhardt
6f5e104fc5 Make SW prefetch flag a parameter again, and add code to make
it actually do something on FullCPU.  Still disabled, as it
causes detailed-boot to hang when you turn it on.

arch/alpha/isa_desc:
    Add EAComp and MemAcc pseudo-instructions to prefetch StaticInst.
cpu/simple_cpu/simple_cpu.hh:
    Changed prefetch() return type from Fault to void.

--HG--
extra : convert_revision : c7cb42682bfea6af117c87d4dfdb06176b6fe6b7
2004-02-26 07:05:36 -08:00
Andrew Schultz
d4637757f8 Remote an old hack that is now unnecessary
base/cprintf_formats.hh:
    Add additional format modifiers

--HG--
extra : convert_revision : f9ec0a664eeb96db7dacacd6b7636e3cb47555e7
2004-02-19 16:32:13 -05:00
Andrew Schultz
e3fb3d1ad0 Misspeculation fix and (more importantly) change to allow for the ev6 style
physical addressing.  This has the uncacheable bit as bit 40 as opposed
to bit 39.  Additionally, we now support (at least superficially) a 44-bit
physical address.  To deal with superpage access in this scheme, any super
page access with either bit 39 or 40 set is sign extended.

--HG--
extra : convert_revision : 05ddbcb9a6a92481109a63b261743881953620ab
2004-02-19 16:30:06 -05:00
Andrew Schultz
12747d3084 Change the physical memory logic, and also add misspeculation fix to
tlb index calls that are called from ExecContext::readIpr

arch/alpha/ev5.cc:
    Fix misspeculation bugs for misspeculated IPR accesses

--HG--
extra : convert_revision : c9ffcf9ef8123dfcaee1606c05aee8ad60d893d7
2004-02-18 21:38:55 -05:00
Andrew Schultz
59a6e9d705 Merge
arch/alpha/alpha_memory.cc:
    SCCS merged

--HG--
extra : convert_revision : 0348e29c833684fd593a6c02913319f45f24e76e
2004-02-16 22:04:55 -05:00
Andrew Schultz
a73e263f94 Change logic for translating a memory addresses, extra checks for invalid
physical addresses.

--HG--
extra : convert_revision : efb4a5229d88cb3c024e0b24f5916048bd42d589
2004-02-16 21:56:38 -05:00
Andrew Schultz
9984412671 Fix bug with physical address translation
--HG--
extra : convert_revision : 2bfc338decdceaaf57f4a391b93882a8e0715a56
2004-02-15 16:33:16 -05:00
Andrew Schultz
092ec1978d Fix to remote debugger while in PAL
arch/alpha/vtophys.cc:
base/remote_gdb.cc:
    Fix to remote debugger while in PAL code
dev/pcidev.cc:
    Remove extra debug printf

--HG--
extra : convert_revision : e64988846ad05cd3ddf47034d72d99dae3501591
2004-02-13 18:15:04 -05:00
Nathan Binkert
8232c9743d fix up vtophys a bit
arch/alpha/vtophys.cc:
    fix up vtophys to deal with translations if there
    is no ptbr, and to deal with PAL addresses
    add ptomem which is just a wrapper for dma_addr
arch/alpha/vtophys.hh:
    add ptomem which is a wrapper for dma_addr with the
    same usage as vtomem

--HG--
extra : convert_revision : 1ae22073d400e87b708a4a7ef501124227fc6c39
2004-02-13 15:36:21 -05:00
Steve Reinhardt
5e82f8d84c Merge zizzer:/bk/m5 into isabel.reinhardt.house:/z/stever/bk/m5
--HG--
extra : convert_revision : 964126edcf72faf572a9272599264ba2f5cd7aa1
2004-02-10 21:44:08 -08:00
Steve Reinhardt
d38f995aee Fixes for Linux syscall emulation.
arch/alpha/alpha_linux_process.cc:
    Fixes for Linux emulation:
    - stat struct alignment
    - osf_{get,set}sysinfo return values
    - additional syscall numbers
    - initialize $r0 to 0
sim/syscall_emul.cc:
    brk(0) just returns brk value (don't update it!)

--HG--
extra : convert_revision : 78e22458321c81e81540d101c9e65e2e4b0ad117
2004-02-10 21:43:57 -08:00
Nathan Binkert
087334bfe5 Merge zizzer.eecs.umich.edu:/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/.automount/ziff/z/binkertn/research/m5/memory

--HG--
extra : convert_revision : 9f385ee5b6958373a9a1bc600eb3e5e8b7987f38
2004-02-09 10:36:32 -05:00
Nathan Binkert
411d5497fa Add that one IPR memory space address that we keep seeing
--HG--
extra : convert_revision : 81b365ac9ca8b33cae99107e5b1900f7c46f0866
2004-02-09 09:06:20 -05:00
Steve Reinhardt
730296f7f9 Results of automatic (yet incomplete) merge.
--HG--
extra : convert_revision : 3ad9a929051bfe111a1e10618c8595acbbade542
2004-02-09 00:30:16 -08:00
Steve Reinhardt
d7b7363444 Add support for memory barriers.
arch/alpha/isa_desc:
    Add cache port bindings for mb & wmb.

--HG--
extra : convert_revision : 72f76150fe471d0dc97bd41598cad4d86a035e39
2004-02-09 00:22:43 -08:00
David Oehmke
95c248c213 Modify the emulated system calls to support running the SPEC Int
benchmarks for alpha-linux.

arch/alpha/alpha_linux_process.cc:
    Added some more ioctl commands to ignore.
    Set unlink and rename to the new functions.
    Ignore setrlimit, times and rt_sigaction.
    Should eventually provide a function for times.
arch/alpha/alpha_tru64_process.cc:
    Added some more ioctl commands to ignore.
    Set unlink and rename to the new functions.
    Ignore setrlimit.
sim/syscall_emul.cc:
    Added implementations for unlink and rename.
sim/syscall_emul.hh:
    Added unlink and rename functions.
    Added a couple more ioctl requests to ignore.
    Print out the PC of any ioctl commands that fail.

--HG--
extra : convert_revision : 8af21c7fa7d0645d3f9324c9ce70ad33590c3c8e
2004-02-05 12:16:17 -05:00
Steve Reinhardt
b6ff600bca Add support for "serializing" instructions that flush
execution pipeline (Alpha trapb & excb).

Add support for write memory barriers (mostly impacts
store buffer).

Add StaticInst flag to indicate memory barriers, though
this is not modeled in the pipeline yet.

arch/alpha/isa_desc:
    Implement trapb, excb, mb, and wmb as insts with
    no execution effect (empty execute() function) but
    with flags that indicate their side effects.

    Also make sure every instruction that needs to go to
    the execute stage has a real opClass value, since we
    are now using No_OpClass to signal insts that can get
    dropped at dispatch.

    StaticInst::branchTarget() is now a const method.
cpu/static_inst.hh:
    Add flags to indicate serializing insts (trapb, excb) and
    memory and write barriers.

    Also declare some StaticInst methods as const methods.
dev/etherlink.hh:
sim/eventq.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_object.hh:
    Make name() return value const.

--HG--
extra : convert_revision : 39520e71469fa20e0a7446b2e06b494eec17a02c
2004-02-04 21:42:00 -08:00
Steve Reinhardt
3e5070a3f1 Fix bug: forgot branchTarget() method on indirect branches.
arch/alpha/isa_desc:
    Add missing branchTarget() method for indirect branches.
cpu/static_inst.hh:
    Add comment clarifying when branchTarget() can be used
    on indirect branches.

--HG--
extra : convert_revision : 0dcfb36a9792a338cefceb3d1501825abace7ac5
2004-02-03 07:19:05 -08:00
Steve Reinhardt
7b07b0877f Change MemReqPtr parameters to references.
This avoids incrementing and decrementing the MemReq
reference counters on every call and return.

arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
cpu/exec_context.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
    Change MemReqPtr parameters to references.

--HG--
extra : convert_revision : 3ba18bdd9f996563988402576bfdd3430e1ab1e5
2004-02-02 10:47:21 -08:00
Nathan Binkert
801c46d250 a bunch of warning fixes
arch/alpha/isa_desc:
    don't say warn: Warning:
base/misc.cc:
    avoid printing two newlines in a row
sim/main.cc:
    print out a message just before we enter the event queue

--HG--
extra : convert_revision : 2a824d4b67661903fc739a0fb0759aa91d72382c
2004-01-27 17:56:23 -05:00
Erik Hallnor
003d2d724c Merge ehallnor@zizzer:/bk/m5 into zazzer.eecs.umich.edu:/z/ehallnor/m5
--HG--
extra : convert_revision : 52437e42f15899db46525ad91b2e43c2a96ace36
2004-01-13 02:10:48 -05:00
Erik Hallnor
413bfc68e6 Change to a new centralized way to specify the memory hierarchy parameters (do_data and do_events). If you use the defaults (false and true respectively) you don't have to change your INI files.
arch/alpha/isa_traits.hh:
    Add a constant for the maximum address value called MaxAddr.

--HG--
extra : convert_revision : 1371e8b713cc6ed134093e9c208db35dc9741ac7
2004-01-13 02:10:35 -05:00
Steve Reinhardt
510eef0fa0 Modify handling of serialize:dir parameter to make it more useful.
Move global checkpoint-related functions and vars into Checkpoint class (as statics).

arch/alpha/pseudo_inst.cc:
dev/disk_image.cc:
    Move global checkpoint-related functions and vars
    into Checkpoint class (as statics).
sim/serialize.cc:
    Move global checkpoint-related functions and vars
    into Checkpoint class (as statics).

    Checkpoint constructor now takes checkpoint directory name instead
    of file name.

    Make serialize:dir parameter actually set checkpoint directory name
    instead of directory in which checkpoint directory is created.  If
    the value contains a '%', the curTick value is sprintf'd into the
    format to create the directory name.  The default is backwards compatible
    with the old fixed name ("m5.%012d").
sim/serialize.hh:
    Move global checkpoint-related functions and vars
    into Checkpoint class (as statics).

    Checkpoint constructor now takes checkpoint directory name instead
    of file name.

--HG--
extra : convert_revision : d0aa87b62911f405a4f5811271b9e6351fdd9fe4
2004-01-11 15:24:18 -08:00
Nathan Binkert
255ac8372d Make stuff build on openbsd
arch/alpha/alpha_tru64_process.cc:
    So, I don't know why linux uses an off_t here.
    I'm also not sure why linux defines an off_t to be a long
    Let's just use long here since it works for linux, and that's
    what bsd does
base/inifile.cc:
    correct #include for OpenBSD
dev/disk_image.cc:
    the correct type for this is streampos

--HG--
extra : convert_revision : f3ac3a3b8515d66e07ffb9780d8a9e387297b6a0
2003-12-19 00:02:20 -05:00
Steve Reinhardt
16021aa436 Fix previously committed call_pal fix... the main problem was in the
makefile, such that decoder.cc was not getting rebuilt.
Also add -fno-strict-aliasing to fix all the bizarre problems
I've been having with g++ 3.3.x.

arch/alpha/isa_desc:
    Fix compilation problems.  AlphaISA is a class now, not a namespace.

--HG--
extra : convert_revision : 1583cebc1258c57cbd286c1955d11648150fa1f4
2003-12-16 11:46:52 -08:00
Steve Reinhardt
2cd5e980d2 Fixes for full-system call_pal instruction.
arch/alpha/alpha_memory.cc:
    Rename md_mode_type to mode_type.
arch/alpha/ev5.cc:
    simPalCheck() only gets called on correct path now, so
    there's no need to test misspeculating().
arch/alpha/isa_desc:
    Get privileged call_pall detection right this time (I hope).
    ExecContext::simPalCheck() and Annotate::Callpal() are now
    called only on non-speculative executions... this should fix
    the bogus pal-call stats we've been seeing (since these are
    incremented in simPalCheck()).
    Also check for invalid call_pall function codes.

--HG--
extra : convert_revision : 465d6724884007d3fa066d14cd5e6db0cd3954e1
2003-12-15 21:06:09 -08:00
Steve Reinhardt
777c1ebfab Stats & serialization tweaks & cleanup. Unserializing from
a checkpoint now gives identical results to running from scratch
and doing at switchover at the same cycle!
- CPUs start at cycle 0 again, not cycle 1.
- curTick is now serialized & unserialized.
- Stats get reset in main (before event loop).  Since this is done
after curTick is unserialized, simTicks gets set correctly for
running from a checkpoint.
- Simplify serialization to happen in a single pass.
- s/Serializeable/Serializable/

arch/alpha/isa_traits.hh:
dev/etherlink.hh:
sim/eventq.cc:
sim/eventq.hh:
    s/Serializeable/Serializable/
kern/tru64/tru64_system.cc:
sim/process.cc:
    Make initial CPU activation on cycle 0 again (not 1).
sim/main.cc:
    Reset stats before getting started.
    Make error message on falling out of event loop
    more meaningful.
sim/serialize.cc:
sim/serialize.hh:
    Get rid of now-useless initial pass; serialization is
    done in a single pass now.
    Serialize & unserialize curTick.
    Wrap curTick and mainEventQueue in a "globals" Serializable object.
    s/Serializeable/Serializable/
sim/sim_object.cc:
    Add static function to serialize all SimObjects.
sim/sim_object.hh:
    Add static function to serialize all SimObjects.
    s/Serializeable/Serializable/

--HG--
extra : convert_revision : 9dcc411d0009b54b8eb61c3a509680b81b9f6f68
2003-12-11 00:16:46 -08:00
Steve Reinhardt
4ce6118fda Factor ExecContext::setStatus(), BaseCPU::execCtxStatusChange(),
and SimpleCPU::setStatus() into separate functions.  For example,
setStatus(Active) is now activate().

--HG--
extra : convert_revision : 4392e07caf6c918db0b535f613175109681686fe
2003-12-10 17:47:28 -08:00
Steve Reinhardt
f13509e968 Generate a fault when a privileged PAL call is
executed in non-privileged (non-PAL) mode.

--HG--
extra : convert_revision : c8823a1eec27d801a1ed6110ade07354c4dd2a32
2003-12-09 14:19:35 -08:00
Steve Reinhardt
9984b2bd6c Formatting & doxygen docs for new syscall emulation code.
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/alpha_tru64_process.hh:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Formatting & doxygen.

--HG--
extra : convert_revision : 4f07dd37e254120800dd0d5c0eb47acc9c00cb3f
2003-12-01 22:39:27 -08:00
Steve Reinhardt
7976794aad Restructuring of LiveProcess etc. to support multiple emulated OS syscall
interfaces, and specific support for Alpha Linux.  Split syscall emulation
functions into several groups, based on whether they depend on the specific
OS and/or architecture (and all combinations of above), including the use of
template functions to support syscalls with slightly different constants
or interface structs.

arch/alpha/alpha_tru64_process.cc:
    Incorporate full Tru64 object definition here, including structure and constant definitions.
    This way we can wrap all of the functions inside the object, and not worry about namespace
    conflicts because no one outside this file will ever see it.
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.cc:
base/loader/object_file.hh:
    Add enums to ObjectFile to indicate the object's architecture and operating system.
cpu/exec_context.cc:
    prog.hh is now process.hh
cpu/exec_context.hh:
    prog.hh is now process.hh
    move architecture-specific syscall arg accessors into ExecContext
cpu/simple_cpu/simple_cpu.cc:
    No need to include prog.hh (which has been renamed)
sim/process.cc:
sim/process.hh:
    LiveProcess is now effectively an abstract base class.
    New LiveProcess::create() function takes an object file and dynamically picks the
    appropriate subclass of LiveProcess to handle the syscall interface that file expects
    (currently Tru64 or Linux).

--HG--
rename : arch/alpha/fake_syscall.cc => arch/alpha/alpha_tru64_process.cc
rename : sim/prog.cc => sim/process.cc
rename : sim/prog.hh => sim/process.hh
extra : convert_revision : 4a03ca7d94a34177cb672931f8aae83a6bad179a
2003-12-01 19:34:38 -08:00
Steve Reinhardt
0a7f82da7d Rewrite getdirentries to replace SS-derived version.
--HG--
extra : convert_revision : 72eced315bbb331d3068279e60f1f0a390eb687a
2003-11-12 08:40:32 -08:00
Nathan Binkert
7f7dcf4e1f add a couple of hacks to get thigns going for ISCA
arch/alpha/pseudo_inst.hh:
    Give temporary access of these functions to full cpu junk
    (this is a hack!)

--HG--
extra : convert_revision : 35499d6bf03b1c21dc918ccc09a6d21719262120
2003-11-07 05:06:22 -05:00
Steve Reinhardt
e4b52476bc Automerge
--HG--
extra : convert_revision : 2ca18ecbf04a1de72391073d0a5309fdbbdfefda
2003-11-03 20:35:05 -08:00
Steve Reinhardt
02795babaf Fix bugs in and expand syscall emulation code.
arch/alpha/fake_syscall.cc:
    Fix a couple of bugs:
    - error return codes weren't making it through due to inadvertent cast to unsigned
    - sigreturn broken in not one but two ways
    - make all file descriptors look like plain files (not ttys)
    Added implementations of setuid, getgid, fcntl, and getdirentries from Dave Oehmke

--HG--
extra : convert_revision : 53d3f13e1b05e3bde9e68ada3774ca39fa4c0d4c
2003-11-03 20:31:15 -08:00
Steve Reinhardt
40b9a3878a Minor changes to instruction trace output.
arch/alpha/isa_desc:
    A few disassembly changes to make it easier to compare with old machine.def traces:
    - Make lds prefetches print f31 instead of r31 as dest.
    - Don't print mode suffixes on FP if SS_COMPATIBLE_DISASSEMBLY
cpu/exetrace.cc:
    Left-justify instruction in field, and increase width by 1.

--HG--
extra : convert_revision : 9ffd56728f1bb772aa3ccda5f027b93d4c3a4135
2003-11-03 20:26:51 -08:00
Nathan Binkert
c55e6b495e Make it so the quiesce instruction is conditionally enabled
arch/alpha/isa_desc:
    move the quiesce instruction out of here so I can conditionally
    enable it.
arch/alpha/pseudo_inst.cc:
    conditionally enable quiesce
arch/alpha/pseudo_inst.hh:
    add quiesce

--HG--
extra : convert_revision : e1c474c4bf8761ff58073785d82b2bec9f632885
2003-11-03 16:47:08 -05:00
Nathan Binkert
491fb95919 ok, let's get this right
arch/alpha/pseudo_inst.cc:
    yes is not a real value, use true

--HG--
extra : convert_revision : 30b998ae6f13641d70c9158777a12b00df8742fe
2003-11-02 22:12:20 -05:00
Nathan Binkert
c307c22257 Fix a bug in the pseudo instruction context
arch/alpha/pseudo_inst.cc:
    Don't forget the descriptions

--HG--
extra : convert_revision : f208ea24d5b34283e962916cb4c7dff976406285
2003-11-02 21:58:23 -05:00
Nathan Binkert
136ee73a58 Add the option to ignore some of the pseudo instructions
--HG--
extra : convert_revision : 2010782749ca9c5dd029f71480956b8a1fa96394
2003-11-02 20:52:40 -05:00
Nathan Binkert
d76445f9f3 Move the m5 pseudo instructions into their own file
arch/alpha/isa_desc:
    Move the pseudo instructions out of the isa_desc, into their own
    file and call out to them when they're to be accessed
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
    move SimExit to sim_exit.cc

--HG--
extra : convert_revision : 1c393adb1c18bd0fef065057d7f4e9cf60ac4197
2003-11-02 20:43:39 -05:00
Nathan Binkert
667cbb6690 Implement more m5 pseduo opcodes:
resetstats
dumpstats
dumpresetstats
m5checkpoint

Lots of cleanup of serialization and stats dumping/resetting to
work with these new instructions

arch/alpha/isa_desc:
    Implement more m5 pseduo opcodes:
    resetstats
    dumpstats
    dumpresetstats
    m5checkpoint

    All of these functions take two optional parameters, the first is a delay,
    and the second is a period.  The delay tells the simulator to wait the
    specified number of nanoseconds before triggering the event, the period
    tells the simulator to repeat the event with a specified frequency
base/statistics.cc:
base/statistics.hh:
    regReset RegResetCallback
dev/disk_image.cc:
    serializeFilename -> CheckpointFile()
sim/debug.cc:
    Move this debugging statement to sim_stats.cc
sim/eventq.cc:
    Don't AutoDelete an event if it is scheduled since the process()
    function could potentially schedule the event again.
sim/main.cc:
    DumpStatsEvent is now Statistics::SetupEvent(Dump, curTick)
sim/serialize.cc:
    Change the serialize event so that it's possible to cause the
    event to repeat.  Also make the priority such that the event
    happens just before the simulator would exit if both events
    were scheduled for the same cycle.

    get rid of the serializeFilename variable and provide a CheckpointFile()
    function.  This function takes a basename that is set in the
    configuration, and appends the current cycle to the name so that
    multiple checkpoints can be dumped from the same simulation.

    Also, don't exit the simulation when a checkpoint file is dumped.
sim/serialize.hh:
    serializeFilename -> CheckpointFile()
    SetupCheckpoint function to tell the simulator to prepare
    to checkpoint at a certain time with a certain period
sim/sim_events.cc:
    DumpStatsEvent stuff gets move to sim_stats.(cc|hh)
    The context stuff gets moved into the already existing
    stats context in stat_context.cc
sim/sim_events.hh:
    DumpStatsEvent stuff gets move to sim_stats.(cc|hh)
sim/universe.cc:
    Provide some simple functions for converting times into
    ticks.  These use floating point math to get as close as
    possible to the real values.  Multipliers are set up ahead
    of time

--HG--
extra : convert_revision : d06ef26a9237529a1e5060cb1ac2dcc04d4ec252
2003-11-02 18:02:58 -05:00
Nathan Binkert
780b3b4bcd SimExit takes a time now
arch/alpha/isa_desc:
    regen

--HG--
extra : convert_revision : a9da9d2a5fc8a0414491e437747cde48dfb61a20
2003-11-02 13:01:08 -05:00
Nathan Binkert
c7d6745b07 deprecate the m5exit instruction and rename it to m5exit_old
Implement a new m5exit instruction with an optional delay

arch/alpha/isa_desc:
    move m5exit to m5exit old.  The old version of the
    instruction is now deprecated

    Implement the new exit instruction with the optional delay
sim/sim_events.cc:
sim/sim_events.hh:
    Make SimExit take a cycle
sim/universe.cc:
    provide ticksPerMS, ticksPerUS, and ticksPerNS so we don't
    have to do math during the cycle

--HG--
extra : convert_revision : e2ed47a2e5cfcd57c82086c6fcb4a28bf801c214
2003-11-02 02:07:31 -05:00
Steve Reinhardt
5a1eb9049d Support for Serializable non-SimObject things like events.
Can now serialize & unserialize DmaRequestEvents and DmaTransferEvents.
Also support serialize/unserialize of pointers to SimObjects and
other Serializable objects.

arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/isa_traits.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple_cpu/simple_cpu.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
    unserialize() now takes a Checkpoint* instead of an IniFile*.
cpu/simple_cpu/simple_cpu.cc:
    unserialize() now takes a Checkpoint* instead of an IniFile*.
    Put ExecContext in its own section so its _status fields doesn't conflict.
sim/eventq.cc:
sim/eventq.hh:
    unserialize() now takes a Checkpoint* instead of an IniFile*.
    Events get serialized by the event queue only if they're marked
    as AutoSerialize... others are assumed to be serialized by something
    else (e.g. an owning SimObject) or to not matter.
sim/param.cc:
    Shift 'const' in case T is a ptr type.
sim/serialize.cc:
sim/serialize.hh:
    Define Checkpoint object to encapsulate everything you need to know
    about a checkpoint.  Use it to allow lookups of named Serializable
    objects (and SimObjects) during unserialization.
    unserialize() now takes a Checkpoint* instead of an IniFile*.

--HG--
extra : convert_revision : 8e6baab32405f8f548bb67a097b2f713296537a5
2003-10-29 21:45:39 -08:00
Steve Reinhardt
af5277a678 Serialization support for Alpha TLBs, PhysicalMemory, and SimpleCPU.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
    Serialize TLB contents.
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
    Complete serialization of SimpleCPU (including owned events).
sim/eventq.cc:
sim/eventq.hh:
    Basic serialization for events.
    Still need to handle dynamic events (not owned by a SimObject).
sim/serialize.cc:
sim/serialize.hh:
    Export serialization filename so PhysicalMemory can
    derive its filename from that.

--HG--
extra : convert_revision : 4db851c5880f73f576ca092d5e5ad4256048eb51
2003-10-29 13:35:07 -08:00
Steve Reinhardt
8da9fcdd75 Flesh out ExecContext serialize/unserialize (including RegFile).
Add support for serializing enums.

arch/alpha/isa_traits.hh:
    Add serialize/unserialize functions for RegFile
    (defined in new isa_traits.cc).
cpu/exec_context.cc:
    Flesh out serialize/unserialize.
sim/serialize.hh:
    Add {UN}SERIALIZE_ENUM().

--HG--
extra : convert_revision : 9e30c7e7b3b290dc8ea0888ba3636fc93ee89052
2003-10-29 08:50:25 -08:00
Steve Reinhardt
aa12cac9fd Rename SERIALIZE_MEMBER to SERIALIZE_SCALAR.
--HG--
extra : convert_revision : 848cfcf3323d224cdb2ff14df6f6996607a5c27f
2003-10-29 00:46:26 -08:00
Steve Reinhardt
1511370d09 More progress on checkpointing... we can now write out a checkpoint and read it back in,
though most objects don't actually serialize any data.

arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/isa_traits.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple_cpu/simple_cpu.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
    Change unserialize param from IniFile& to const IniFile*.
cpu/simple_cpu/simple_cpu.cc:
    Change unserialize param from IniFile& to const IniFile*.
    Make unserialize call ExecContext::unserialize.
sim/eventq.cc:
    Rename MainEventQueue (no spaces) for easier parsing in checkpoints.
    Disable event serialization for now, so we can focus on the easy stuff.
sim/serialize.cc:
    Change paramIn and arrayParamIn param from IniFile& to const IniFile*.
sim/serialize.hh:
    Change unserialize, paramIn, and arrayParamIn params from IniFile& to const IniFile*.

--HG--
extra : convert_revision : 6e8853ed375eddec0e140c95a01dd51bd225f7b9
2003-10-29 00:41:24 -08:00
Steve Reinhardt
e12e64a071 Merge zizzer:bk/m5 into isabel.reinhardt.house:/z/stever/ser/m5
--HG--
extra : convert_revision : 50aa3791d27a17c4ea2fb4aee1a67011bd2abec1
2003-10-28 12:56:17 -08:00
Steve Reinhardt
b90f810575 Revamp serialization to make it easier.
--HG--
extra : convert_revision : c57a538d7cf606dbdf5fa244f92da46bd830e335
2003-10-28 12:55:12 -08:00
Steve Reinhardt
1820520697 Clean up a few spots where we weren't handling of misspeculation correctly.
arch/alpha/ev5.cc:
    Don't call kernelStats.hwrei() or system->breakpoint() on misspeculated paths.
arch/alpha/isa_desc:
    Don't write reegs.intrflag, do Annotate::Callpal, or call xc->syscall
    on misspeculated paths.

--HG--
extra : convert_revision : e73b96fbe4ac5be85fb20aa218fd05fd56d5b2f3
2003-10-28 09:09:45 -08:00
Nathan Binkert
cec7f73abf emulate callpal halt for non FULL_SYSTEM
in the process make m5_exit more generic

arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
    There's no reason that this needs to be in an arch specific file
arch/alpha/isa_desc:
    m5_exit -> SimExit
    Emulate callpal halt and cause the simulator to exit
    while we're at it, sort #includes
sim/sim_events.cc:
sim/sim_events.hh:
    move the m5_exit function here, renaming it to SimExit.
    Also Allow the caller to pass in the termination message.

--HG--
extra : convert_revision : 54b43b17a412ab387b8672c27ef0b04fce10ee15
2003-10-28 10:05:58 -05:00
Steve Reinhardt
ced22d81a6 Fix some problems with stats reset & floss counters.
arch/alpha/isa_desc:
    Keep m5 pseudo-instructions (like resetstats) from taking effect
    on misspeculated paths.

--HG--
extra : convert_revision : 7f0b0490164bca377ff2b14abc35a6c26bac9e6d
2003-10-26 22:37:14 -08:00
Steve Reinhardt
9508bf0a87 Merge stever@zizzer:/bk/m5 into isabel.reinhardt.house:/z/stever/bk/m5
--HG--
extra : convert_revision : 921d26b6fe29870fa532394b388bc0fe6cac183e
2003-10-24 23:37:28 -07:00
Steve Reinhardt
02d80c96b7 Move some common full-system CPU initialization from the
SimpleCPU & FullCPU constructors to AlphaISA::initCPU().

cpu/simple_cpu/simple_cpu.cc:
    Move some common full-system CPU initialization from the
    SimpleCPU & FullCPU constructors to AlphaISA::initCPU().
    Make 'fault' local to SimpleCPU::tick.
cpu/simple_cpu/simple_cpu.hh:
    Make 'fault' local to SimpleCPU::tick (not an object member).

--HG--
extra : convert_revision : e878dedfff06aac0548aca8b14d66c18b8916895
2003-10-24 23:20:27 -07:00
Andrew Schultz
47399b6c5e Added m5func "resetstats" to allow scriptable reset of statistics inside sim
--HG--
extra : convert_revision : 35a93fe085c2ca7ca1fc8bf887539e0b9c704aaf
2003-10-24 16:28:04 -04:00
Steve Reinhardt
cc9a838f4c Merge stever@zizzer:/bk/m5 into isabel.reinhardt.house:/z/stever/bk/m5
--HG--
extra : convert_revision : b0f93bd35d767fd3a520a9fed70a71d40b0056db
2003-10-23 19:09:18 -07:00
Steve Reinhardt
f5da73b688 Initial support for CPU switching. New SamplingCPU object encompasses a set
of CPUs that get switched round-robin (though currently we're only shooting for
two CPUs and one switch event, and even that doesn't quite work yet).  Registration
of ExecContexts with System/Process object factored out so we can create two CPUs
but only register one of them at a time.  Also worked at making behavior and naming
in System and Process objects more consistent.

arch/alpha/ev5.cc:
    Rename ipr_init to initIPRs and get rid of unused mem arg.
arch/alpha/fake_syscall.cc:
    Process:numCpus is now a function (not a data member).
base/remote_gdb.hh:
    Support for ExecContext switching.
cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple_cpu/simple_cpu.hh:
    Support for ExecContext switching.
    Renamed contexts array to execContexts to be consistent with Process.
    CPU ID now auto-assigned by system object.
cpu/simple_cpu/simple_cpu.cc:
    Support for ExecContext switching.
    Renamed contexts array to execContexts to be consistent with Process.
    CPU ID now auto-assigned by system object.
    Cleaned up MP full-system initialization a bit.
dev/alpha_console.cc:
    Renamed xcvec array to execContexts to be consistent with Process.
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
    Support for ExecContext switching.
    CPU ID now auto-assigned by system object.
sim/prog.cc:
sim/prog.hh:
    Support for ExecContext switching.
    Process:numCpus is now a function (not a data member).
sim/system.cc:
sim/system.hh:
    Support for ExecContext switching.
    Renamed xcvec array to execContexts to be consistent with Process.

--HG--
extra : convert_revision : 79649cffad5bf3e83de8df44236941907926d791
2003-10-23 19:07:52 -07:00
Erik Hallnor
320540829d Move to non-architecture specific MemReq
arch/alpha/alpha_memory.hh:
cpu/exec_context.hh:
cpu/pc_event.hh:
    Move to non architecture specific MemReq

--HG--
extra : convert_revision : 2445943b6f1c8af86b90cfa9c2f9b1eb4a6a1aa2
2003-10-23 16:40:08 -04:00
Andrew Schultz
f600cff5c2 Created new M5 instruction to allow an integer parameter (init_param) to be specified in the INI and then read inside the simulator.
arch/alpha/isa_desc:
    Added new M5FUNC instruction to put allow reading of init_param inside simulator
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/system.cc:
sim/system.hh:
    Added support for init_param

--HG--
extra : convert_revision : 8253f0b4239b194d4f04665c9deec1fcdf665c8a
2003-10-21 17:18:17 -04:00
Nathan Binkert
e0b065ff7c Separate the stuff for SimObject from SimObject builder.
This makes testing a bit easier.

arch/alpha/alpha_memory.cc:
cpu/intr_control.cc:
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
dev/alpha_console.cc:
dev/console.cc:
dev/disk_image.cc:
dev/etherbus.cc:
dev/etherdump.cc:
dev/etherlink.cc:
dev/ethertap.cc:
dev/simple_disk.cc:
kern/tru64/tru64_system.cc:
sim/main.cc:
sim/prog.cc:
    Need to include builder.hh
    sort #includes
sim/sim_object.cc:
sim/sim_object.hh:
    Separate the SimObjectBuilder stuff into its own file

--HG--
extra : convert_revision : e8395e0cc6ae1f180f9cd6f100795a1ac44aeed5
2003-10-20 20:17:01 -04:00
Steve Reinhardt
f951b00d89 Get rid of obsolete code, most of it '#if 0'ed anyway.
Mostly vestiges of Dave's long-gone instruction prefetching stuff.

arch/alpha/isa_traits.hh:
    Delete unused extractInstructionPrefetchTarget().
base/inifile.cc:
    Delete '#if 0' code
cpu/base_cpu.hh:
    Delete unused filterThisInstructionPrefetch() function.
cpu/exetrace.hh:
    Delete '#if 0' code (obsolete flags).

--HG--
extra : convert_revision : c8317f56ba0a0e568daa785825ee938584987bed
2003-10-19 17:30:26 -07:00
Steve Reinhardt
83d32482dc Add comment to elaborate on store-conditional result code (and remove
stale reference to machine.def).

arch/alpha/isa_desc:
    Add comment describing store-conditional result code
cpu/exec_context.hh:
    update comments

--HG--
extra : convert_revision : ac59e0ad7a9440cb6656617fdf05495b59c68f55
2003-10-18 21:21:14 -07:00
Steve Reinhardt
8b4f16a727 Minor documentation tweaks.
arch/alpha/aout_machdep.h:
    Comment aout_exechdr fields to make doxygen happy.

--HG--
extra : convert_revision : 23fe88cb7ee511ccd83d2779024daf015133c9ce
2003-10-16 12:41:35 -07:00
Nathan Binkert
638a07d15a Merge
cpu/pc_event.cc:
    SCCS merged

--HG--
extra : convert_revision : f7046f2bf6053be9b00150390fabe3d4f82b0981
2003-10-14 16:53:52 -04:00
Nathan Binkert
4759c203c7 Remove all of the Tru64 specific stuff from the base System object
into its own Tru64System object.  Also remove the System builder
stuff and create a Tru64System builder.  This makes it much
simpler to support more operating systems.

arch/alpha/ev5.cc:
    Each system provides its own mechanism for doing a breakpoint.
base/remote_gdb.hh:
    #include <map>
cpu/pc_event.cc:
cpu/pc_event.hh:
    Separate out System specific PCEvents
cpu/simple_cpu/simple_cpu.cc:
    each system provides its own init script
kern/tru64/dump_mbuf.cc:
kern/tru64/printf.cc:
    Stick this in a namespace

--HG--
extra : convert_revision : 9f74527ed2ff8010431d9aff34357aaecc1fb3f6
2003-10-14 12:19:59 -04:00
Steve Reinhardt
af5cdc1d8c Rename CPU object to FullCPU
arch/alpha/isa_desc:
arch/alpha/isa_traits.hh:
cpu/static_inst.hh:
    CPU -> FullCPU

--HG--
extra : convert_revision : 2bed1ed9372ca9e33f7e391a1aa47bbc02675691
2003-10-13 22:21:19 -07:00
Steve Reinhardt
75e5460579 Rename full_cpu/cpu.cc,hh to full_cpu.cc,hh.
arch/alpha/isa_desc:
    Fix include: cpu.hh renamed to full_cpu.hh
cpu/pc_event.cc:
    Didn't need cpu.hh, just base_cpu.hh.
sim/sim_events.cc:
    Didn't need cpu.hh, just param.hh.

--HG--
extra : convert_revision : 2e3fd36476c639af950ba2113f67e8ea24c22be8
2003-10-13 21:51:34 -07:00
Nathan Binkert
f94ff9ace5 Split up kernel.cc into separate files for dump_mbuf and printf
cpu/exec_context.hh:
dev/alpha_console.cc:
sim/system.cc:
sim/system.hh:
    Convert from fixed array to a vector
arch/alpha/arguments.hh:
    now that CopyData and CopyString are in vtophys.hh, this
    include is not necessary
arch/alpha/vtophys.hh:
    Include isa_traits.hh for Addr
cpu/pc_event.cc:
    Temporarily get this working while we're changing things

--HG--
extra : convert_revision : 9a7597b7bd5d050819766f8edf7a02f28447b9ca
2003-10-13 17:24:27 -04:00
Nathan Binkert
2471c214bf cleanup
arch/alpha/arguments.hh:
arch/alpha/arguments.cc:
    sort #includes

--HG--
extra : convert_revision : f152f2fa1479649e7376e2a24107da642c7da5aa
2003-10-13 16:14:28 -04:00
Nathan Binkert
60a7bd950b CopyData and CopyString moved from kernel.cc to vtophys.cc
kernel.cc and kernel.hh moved to kern/tru64

--HG--
extra : convert_revision : 1b9123af03960b602a2d52dfa7b714280f9995aa
2003-10-13 16:09:33 -04:00
Nathan Binkert
b177f696ff Try to get the correct license on various files
remove stuff that is ambiguous
Clean up code a bit

arch/alpha/aout_machdep.h:
    Add M5 License
docs/stl.hh:
    M5 license
base/remote_gdb.cc:
    Most of this is mine, so stick in the m5 license
dev/console.hh:
    Clean up comments
    merge simple() and out() into one function.
dev/console.hh:
dev/console.cc:
    m5 license
dev/console.cc:
    merge simple and out.
    remove dead code
dev/console.cc:
    Remove comments that weren't mine.
    Clean up code
dev/console.hh:
    update names
dev/alpha_console.cc:
    use new interface

--HG--
extra : convert_revision : 3cd2357e1525db43c2ef9e89a9b47a47861d6af9
2003-10-13 02:00:47 -04:00
Steve Reinhardt
25693e9e69 Make include paths explicit and update makefile accordingly.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/fake_syscall.cc:
arch/alpha/faults.cc:
arch/alpha/isa_desc:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/circlebuf.cc:
base/compression/lzss_compression.cc:
base/compression/lzss_compression.hh:
base/cprintf.cc:
base/cprintf.hh:
base/fast_alloc.cc:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/hashmap.hh:
base/hostinfo.cc:
base/hostinfo.hh:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/inet.cc:
base/inet.hh:
base/inifile.cc:
base/inifile.hh:
base/intmath.cc:
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/exec_aout.h:
base/loader/exec_ecoff.h:
base/loader/object_file.cc:
base/loader/object_file.hh:
base/loader/symtab.cc:
base/loader/symtab.hh:
base/misc.cc:
base/misc.hh:
base/pollevent.cc:
base/pollevent.hh:
base/random.cc:
base/random.hh:
base/range.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/res_list.hh:
base/sat_counter.cc:
base/sat_counter.hh:
base/sched_list.hh:
base/socket.cc:
base/statistics.cc:
base/statistics.hh:
base/str.cc:
base/trace.cc:
base/trace.hh:
cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/exetrace.cc:
cpu/exetrace.hh:
cpu/intr_control.cc:
cpu/intr_control.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
cpu/pc_event.cc:
cpu/pc_event.hh:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/static_inst.cc:
cpu/static_inst.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
sim/debug.cc:
sim/eventq.cc:
sim/eventq.hh:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/prog.cc:
sim/prog.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/sim_time.cc:
sim/system.cc:
sim/system.hh:
sim/universe.cc:
test/circletest.cc:
test/cprintftest.cc:
test/initest.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
test/tracetest.cc:
util/tap/tap.cc:
    Make include paths explicit.

--HG--
extra : convert_revision : 941cbdc591fd4d3d1d9f095cd58fc23dd2d73840
2003-10-10 11:09:00 -07:00
Steve Raasch
a5366f9683 testing behavior of decoder.cc file
arch/alpha/alpha_memory.cc:
    append a blank line

--HG--
extra : convert_revision : 482388741a3000b0c745733c9882300ff9ecf529
2003-10-08 23:09:50 -04:00
Steve Reinhardt
e475dba424 New loader structure. Expand Nate's ObjectFile to automatically detect file formats
and generate an appropriate child object, which knows how to load its text & data into memory
(and symbols, for ecoff only at this point).  Ecoff format supports Tru64 binaries, kernel, and
console.  A.out format is used by PAL code.  Elf support is there and appears to work for
Alpha/Linux binaries, but awaits a Linux syscall emulation layer before further testing.

arch/alpha/ecoff_machdep.h:
base/coff_sym.h:
base/coff_symconst.h:
base/exec_ecoff.h:
    Add Id string & provenance comment, clean up types
base/object_file.cc:
base/object_file.hh:
    Add auto format detection and text/data loading.
sim/prog.cc:
    Moved binary loading & stack setup here (was in arch/alpha/loader.cc).  Some of this is
    platform-dependent, but I think most of it is not.  We'll factor out the platform-dependent
    parts when the need arises.
sim/prog.hh:
    Get rid of unused environ_base field.
sim/system.cc:
    Use new ObjectFile loader structure for console, kernel, & palcode.

--HG--
extra : convert_revision : 8eae509bf71cf204bc3ec78c68699cfd01baed97
2003-10-07 23:13:01 -07:00
Steve Raasch
92638f9a65 Import changeset
Doxyfile:
LICENSE:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/fake_syscall.cc:
arch/alpha/faults.cc:
arch/alpha/faults.hh:
arch/alpha/isa_desc:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/osfpal.hh:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
arch/isa_parser.py:
base/bitfield.hh:
base/callback.hh:
base/circlebuf.cc:
base/circlebuf.hh:
base/cprintf.cc:
base/cprintf.hh:
base/cprintf_formats.hh:
base/date.cc:
base/dbl_list.hh:
base/endian.hh:
base/fast_alloc.cc:
base/fast_alloc.hh:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/hashmap.hh:
base/inet.cc:
base/inet.hh:
base/inifile.cc:
base/inifile.hh:
base/intmath.cc:
base/intmath.h:
base/kgdb.h:
base/misc.cc:
base/misc.hh:
base/mod_num.hh:
base/object_file.cc:
base/object_file.hh:
base/pollevent.cc:
base/pollevent.hh:
base/random.cc:
base/random.hh:
base/range.hh:
base/refcnt.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/res_list.hh:
base/sched_list.hh:
base/socket.cc:
base/socket.hh:
base/statistics.cc:
base/statistics.hh:
base/str.cc:
base/str.hh:
base/symtab.cc:
base/symtab.hh:
base/trace.cc:
base/trace.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/pcireg.h:
dev/simple_disk.cc:
dev/simple_disk.hh:
kern/tru64/tru64.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
sim/async.hh:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/cache/lzss_compression.cc:
sim/cache/lzss_compression.hh:
sim/cache/null_compression.hh:
sim/debug.cc:
sim/debug.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/host.hh:
sim/hybrid_pred.cc:
sim/hybrid_pred.hh:
sim/intr_control.cc:
sim/intr_control.hh:
sim/main.cc:
sim/memtest.cc:
sim/memtest.hh:
sim/op_class.hh:
sim/param.cc:
sim/param.hh:
sim/pc_event.cc:
sim/pc_event.hh:
sim/predictor.hh:
sim/prog.cc:
sim/prog.hh:
sim/sat_counter.cc:
sim/sat_counter.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/sim_time.cc:
sim/sim_time.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/smt.hh:
sim/static_inst.cc:
sim/static_inst.hh:
sim/std_types.hh:
sim/system.cc:
sim/system.hh:
sim/universe.cc:
test/Makefile:
test/bitvectest.cc:
test/circletest.cc:
test/cprintftest.cc:
test/foo.ini:
test/initest.cc:
test/initest.ini:
test/lru_test.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/sized_test.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
test/tracetest.cc:
util/rundiff:
util/tap/Makefile:
util/tap/tap.cc:
util/term/Makefile:
util/term/term.c:
    RCS to BitKeeper
sim/main.cc:
    Initial revision
sim/main.cc:
    Added base SMT support to SS3 distribution
sim/main.cc:
    Corrected statistics in sim-smt
    Added "cnt_*" statistics to sim-smt and sim-outorder
    Added execution tracing to sim-outorder
sim/main.cc:
    Numerous minor fixes.
    Implemented Ideal and Random fetch policies.
    Numerous new statistics.
sim/main.cc:
    A few minor bug fixes to collapsing RUU & "ideal" fetch policy.
sim/main.cc:
    Snapshot of MICRO99 work in progress.  Lots of SMT stuff, EIO fixes, etc.
sim/main.cc:

    -> New fetch stage:
    - Fetch a block at a time
    - Execute in fetch
    -> Removed execute from ruu_dispatch()
    -> Cleaned up
sim/main.cc:
    Added build time-stamp to top of simulation log
sim/main.cc:
    Corrected error in priority rotation routine
    Added -max:mult option
    Modified makefile to use egcs compiler
    Added the -t option bkdwn.pl
sim/main.cc:
    Added memory usage display
    Fixed #define for number of RS_LINKs
sim/main.cc:
    Should be able to build other simulators (sim-fast, sim-eio, etc.) using
    "make -f Makefile.orig" (for Alpha at least, not quite for PISA).
sim/main.cc:
    More SMT vs. non-SMT cleanup: 'make sim-X' now works for most X.
sim/main.cc:
    Changed function of Fetch/Decode/Dispatch pipe:
    a) Fetch only if room in fetch queue
    b) Decode only if pipe advanced as a result of dispatching a packet
    c) Dispatch a packet only if:
    1) Room for all insns in RUU
    2) Room for all insns in LSQ
    3) Room for all insns in INT Register File
    4) Room for all insns in FP Register File
    Added ROB structure
    a) Instruction is placed in RUU & ROB at dispatch
    b) Instruction is removed from RUU at writeback (except stores)
    c) Instruction is removed from ROB at commit
    Added support for counting physical register usage (INT and FP)
    a) subtract from "free" count at dispatch
    b) add back when instruction is removed from ROB
    Added "my_index" field to RUU_station (simplifies reverse-lookups)
    Removed all remaining ptrace stuff
    RUU & LSQ now dump squashed instructions instead of marking them squashed
    - No cost!
    Reworked commit stage to use ROB instea
sim/main.cc:
    - Added sc_dist1 stat type as a user-transparent special case of distribution
    with unit-size buckets: saves an unnecessary divide on every sample
    - Minor changes to compile as C++ code
base/fast_alloc.cc:
base/fast_alloc.hh:
    Major reorganization.  Split sim-smt.c into multiple files, compile with C++,
    split ROB & RUU structures, numerous small formatting and performance changes.
sim/eventq.cc:
sim/eventq.hh:
    - Replaced SimpleScalar event queue code with smt_eventq.{cc,hh}
    - Eliminated unused cache:flush option
    - Initialize bpred history regs and BTB and RAS entries to provide
    repeatable results
    - Added reset_spec_state() function: cleans up interface to spec_state.c
sim/eventq.cc:
sim/eventq.hh:
    Major reorganization of memory-system code and interface.
base/fast_alloc.cc:
sim/eventq.cc:
sim/eventq.hh:
    Moved C++ files to .cc/.hh, compile C files with C compiler.
base/dbl_list.hh:
    Initial check-in: doubly-linked list template class.
sim/eventq.hh:
    Added when_created and when_scheduled time-tags for debugging
base/fast_alloc.hh:
    Plug memory leak
sim/eventq.cc:
    Runahead_Prefetch memory-system support, including miss notification
    events in cache.
sim/eventq.cc:
sim/eventq.hh:
    Merged branch "mt-frontend" into trunk of CVS tree
    Changes include:
    Multi-threaded Fetch & Decode
    Correct functionality of branch misprediction fixup (MT only)
    Improved stats
base/intmath.cc:
base/intmath.h:
    Integer math functions.
base/fast_alloc.cc:
base/fast_alloc.hh:
    Remove carriage returns.
base/intmath.h:
    Add Min/Max template functions
sim/prog.cc:
sim/prog.hh:
    Adding smt-safe and smt-fast.  These are functional simulators based on
    sim-safe and sim-fast.  Despite their names, they do not actually don't
    handle multithreaded programs yet.  The runfile functionality was
    pulled out of sim-smt.cc into its own files.  This allows all three
    simulators to use runfiles.

    NOTE:  There is a lot of duplicated code in these three simulators that
    should probably be separated out.  The macro type definitions in engin.hh
    are similar to the definitions in smt-safe.cc and smt-fast.cc
sim/prog.cc:
    Add support for loading a kernel with simplescalar.  Also add skeleton for
    loading a disk image to boot from with simplescalar.

    Hook for loading palcode is in place, but not implemented.
    Initial parameters passed to kernel at boot time are not passed properly.
sim/prog.cc:
    Only support loading kernel/disk image if we're running FULL_SYSTEM
sim/prog.cc:
    Make loading PAL a separate operation.  Also separate kernel loading and
    disk loading so that it can only be done in FULL_SYSTEM.  Finally, we need
    to also load the console image file.  I'm not sure what's in there, maybe
    some stuff from SRM, but it's needed for proper execution.
dev/alpha_console.cc:
dev/alpha_console.hh:
    Console device implementation from simos.  This is a simple device that
    supports the necessary console functions for booting.
sim/prog.cc:
sim/prog.hh:
    Separate the kernel loader and the program loader for simplicity since they
    don't share much code.
arch/alpha/alpha_memory.hh:
    Add this somewhat gross hack to take care of the fact that alpha has the
    this load locking and conditional store mechanism.
sim/prog.cc:
    Enable asids again.  This makes multithreaded programs work again.
    I guess you could say that this was an accidental commit.  Sorry
sim/main.cc:
    Clean up Simplescalar copyright notice.
sim/prog.cc:
    Allow '-' for stdout as well as stdin in run file.
dev/alpha_console.cc:
dev/alpha_console.hh:
sim/prog.cc:
arch/alpha/alpha_memory.hh:
    Replace the interface to the memory system.  Basically this change goes
    away from the model of passing an address, and a number of bytes and
    getting/setting data.  This change rather creates a memory_request packet
    (a simple struct) that bundles all of the necessary information together
    to pass into the memory system when making a request.  This makes the
    function call syntax consistent even when you have virtual to physical
    translation and when you have strange flags like locked, or physical that
    you need to pass to your memory system.  It has the added benefit of allowing
    the layers to pass data to each other, possibly skipping layers in between.
    This was necessary for the whacked out behavior that store conditional has
    on alpha.
    In addition, the entire memory system is now consistent in that it will return
    an alignment fault due to an unaligned access.  This is necessary to properly
    model a full alpha system, but changes the behavior of bogus bad path loads
    and stores that access unaligned data.  Because
base/fast_alloc.cc:
base/fast_alloc.hh:
    Major enhancement of FastAlloc debug code (uncomment #define in
    fast_alloc.hh to enable).  Can now dump summary of in-use objects
    by type and address/type of oldest n objects (thank you RTTI!).
    Should be easier to identify memory leaks now.
base/res_list.hh:
    file res_list.hh was initially added on branch segmented_iq.
sim/sat_counter.hh:
    file sat_counter.hh was initially added on branch segmented_iq.
sim/std_types.hh:
    file std_types.hh was initially added on branch segmented_iq.
base/fast_alloc.hh:
base/res_list.hh:
sim/sat_counter.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/prog.cc:
sim/std_types.hh:
    Merged branch "segmented_iq"
    -> Objectized the IQ and LSQ
    -> Implemented Standard, Sezned, and Segmented IQ's
    -> Major fixes to wrong-path execution (primarily involving data dependencies)
base/res_list.hh:
    g++ is braindead, so I cannot pull template functions out into a .cc file.
    Instead, pull large functions out of the class definition and inline them.
    This leads to a much more readable class definition.

    In addition, since these functions are inlined, youseems to be what is
    intended anyway.
sim/prog.cc:
    Move some variables to smt_prog so that targets other than sim-smt can use
    them.
sim/main.cc:
    remove the dlite debugger (for smt at least)
dev/alpha_console.cc:
sim/eventq.cc:
sim/main.cc:
    I knew I had done this for a reason
    Change 64 bit types back to long for alpha and replace all instances
    of stuff like %lld to use FMT64d and the like.

    The reason this is necessary is because TRU64 does not understand what
    %lld is and will print out "ld" instead of actually printing the
    number.

    So, PLEASE use the FMTxxx stuff instead of sticking %lld, %llx, %016llx
    and such into the code.
sim/main.cc:
    Don't want FMT64d for things declared 'long': this doesn't work when
    FMT64d evaluates to "%lld".  Just use "%ld" instead.
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/pcireg.h:
dev/simple_disk.cc:
dev/simple_disk.hh:
    Add several initial devices for full alpha system simulation.
    Many of these devices are based on SimOS devices
dev/alpha_console.cc:
dev/alpha_console.hh:
    Update the alpha_console to take advantage of the simple disk interface
sim/eventq.cc:
sim/eventq.hh:
    Make it so you can service events that will happen in the future
base/trace.cc:
base/trace.hh:
    This is a simple tracing facility.
    The idea is that there is a bitvector where each bit represents something
    that you may want to trace.  The end result is that you can at runtime
    turn on and off different tracing statements in the code so that you
    only see messages for things that you care about.

    This is only currently used in the devices framework, but I would like
    to see it eventually replace the debug, warn, and info functions.
sim/intr_control.hh:
    Initial abstraction for a processor and interrupt controller
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
    Add full support for the SYSTEM_EV5 model in smt-safe.  With this model, the
    user should be able to boot Tru64 unix.

    Several aspects of the memory subsystem were changed to accomidate this
    ability:
    - The C memory access functions no longer return an md_fault_type.
    - The prot_* functions no longer take a memrequest, and no longer return
    an md_fault type.  They now take a single address and a size.  This is
    because the prot_* functions don't need translation abilities, etc.
    - The prot_* functions will by default fail to work unless they are
    specifically implemented for the class that you want to use them with.
    - The unaligned parameter to the READ_* and WRITE_* function calls was added
    back so that exceptions that occur on STQ_U, LDQ_U, etc get the proper
    faulting address.
    - The memory controller now supports adding an arbitrary number of objects
    at arbitrary memory ranges so that a variety of devices can be accomidated.
    - The physical_memory class now not only emulates a specific amount of memor
base/trace.cc:
    Check for existence of environment variable
dev/console.cc:
    Temporary fix to get this to compile under Linux.
sim/main.cc:
    Flush stdout before dumping stats.
sim/exec_context.cc:
sim/exec_context.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/main.cc:
sim/prog.cc:
sim/prog.hh:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/fake_syscall.cc:
    Pull per-cpu variables into cpu_t object as first step toward multiprocessor
    support.  Also encapsulated execution context into a single object.
    Program loading code also significantly reorganized.
    Syscall redirection to host machine temporarily broken (must use EIO
    files for now).
arch/alpha/fake_syscall.cc:
sim/eventq.cc:
sim/exec_context.cc:
sim/exetrace.cc:
sim/main.cc:
sim/prog.cc:
    Update source tree to deal with shuffling of files and renaming of files.
    Maybe a tiny bit of style here and there for kicks too.
sim/prog.cc:
    Fix more stuff for reorg.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/fake_syscall.cc:
base/dbl_list.hh:
base/fast_alloc.cc:
base/fast_alloc.hh:
base/intmath.cc:
base/intmath.h:
base/res_list.hh:
base/trace.cc:
base/trace.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/pcireg.h:
dev/simple_disk.cc:
dev/simple_disk.hh:
sim/main.cc:
sim/eventq.cc:
sim/eventq.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/intr_control.hh:
sim/prog.cc:
sim/prog.hh:
sim/sat_counter.hh:
sim/std_types.hh:
    Some style changes
    remove all of the $Log$ crap
    add $Id$ strings to the top of all files.
arch/alpha/alpha_memory.cc:
    Convert memory request objects to have a bitvector of flags.
sim/sat_counter.hh:
    Minor bug-fixes to statistics & options
    Saturating counter wasn't initializing properly
arch/alpha/fake_syscall.cc:
    Compile on OpenBSD
base/fast_alloc.cc:
dev/console.cc:
dev/disk_image.cc:
sim/eventq.cc:
sim/eventq.hh:
sim/exec_context.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/intr_control.hh:
sim/prog.cc:
sim/sat_counter.hh:
    Move extern "C" statements out of C++ files and into the C headers with
    #ifdef __cplusplus guarding the extern.
base/str.cc:
base/str.hh:
    My lame old reference counting string class.  It's really not too bad.
base/intmath.cc:
    removed unused variable
sim/main.cc:
    add option -inifile to load the config file
base/inifile.cc:
base/inifile.hh:
sim/main.cc:
    rename configfile to inifile
base/intmath.h:
    Functions to determine if a character is hex, dec, oct.
    Convert hex to int
base/str.cc:
base/str.hh:
    Add a tokenize function.
    Fix a bug in the CopyRight function
    Add a const iterator
    Add a string to number function that will deal with hex, decimal, octal,
    positive numbers and a few suffixes.  Complete with bounds checking and
    syntax checking
base/inifile.cc:
base/inifile.hh:
    Cope with fix in CopyRight function from the String class.
    Add a find default which whill check for a Default= parameter.
    Add #include guards
dev/alpha_console.cc:
    style. change assertion
sim/sat_counter.hh:
    Added instruction-type identification methods to dyn_inst
    Continued work on the segmented IQ:
    - Stats
    - Seg0 load mechanisms
    - "short" dump function
    - free_slots_last_cycle model improvement
    Added stats to sat_counter
sim/main.cc:
    Parse .ini file for options in main.cc.
sim/main.cc:
    Reindent following style guide.
sim/sat_counter.hh:
    Updates to the segmented IQ
sim/hybrid_pred.hh:
    Initial check-in
sim/predictor.hh:
    Initial check-in of predictor
    Mods to predictor stats
sim/hybrid_pred.hh:
sim/predictor.hh:
sim/sat_counter.hh:
    Class heirarchy fixes
sim/predictor.hh:
sim/sat_counter.hh:
    Now the predictors actually work!
sim/sat_counter.hh:
    Final fixes to the SaturatingCounterPred
    Corrections to the LRP and HMP
sim/sat_counter.hh:
    Bug fixes and predictor mods to segmented IQ during ISCA-2002 work
    Dumping of queue contents is a little more flexible for debugging
arch/alpha/fake_syscall.cc:
sim/prog.cc:
    Updated fake syscall support (for most common syscalls) so we can
    once again run straight binaries (not just EIO files).
sim/sat_counter.hh:
    Final updates (for now) to the Segmented IQ
    Cleaning up the fetch stage
    Speed improvements to the Saturating Counter Predictor Object
sim/prog.cc:
sim/prog.hh:
    Fix parameter bug in process_t::dup_fd (causing stdio fd's not to get
    remapped correctly).
base/str.hh:
    Add forward decl of class ostream
base/inifile.cc:
base/inifile.hh:
    Rename members to conform to common style.
base/inifile.cc:
    Oops... looks like CPP_PIPE doesn't work.
sim/main.cc:
sim/sat_counter.hh:
sim/sim_object.cc:
sim/sim_object.hh:
    New configuration scheme based on .ini files and hierarchical descriptions.
    Currently in a transitional state: only sim_smt CPU, IQ, Cache, Bus, and
    Mem objects are configured this way.  Old mmodel.{hh,cc} completely gone.
base/inifile.cc:
    Fix pipe directionality for Linux: CPP_PIPE works again.
sim/sim_object.cc:
    Updates for INI-file parameters for Seznec and Segmented IQ models
    Fixed naming of IQ classes
sim/sim_object.cc:
sim/sim_object.hh:
    - Minor revisions to ParamContext, SimObjectBuilder, etc. to allow creation
    of SimObjects outside of configuration hierarchy.
    - Encapsulated magic boilerplate for object creation in macros to simplify
    usage and make future changes like this simpler.
arch/alpha/fake_syscall.cc:
sim/exec_context.cc:
sim/exec_context.hh:
sim/prog.cc:
sim/prog.hh:
    Rename process_t --> Process, eio_process_t -> EioProcess,
    live_process_t -> LiveProcess
base/str.cc:
base/str.hh:
    flesh out string class
base/str.cc:
    This time commit the right file.
base/str.cc:
    fix Tokenize for the case where the last string is only a single character
sim/sim_object.cc:
    Instantiate Param<String>::showValue().
sim/sim_object.cc:
sim/sim_object.hh:
    - Auto-register global parameter contexts for non-SimObject parameters
    - added ParamContext::parseAllContexts()
    - Finish and test enum params (SimpleEnumParam, MappedEnumParam)
    - Add vector-valued parameters: VectorParam<T>, SimObjectVectorParam,
    SimpleEnumVectorParam, MappedEnumVectorParam
    - Factor parsing & displaying functions to share code between scalar
    and vector parameter objects
    - Fix bug where a SimObjectClass constructor could be called before
    the static SimObjectClass::classMap constructor
    - Add "help" functions to dump parameter descriptions
    (ParamContext::describeAllContexts() and
    SimObjectClass::describeAllClasses())
sim/main.cc:
    Dump out config file parameters on '-h' cmd-line argument.
sim/sim_object.cc:
sim/sim_object.hh:
    - Add showType() method to display parameter type as string for help
    - Change EnumParam types to include specific enum type (avoids casting)
sim/sim_object.hh:
    Minor updates for statistics, new compilers, etc.
    Moved some options into new options model
base/inifile.cc:
base/inifile.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/prog.cc:
sim/prog.hh:
sim/sim_object.cc:
sim/sim_object.hh:
    Eliminated old SimpleScalar options package from sim_smt, shifting
    everything over to new parameter objects fed by .ini-style
    configuration files.  Parameters can be set on command line using
    '--<sec>:<param>=<value>'.  All other cmd-line options are assumed
    to be config file names, except '-h' prints help msg.

    Got rid of *_reg_options(), *_check_options(), *_uninit() calls.
    Moved more initialization into constructors; remaining code is now
    automagically executed by providing checkParams() and cleanup()
    methods on ParamContext-derived objects.  (See exetrace.cc, for
    example.)

    Runfile is gone; processes are initialized as simulation objects.

    Split parameter code out of sim_object.{cc,hh} into param.{cc,hh}.

    Moved a bunch of CPU object methods from sim_smt.cc to cpu.cc.

    smt_reg_stats calls now need to know number of threads.  Can be done
    by explicit argument to global function, or (for backward
    compatibility) calling CPU object method with same parameters as old
    global function.

    Renamed "SimControl" par
base/circlebuf.cc:
base/circlebuf.hh:
    Add a circular buffer class that holds string data.
    You can set the size of the buffer, and basically keep writing to it,
    and later read the last size bytes from the buffer.  kinda like tail -f
test/Makefile:
test/bitvectest.cc:
test/circletest.cc:
test/foo.ini:
test/initest.cc:
test/initest.ini:
test/strnumtest.cc:
test/tokentest.cc:
    Add a little bit of test framework and a bunch of initial tests
test/paramtest.cc:
    Move the param test thing to the new test framework, though it doesn't
    compile right now since I couldn't figure it out
base/inifile.cc:
    Disable pipes for cpp: hangs if cpp output is bigger than kernel pipe buffer.
sim/sim_object.cc:
    Check for accidental redefinition of SimObject class names.
base/str.cc:
    Support exponents in StringToNumber.

    It should be noted, that while StringToNumber does bounds checking,
    the bounds checking has not been mathmatically proven, so it could
    have mistakes.
base/range.hh:
    Simple range class that will parse a range and provides comparison
    operators
base/trace.hh:
    New tracing options
test/Makefile:
test/rangetest.cc:
    add a new test for the Range class
sim/exetrace.cc:
sim/exetrace.hh:
sim/main.cc:
    Create an ExecutionTrace class that encapsulates the old exe_trace stuff.
    Convert the last of the old options stuff to the new params and get rid
    of the old options files.
    Get rid of the old range files.
arch/alpha/fake_syscall.cc:
    Stupid linuxisms
sim/main.cc:
sim/sim_object.cc:
    Output config info to cerr instead of cout.
sim/main.cc:
    Load default.ini if the file exists
test/Makefile:
test/bitvectest.cc:
test/circletest.cc:
test/initest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/strnumtest.cc:
test/tokentest.cc:
    Add Id tags
sim/sim_object.cc:
    Bug fix to allow use of "default=" in ini-files
sim/prog.cc:
    Fix for wacky compiler bug
base/inifile.cc:
    Modified some ROB statistic labels to make them more uniform
    Re-implimented rob-caps
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
    Add support for doing virtual to physical translation using the in-memory
    page table
base/kgdb.h:
base/remote_gdb.cc:
base/remote_gdb.hh:
    Basic support for remote debugging
base/pollevent.cc:
base/pollevent.hh:
    A class abstraction for poll
base/socket.cc:
base/socket.hh:
    Support for tcp server sockets
base/symtab.cc:
base/symtab.hh:
    simple symbol table loaded from a preprocessed file
dev/alpha_access.h:
dev/alpha_console.hh:
    split alpha access into a separate file so that building console code is
    simpler
dev/disk_image.cc:
dev/disk_image.hh:
    use a string for the disk image file name instead of a char *
arch/alpha/alpha_memory.cc:
    Make the MCSR segment check more explicit
    rearrange
base/trace.cc:
    Make trace stuff use new parameter stuff
base/trace.hh:
    Fix DPRINTF and DPRINTFN macros
    Add a few new trace flags
sim/exetrace.cc:
sim/exetrace.hh:
    Add more features to the exetrace stuff.
    Make use of the symbol table support.
base/remote_gdb.cc:
    fix DPRINTFs
dev/alpha_console.cc:
dev/console.cc:
dev/console.hh:
    Change the console framework to use the new pollevent stuff.
    This adds support for a console that can be attached and detached at runtime
    via a tcp connection (telnet).  There is also a circular buffer integrated
    into the console so that upon connection, any missed console text is output
    to the console.
    In the future, this should easily allow for multiple system consoles to
    be attached.
base/inifile.cc:
base/str.hh:
    Move the string hash function
base/symtab.cc:
base/symtab.hh:
sim/exetrace.cc:
    Add support to lookup symbols by name, and take advantage of that support
    for looking up symbols for panic and badaddr
base/str.cc:
base/str.hh:
    change to new formatting.
    naming convention still dosn't match new style
dev/console.cc:
dev/console.hh:
    Fix console code so that typed characters are properly handled.
    When clearing interrupts, be explicit with regards to which ones.
arch/alpha/vtophys.cc:
    a tad bit of error checking
sim/exetrace.cc:
sim/exetrace.hh:
    EXE-Trace extensions
    Disabled "good_mem" memory layer... this still needs to be properly removed
base/kgdb.h:
    Add more kgdb commands
base/trace.hh:
    Tracing for ISP
sim/exec_context.cc:
sim/exec_context.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/prog.cc:
sim/prog.hh:
    Update to BTB functionality
    Fixed numerous statistics
    Fixed path of store instructions so that they _all_ go through issue stage
    Updates to exetrace functionality
sim/eventq.cc:
sim/eventq.hh:
    Replaced every-cycle termination checks in sim_main() with events.

    Added per-thread instruction-count-based event queues to handle
    termination based on committed instruction count.  These are now
    specified via parameters to the FullCPU object (max_insts_any_thread
    and max_insts_all_threads) rather than global parameters under the
    [max] context.

    Also replaced break_cycle check with DebugBreakEvent.

    Some cleanup of eventq.{cc,hh}.
sim/prog.hh:
    Don't die if included under FULL_SYSTEM: just skip contents.
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Added SimpleCPU object to do sim_safe type simulation in sim_smt.
    Created abstract base class BaseCPU as common parent of (detailed) CPU
    and SimpleCPU.
sim/exec_context.cc:
sim/exec_context.hh:
sim/prog.cc:
sim/prog.hh:
    Register Process object stats using SimObject reg_stats() method
    rather than indirectly via Thread end exec_context objects.
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/main.cc:
sim/sim_object.cc:
sim/sim_object.hh:
    Changes to eliminate the global 'the_cpu' pointer to allow for
    mutliple CPUs/systems.  Specifically:

    - Add findMaxThreadsPerCPU() and tickAll() static methods to
    BaseCPU class.

    - Added generic printExtraOutput() method for all SimObjects,
    to dump output at the end of simulation that is not covered by
    stats.  Use this hook on CPU object to call
    dump_floss_reasons().  sim_aux_stats() is now obsolete.

    - printExtraOutput() takes an ostream& rather than a FILE*, so
    dump_floss_reasons() had to be converted to C++ I/O.

    - Fixed a bug in floss_reasons.cc where an additional
    mem_access_result_t item (MA_NOT_PREDICTED) did not have a
    corresponding entry in mem_access_result_item_descr.  This
    resulted in "(null)" being printed with sprintf I/O (which no
    one had noticed, apparently), but caused a segfault using
    streams.
sim/exec_context.hh:
sim/main.cc:
sim/prog.cc:
sim/prog.hh:
sim/sat_counter.hh:
sim/simple_cpu.cc:
    Rename many stats to include config hierarchy path, so results from
    different CPUs/systems can be distinguished.

    Move stats.c/h into C++... renamed to stats.cc/hh.  Added overloads
    of most stat registration functions to allow 'string' rather than
    'char *' stat names & formulas... no more sprintf needed!
sim/base_cpu.cc:
sim/base_cpu.hh:
    Add sim_num_insn stats as per-CPU and total number of simulated instructions
    so we can continue to calculate sim_inst_rate.
sim/simple_cpu.cc:
    Fix sim_num_insn stat for SimpleCPU.
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Move global memory interface objects into SimpleCPU object.
    Made read/write functions SimpleCPU members for easier access to same.
    Can now do multiple systems in non-FULL_SYSTEM mode.
sim/param.hh:
sim/sim_object.cc:
sim/sim_object.hh:
    SimObjects now look in the .ini database first using the object
    instance name (e.g., sys.cpu0) *then* using the configuration class
    name (e.g., DetailedCPU).  This makes it easier to use a common
    description but override a few simple things like the workload.
base/remote_gdb.cc:
dev/console.cc:
dev/disk_image.cc:
    Make ConsoleListener & GDBListener explicitly print which ports
    they're listening on.
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/fake_syscall.cc:
arch/alpha/vtophys.hh:
base/remote_gdb.cc:
base/symtab.cc:
base/symtab.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
sim/exec_context.cc:
sim/exec_context.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/main.cc:
sim/prog.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Cleanup of full-system global variables, primarily in simple_cpu.cc,
    to allow multi-system simulations.  (Multiple systems not yet yested
    though.)  Also changes to build sim_smt in full-system mode (though
    with only SimpleCPU and not the full timing CPU for now).

    Still to do: minimize changes in SimpleCPU code between full-system
    and application modes... way too many ifdefs there.  Much of the
    full-system stuff moved into SimpleCPU should be put in a new System
    object to allow multiprocessor simulations.

    Converted last remaining modules from C to C++ (mostly in /old).
    Renamed all .c files to .cc and a few .h files to .hh.

    Renamed architecture-specific files in arch/$TARGET from
    $TARGET.{cc,hh,def} to machine.{cc,hh,def} to get rid of pointless
    intermediate files in object directory.  Split exo-specific
    definitions out of machine.hh into machine_exo.h.

    Specifics:

    In machine.def, null resource descriptors must be FUClamd_NA (and not
    NA) to pass C++ type checking.

    Enhanced error checking/reporting in bas
base/range.hh:
    Use the templated type for intermediate storage.
    Added "valid" flag and method to the user can determine if the range parse or assignment was successful.
sim/eventq.cc:
sim/eventq.hh:
    Modifications to properly count commited instructions... [no impacts]
test/Makefile:
test/offtest.cc:
    New test
test/foo.ini:
test/initest.cc:
    add Another piece to the test
arch/alpha/ev5.hh:
    Properly do alternate mode
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
sim/simple_cpu.cc:
arch/alpha/ev5.cc:
arch/alpha/isa_traits.hh:
base/hashmap.hh:
    formatting
arch/alpha/alpha_memory.cc:
    C style comment -> C++ style
arch/alpha/alpha_memory.cc:
    more formatting
arch/alpha/alpha_memory.cc:
    Add ALT_MODE support to the tlb lookup and make mode handling more sane
test/Makefile:
test/symtest.cc:
    Add a test for the symboltable
base/symtab.cc:
    Avoid some temporary objects
base/trace.cc:
    add a hexdump like dump function for dumping memory
base/trace.hh:
    Add more trace flags
    Add DUMP which does a hexdump with semantics like DPRINTF
    flush standard out after a debugging print or dump
dev/simple_disk.cc:
    Add some debugging dumps
sim/param.cc:
sim/param.hh:
sim/sim_object.cc:
    Because of order of construction, call a function that will return a
    ParamList that will construct it as soon as it is needed
dev/pcireg.h:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Flesh out the pci configuration space support.
    Add configuration file support for vendor ID and device ID.
    Clean up debugging
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Don't execute pmap_scavenge_boot.
    rename console_panic_addr to panic_addr.
    change some warn()s to DPRINTF()
base/pollevent.cc:
base/pollevent.hh:
    Don't poll every cycle.  Use SIGIO to kick a poll off.
    Make it possible to disable events
sim/exetrace.cc:
sim/exetrace.hh:
sim/simple_cpu.cc:
    Completely rework the exetrace stuff.
    Make a clas that holds all of the trace data for a particular cycle.
    Add a N entry trace log so that one can dump the last N cycles leading
    up to some sort of crash.
    When printing a branch instruction, print the target symbol if available
    instead of the address
dev/console.cc:
dev/console.hh:
sim/simple_cpu.cc:
    Make console code deal with not being polled every cycle
sim/simple_cpu.cc:
    Don't interrupt while in PAL
base/remote_gdb.cc:
base/remote_gdb.hh:
    constify some functions.
    fix some buffer handling.
    add some debugging help
sim/param.cc:
    Initialize paramList to NULL
sim/exetrace.cc:
sim/exetrace.hh:
sim/simple_cpu.cc:
    Rework the execution trace stuff again.  Merge the cycle log and the exetrace
    into one class.
    Stick the TraceData in the dyn_inst_t class.
    Put the read_foo and write_foo functions in the dyn_inst_t class.
    This gets rid of the memaccess namespace.
sim/exetrace.cc:
sim/exetrace.hh:
sim/simple_cpu.cc:
    Don't worry about which thread to trace right now.  Fix that later.
    Add better support for merged logging and tracing.
    Make sure that there is a place to put data when there is no log.
    Make tracing work for non-system.
sim/exetrace.hh:
    tracing() method must not return true if not initialized
sim/base_cpu.cc:
sim/main.cc:
    Many fixes to statistics (especially distributions)
    Many renamed statistics (added CPU name to all except cache stuff)
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
sim/intr_control.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    style fixes:
    Make class names follow the ClassName style
    Indenting based on four spaces
sim/param.cc:
    Added pipetracing
    (The trace output _should_ be compatible with the original Simplescalar
    output, making their visualization tools available to us and providing
    us with a more detailed debugging tool than exetrace)
base/trace.hh:
    Separate disk and disk data
    add tlaser uart
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
    Make this use C++ instead of void * voodoo
base/symtab.cc:
base/symtab.hh:
sim/exetrace.cc:
sim/exetrace.hh:
    constify
sim/param.hh:
    SimObjects are always pointers.  Make this clear, and add the -> operator
sim/prog.hh:
    fix comment
dev/pcireg.h:
    Don't depend on order of #includes
sim/exetrace.cc:
    Make logging work without tracing
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
sim/intr_control.cc:
sim/intr_control.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Turn all of the devices and system stuff into SimObjects.
    Add many extra parameters to have config file flexibility
base/sched_list.hh:
    file sched_list.hh was initially added on branch clustering.
dev/console.cc:
dev/disk_image.cc:
    Don't assume variables are initiaized to be zero
sim/simple_cpu.cc:
    don't forget to dump the trace data if we're tracing
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
sim/simple_cpu.cc:
    remove md_done_hwrei which was a hack that helped me
    make the trace output look like what I was able to get out of
    SimOS.  Since we're more advanced than them, it's not needed
sim/simple_cpu.cc:
    Try to make the trace more representative of what's going on.  (Mainly around
    disruptions.)
sim/simple_cpu.cc:
    Disable this code since it uses a hardcoded address.  This may be more useful
    in the future though.
sim/simple_cpu.cc:
base/statistics.hh:
    oops
base/trace.hh:
    style
base/trace.hh:
    add tracing to interrupts
sim/simple_cpu.cc:

    Removed old access call in CPUMemInterface and added MemREqs to the pipeline.
sim/prog.cc:

    Give main memory a name to fix statistics.
sim/main.cc:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Added basic infrastructure to do checkpointing. Simple test in SimpleCPU.
base/trace.hh:

    Added support for checkpoint/serialization
    Added Serilize to list of know flags
sim/param.cc:
sim/serialize.hh:

    Added support for checkpoint/serialization
    Added Serilize to list of know flags
    Now add implicit SimObjects to the ConfigHierarchy so they can be unserialized.
sim/serialize.hh:
sim/simple_cpu.cc:

    Added WH64 implementation and dependencies
    Added WH64 implementation, and added the ability to do stores of more than 4 bytes, and sett loads to 8 bytes.
base/inifile.hh:
base/str.hh:
    Use functors for the hash functions for the hashtable class.
    Pulled up from the pisa branch with a few modifications.
sim/eventq.cc:
sim/eventq.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Updated to Hierarchical naming
    Infrastructure for checkpointing.
base/inifile.cc:
base/inifile.hh:
base/trace.hh:
sim/exec_context.hh:
sim/exetrace.cc:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/simple_cpu.cc:
test/Makefile:
    - Merge PISA branch onto HEAD

    - Tag before merge: HEAD_PRE_BR_PISA_MERGE
    - Tag after merge: HEAD_POST_BR_PISA_MERGE
    - Similar tags on PISA branch

    - Add port to SimpleScalar/PISA
    - New PISA instructions:
    itouch
    spill
    reload
    map
    unmap

    - Add prefetch implementation
    - Prefetch cache
    - Cache buffer (victim/prefetch buffers)
    - Prefetch queue
    - itouch instruction

    - Add functional SLAT implementation
sim/main.cc:
    Make this work in non Linux
base/remote_gdb.cc:
sim/base_cpu.hh:
sim/simple_cpu.cc:
    Make FULL_SYSTEM work again after the pisa merge.
    Random cleanups.
sim/main.cc:
sim/memtest.cc:
sim/memtest.hh:

    Removed rules to make SIM_MEMTEST, added memtest.cc to smt source list
    Renamed sim_memtest to memtest. Memtest now extends BaseCPU and can be dropped into sim_smt. Still need to add the ability to stop it running without a manual ctrl-C though.

    Memtest currently does not test copies, just reads and writes. The multiple MSHR/Cache changes broke copying along the way.

    Just touched main to help debug (needed to give a set random seed). Its back to normal.
sim/main.cc:
    undo erik's mistaken commit
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/vtophys.cc:
base/circlebuf.cc:
base/circlebuf.hh:
base/inifile.cc:
base/inifile.hh:
base/pollevent.cc:
base/pollevent.hh:
base/range.hh:
base/remote_gdb.cc:
base/str.cc:
base/str.hh:
base/symtab.cc:
base/symtab.hh:
base/trace.cc:
base/trace.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/exec_context.cc:
sim/exetrace.cc:
sim/exetrace.hh:
sim/hybrid_pred.hh:
sim/intr_control.cc:
sim/intr_control.hh:
sim/main.cc:
sim/memtest.cc:
sim/memtest.hh:
sim/param.cc:
sim/param.hh:
sim/prog.cc:
sim/prog.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
test/bitvectest.cc:
test/foo.ini:
test/initest.cc:
test/initest.ini:
test/paramtest.cc:
test/rangetest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
    - Get rid of my String class, the Vector class, the bitvector class, and my
    doubly linked list class.
    - Convert tokenize, to_number (formerly StringToNumber) and eat_white to
    function on stl strings.
    - Change most cases of char * and const char * to string, or const string &
    - Some formatting and style nits, but not too many.
sim/param.cc:
test/bitvectest.cc:
    use resize, not reserve to change the size of the actual vector
base/str.hh:
    fix to_lower
dev/console.cc:
    better tracing
sim/memtest.cc:
sim/memtest.hh:

    Added support for CoherenceTest
    Fixed small error that was leading to a fixed address being used half of the time.
sim/exetrace.cc:
sim/exetrace.hh:
    Improvements to EXE-Trace:
    Displays thread number (optionally)
    Doesn't display 'count' field (optionally)
    'Extended' output lines up nicely
sim/memtest.cc:
    Fixed a print warning in memtest.cc
sim/exetrace.hh:
sim/main.cc:
sim/serialize.cc:
sim/serialize.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    - Merge SLAT changes

    - Add stats to prefetch cache to track cycles lost due
    to each miss address

    - Get simple_cpu and FULL_SYSTEM to compile again.  I'm
    not sure these will run correctly (simple_cpu should)
    but it is an improvement over what's currently available.

    Split the engine files into generic, cpu-specific
    and isa-specific files to isolate the various parts of
    the engine code.  This is quite hackish in places due to
    machine.def (e.g. see comments in execute.cc).  Further
    cleanup is warranted but it compiles and passes smt-test.
    Later commits will remove unused code.
base/trace.hh:
sim/param.cc:
sim/sim_object.cc:
    add a new DTRACE macro that tests a trace variable if tracing is on, or
    evaluates to fals if tracing is off.  Avoids #if TRACING_ON/#endif

    add an option for wheter or not you want the parameter stuff dumped while
    the simulator is starting
sim/exetrace.cc:
sim/exetrace.hh:
    Make the execution trace print the way it did before steve's last change.
    Also, pass the flags in a more intelligent manner rather than adding new
    function parameters all over the place.
sim/exetrace.hh:
sim/simple_cpu.hh:
    make exetrace work in FULL_SYSTEM after dave's last changes.
    Exetrace could probably be improved more to remove most of the
    #ifdef FULL_SYSTEM junk.  Not today though
base/trace.hh:
    new trace flags
dev/alpha_console.cc:
    size was too big
dev/pcireg.h:
    new device ID for simos ethernet device
dev/disk_image.cc:
dev/simple_disk.cc:
dev/simple_disk.hh:
    be smarter about using stl strings
sim/pc_event.cc:
sim/pc_event.hh:
    PC based event system
sim/simple_cpu.cc:
    Make all existing pc based stuff use the new pc based events
base/trace.cc:
base/trace.hh:
sim/param.cc:
sim/sim_object.cc:
    If we're not tracing, print out the configuration junk.  If we are tracing,
    the configuration printing is default
sim/exetrace.cc:
    - Fix bogus references to omitCount and includeTnum.
base/kgdb.h:
base/remote_gdb.cc:
base/remote_gdb.hh:
    TONS of improvements to remote kernel debugging.

    -  Use the pc based events stuff to simulate hardware breakpoints.
    -  Implement the set/clear breakpoint/watchpoint function, though
    only breakpoints are implemented right now.
    Both software and hardware breakpoints are implemented as hardware
    breakpoints.
    -  Fix numerous bugs in single stepping, and make temporary breakpoints
    use hardware breakpoints instead of software breakpoints.
    -  Add tons of debugging stuff to help with future remote debugger debugging.
    (No, that was not an accidental doubling.)
    -  Implement part of the query variable function.
    -  Remove old cruft that we don't need.
    -  Improve comments
dev/disk_image.cc:
dev/disk_image.hh:
    Copy on write disk support
    This code uses a hash table to implement copy on write support to disk image
    blocks.  There is also support to write out the table and load it back in.
dev/simple_disk.cc:
    This class uses std::string
sim/simple_cpu.hh:
    don't need these
base/circlebuf.cc:
base/circlebuf.hh:
    Add some size information so we can keep track of wheter or not the buffer
    is empty
arch/alpha/vtophys.cc:
    simplify
base/object_file.cc:
base/object_file.hh:
    initial framework for sucking in an object file and figuring out some stuff
    for it.  Support for ecoff and a header for elf.  There is nothing for
    relocations, but the symbol information is available so an external
    program is no longer required for that.
base/symtab.cc:
base/symtab.hh:
    Update some of the symbol table stuff to add support for manual insertion of
    symbols.  This is used by the object file code so that we can read the
    table from the object file and stick it into the more efficient symtab
test/Makefile:
test/nmtest.cc:
    test program for using the symbol table code.  Basically allows one to look
    up a symbol in an object file
dev/console.cc:
dev/console.hh:
    Clean up the console code, add an input buffer queue to avoid leaving data in
    the socket buffer.  This allows us to preprocess data as it comes in for
    things such as telnet support.  There is some minimal telnet support in here
    but it isn't working very well, and isn't enabled by default
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Make the various pc based events part of the CPU object instead of being
    global
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Do the badaddr stuff far more intelligently.  Basically, what we do now
    is first determine if the address goes to any proper device.  If not, the
    address is bad.  If so, ask the device whether the address is any good or
    not.  The default case is that a device will say that all of its addresses
    are good, but there are some devices that don't follow this paradigm.
dev/alpha_console.cc:
dev/alpha_console.hh:
sim/intr_control.cc:
sim/intr_control.hh:
sim/universe.cc:
    Make the tick frequency a global parameter and have all devices work from that
    Also, make the timer interrupt delay parameterizeable (and make the default
    shorter).  This should make boot happen a little faster
base/refcnt.hh:
    Simple reference counting class.  Could be replaced by boost shared_ptr some
    day.

    Classes that are reference counted must have exported functions incref()
    and decref() for manipulating the reference count.  This doesn't have the
    convenience of shared_ptr where the shared classes can be used unmodified,
    but it also means that the refcnt pointer (the pointer in this code) is
    the size of a normal pointer for this system.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherpkt.hh:
    Initial hack at a ethernet device model and an ethernet bus model.  Known to
    be broken at this point
arch/alpha/alpha_memory.cc:
sim/simple_cpu.cc:

    Memory system enhancements:

    - Functional implementation of load-locked/store-conditional in
    main_memory object (the functional memory object for non-full-system
    mode).  This code should eventually be extracted out and applied to
    both main_memory and physical_memory so that it works in full-system
    mode as well.  Moved lock_flag & lock_addr from system registers to
    control registers so they're available in non-full-system mode.

    - Moved Alpha unaligned access handling back into machine.def.  (It
    was a flag on the mem request and handled in the memory system, but
    that approach appears to be unnecessarily complicated.)

    - Cleanup of AlphaMemoryRequest: down from five constructors to one;
    Erik's full-word flags are now bits in Nate's flag word.

    - Eliminate obsolete memory.h functions, and some unused memory_object
    functions.
arch/alpha/vtophys.cc:
base/remote_gdb.cc:
sim/prog.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:

    Renamed SimpleCPU::(read|write)_(byte|half|word|qword) to just read &
    write, overloaded on the type of the 'data' argument.  Merged the
    full-system and non-full-system implementations of these eight
    original functions into two common template functions.

    To support this, also renamed (read|write)[1248] on memory_object and
    derivatives to just read & write, again overloaded on the type of the
    'data' argument.  Many of these functions could now be condensed into
    a few template functions (though with a level of indirection so that
    the interface can remain virtual).  I did not do that though.
sim/exec_context.hh:
sim/pc_event.hh:
    - Eliminate static SLAT variables when building FULL_SYSTEM
base/remote_gdb.cc:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    make it easier to drop into the remote debugger from within the local debugger
dev/pcireg.h:
    Instead of having each pci device define its own sim object to represent
    the configuration space, just define one TlaserPciDev type and change the
    configuration regs as needed.
base/range.hh:
    Fix bugs in range parsing code.
sim/eventq.hh:
    Uncomment inlined event check (not sure why it was commented out
    to begin with).
base/str.hh:
    - Add some missing #includes.

    - Remove some prefetching stats to shorten log lengths.

    - Fix perfect cache to work with new coherence mechanism
    (or at least not fail when there is no coherence protocol).
base/range.hh:
    Consider whether a range object is valid or not when doing range tests.
    Reorganization & minor documentation of range comparison code.
sim/exetrace.hh:
    Bug fix related to previous commit on range.hh.
test/nmtest.cc:
    Add ability to do lookups by address
dev/etherbus.cc:
base/statistics.cc:
    fix
sim/simple_cpu.cc:
    make it so we can change the boot flag
sim/simple_cpu.cc:
    Bit more debugging info
base/circlebuf.cc:
    Must initialize the size
dev/console.cc:
sim/simple_cpu.cc:
    better debugging
base/remote_gdb.cc:
    Don't panic if the execution context isn't the same, just don't execute the
    breakpoint since it probably belongs to another instance
sim/memtest.cc:
    Removed bcopy_in & bcopy_out (needless aliases for prot_write &
    prot_read, respectively).  Made prot_read & prot_write public methods
    (not protected).  Had to change some char arrays to byte_t to keep
    compiler happy.

    Renamed strcpy_in and strcpy_out to writeString and readString,
    respectively, to reduce confusion about the direction they operate.

    Also some reformatting for style.
sim/main.cc:
    Move some more old simplescalar I/O from stdio to C++ streams.

    Some reformatting for style in main.cc as well.
base/inifile.cc:
base/inifile.hh:
    Pass -D, -U, and -I args to cpp for ini-file processing.  Should make
    use of #defines in .ini files much handier, once we get our parser up
    to dealing with the resulting whitespace issues.

    Some reformatting for style as well.
sim/main.cc:
    Pass -D, -U, and -I args to cpp for ini-file processing.  Should make
    use of #defines in .ini files much handier, once we get our parser up
    to dealing with the resulting whitespace issues.
sim/exetrace.cc:
sim/exetrace.hh:
sim/simple_cpu.cc:
    Changes to exetrace code to make it somewhat less schizophrenic so
    that it works under non-full-system SimpleCPU.  (Previous code assumed
    either full-system+simple CPU or non-full-system+detailed CPU.)

    Also removed a lot of unused code in simple_cpu.cc.
base/trace.hh:
    Added trace flags to display all syscalls or common syscall-related
    warnings (which are suppressed by default).
arch/alpha/fake_syscall.cc:
sim/exec_context.cc:
sim/exec_context.hh:
sim/prog.cc:
sim/prog.hh:
sim/simple_cpu.cc:
    Syscall emulation (non-full-system) support for multithreaded apps
    compiled using Tru64 5.1's pthreads library.

    More specifically, you can now associate multiple processors with a
    single LiveProcess object (via their workload parameters).  Only one
    processor will be active initially.  The additional processors will
    be assigned to handle new "virtual processor" threads as they are
    created by the pthreads user library.  Functionality is limited, as
    we do *not* emulate any kernel scheduling: once a VP thread is created,
    it is permanently bound to a simulated CPU.  However, most of the
    SPLASH-2 benchmarks seem to run on both uni- and dual-processor targets.

    Includes total rewrite of syscall emulation (fake_syscall.cc).  Only
    syscalls that have been needed thus far have been re-implemented in
    the new framework.  Others will be moved over on demand.
base/trace.cc:
    Better dump function
sim/simple_cpu.cc:
    The active field of exe_ctx is not used in FULL_SYSTEM
sim/eventq.cc:
dev/etherbus.cc:
    more debugging
sim/memtest.cc:

    Added support for mem_cmd.cc

    Transitioned from enum mem_cmd to class MemCmd
sim/eventq.hh:
sim/param.hh:
sim/serialize.hh:
sim/sim_object.hh:
test/sized_test.cc:
    - Fix PISA syscalls to use new memory interface.

    - Make prefetching a real SimObject and port existing
    prefetchers to the new framework.
base/inet.cc:
base/inet.hh:
    Move functions for networking into a separate file
sim/exec_context.cc:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Add basic support for a quiesce instruction.
    - Suspend the current thread on quiesce
    - Resume on interrupt
    Add an arm instruction that doesn't do anything yet
sim/simple_cpu.cc:
    Added FULL_SYSTEM wrapper to use of "proc" in tick().
    Nate, please check to make sure I didn't break it.
base/inifile.hh:
    Added include of vector
base/trace.hh:
    - Create a ScsiDevice base class that represents all of the functions that a
    SCSI device might want to implement
    - Clean up the ScsiDisk class: remove unneeded junk and give better names
    - Create a ScsiNone class that is used when a given target has no device
sim/main.cc:
    Always use the same random seed to make the memory tester repeatable.
    As the comment says, someday we should make this a parameter.
    (Do we still need "mysrand()" and "myrand()"?)
sim/memtest.cc:
sim/memtest.hh:
    - Get rid of CoherenceTest... MemTest is just as capable.
    - Lots of new parameters for MemTest.
sim/pc_event.cc:
    Don't execute a pc event twice
dev/disk_image.cc:
    Add a config node of the copy on write disk image
base/trace.hh:
dev/disk_image.cc:
    More debugging
base/trace.hh:
    Major update in dma code.
    -  Separate the io callback into a read callback and a write callback
    -  Fix the write callback so that the proper data is written back to the
    disk and data is copied to the proper place in the data buffer
    -  Use sim_freq for the tick frequency.  (There is still no delay)
    -  Remove a bunch of unnecessary code
    -  Make code more concise and remove old cruft
    -  More Debugging (of course)
    -  Formatting fixes
    -  mprotect hack to make sure that dma buffer is not overwritten
sim/exec_context.cc:
sim/exec_context.hh:
    Fix broken assertion in main_memory::checkLockedAddrList().
    Check for lots of failed store-conditionals and print deadlock warning message.
arch/alpha/fake_syscall.cc:
    Use actual number of CPUs allocated to process (not const 2!).
    A few additional syscalls for pthreads support (not quite there yet though).
sim/prog.cc:
sim/prog.hh:
    Use actual number of CPUs allocated to process (not const 2!).
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/fake_syscall.cc:
base/remote_gdb.cc:
base/remote_gdb.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/pc_event.cc:
sim/pc_event.hh:
sim/prog.cc:
sim/prog.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    exec_context_t -> ExecContext
    spec_exec_context_t -> SpecExecContext
dev/disk_image.cc:
    quell warnings
base/trace.hh:
    remove more warnings
sim/exec_context.cc:
sim/exec_context.hh:
sim/prog.cc:
sim/prog.hh:
sim/simple_cpu.cc:
    remove the Process object from FULL_SYSTEM since it doesn't really make
    any sense
sim/simple_cpu.cc:
    move SIM_OBJECT junk to the end like other files
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Make it so we can use a memory hierarchy in FULL_SYSTEM SimpleCPU
arch/alpha/fake_syscall.cc:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/prog.cc:
sim/prog.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    - Add pointer from execution context to the CPU it's running on.
    - Just pass execution context pointer to the syscall emulation code,
    instead of a bunch of individual field arguments.
    - A few more exec_context_t -> ExecContext changes for non-full-system.
    - Rudimentary thread scheduling for non-full-system support of
    pthreads apps.  Hopefully this won't go much farther.
sim/exec_context.cc:
    Oops... fix minor bug from merge.
arch/alpha/fake_syscall.cc:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/prog.cc:
sim/prog.hh:
sim/simple_cpu.cc:
    - We really don't want to build a thread scheduler in the simulator...
    rip all that out, and replace with some basic synchronization
    primitives implemented as syscalls.  Non-full-system MP apps thus
    need to be compiled specially to use these primitives, but it's
    plenty good enough to get SPLASH-2 up and running.

    These primitives block by suspending the execution context (for
    efficient simulation).  Studies that care about synch operation
    costs should use user-level LL/SC-based primitives instead.

    - Implement more than two states (active vs. !active) for an ExecContext.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/fake_syscall.cc:
arch/alpha/vtophys.cc:
base/circlebuf.cc:
base/fast_alloc.cc:
base/inifile.cc:
base/inifile.hh:
base/object_file.cc:
base/object_file.hh:
base/range.hh:
base/remote_gdb.cc:
base/res_list.hh:
base/socket.cc:
base/str.cc:
base/str.hh:
base/symtab.cc:
base/symtab.hh:
base/trace.cc:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/simple_disk.hh:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/eventq.cc:
sim/exetrace.cc:
sim/exetrace.hh:
sim/hybrid_pred.hh:
sim/intr_control.cc:
sim/intr_control.hh:
sim/main.cc:
sim/memtest.cc:
sim/memtest.hh:
sim/param.cc:
sim/param.hh:
sim/pc_event.hh:
sim/prog.cc:
sim/prog.hh:
sim/sat_counter.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_object.cc:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/universe.cc:
    First pass at compiling with gcc 3.x.  Lots of "std::" in header files,
    "using namespace std" in source files.  (Note policy of not putting "using"
    statements in headers or before includes in sources.)

    Still not able to compile with gcc 3.2.
    Errors:
    - Can't create an ifstream from a file descriptor anymore (breaks IniFile).
    - "`class MSHR::MSHRegister' is private" errors in mshr.cc and prefetch_cache.cc:
    not clear why since it's in the public part of the class declaration.
    - cpu.cc:879: can't match a reference and 0 (specifically "no match for `bool ?
    SimObjectParam<PipeTrace*>& : int' operator")
    - pipetrace.cc: "invalid conversion from `int' to `std::_Ios_Fmtflags'"
    Warnings:
    - strstream now deprecated... needs some rewriting in sat_counter.hh
    and hybrid_pred.hh (need to get all that code out of the headers anyway)
    - trace.hh macro problem: cpp now says 'pasting "::" and "Event" does not
    give a valid preprocessing token'
    - major "implicit typename" issues in base/sized.hh
base/trace.hh:
    Token pasting not necessary.  Quiets g++ 3.2 warning
base/inifile.cc:
base/inifile.hh:
    Make this compile in g++ 3.2
base/remote_gdb.hh:
dev/etherbus.hh:
dev/pcireg.h:
dev/simple_disk.cc:
    Make this stuff g++ 3.2 happy
base/inifile.cc:
    Make this still compile in g++ 2.95
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
sim/serialize.hh:
sim/simple_cpu.cc:
    Added serialization for simple FULL_SYSTEM objects. Working on the hard ones
sim/simple_cpu.cc:
    Make this code actually compile.  Fix style while we're at it
sim/base_cpu.cc:
    Fixes to recent updates to maintain gcc 3.2 compatibility
    (mostly more std:: in header files).
test/Makefile:
    SS -> M5
base/cprintf.cc:
base/cprintf.hh:
test/Makefile:
test/cprintftest.cc:
    printf replacement that uses C++ io streams and is typesafe
    Any type that overloads operator<< for use with streams will work with this
    structure.

    The format string is backwards compatible with printf style format strings,
    but the types are not checked, for example, %s doesn't verify that the
    type being printed is a string, %d doesn't verify that the type being
    printed is an integer.  Instead, the various formats just set up the proper
    io stream manipulators for printing.  So, %#s doesn't mean anything different
    from %s, but %#x does mean something different from %x.  If the type you are
    printing does't care about the #, then nothing changes.
base/cprintf.hh:
test/cprintftest.cc:
    Fix case where there is only a format string, and no arguments
base/cprintf.hh:
base/cprintf_formats.hh:
    std::
base/trace.cc:
base/trace.hh:
    Make the tracing stuff use cprintf
base/cprintf.cc:
    Save and restore iostream state
dev/etherbus.cc:
    Rewrite the dma engine support so that it can interact with the dma_interface
    to the timing memory model.  This way, all of the timing of the dma transfers
    themselves can come from the memory system.  Simos copyright removed since
    this code shares nothing with Simos
sim/hybrid_pred.hh:
sim/predictor.hh:
sim/sat_counter.hh:
    Fixes to stat names in segmented IQ
    Changes from strstream to stringstream to remove warnings
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherint.hh:
    Separate the interface to the bus from the device
sim/simple_cpu.cc:
    Move progress message from SimpleCPU::tick() to new ProgressEvent.
    (Much more efficient, and available independent of CPU model.)
dev/console.cc:
dev/console.hh:
    Added [DoEvents] default so command line --DoEvents:do_events=1 turns on events for all busses
    Added serlization function headers (not implemented yet).
sim/eventq.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Added [DoEvents] default so command line --DoEvents:do_events=1 turns on events for all busses
    Added serlization function headers (not implemented yet).
    Added EventQueue::nextEventTime(), returns time head is scheduled, or sim_cycle if empty.

    Added support for uniprocessor SimpleCPU with timing memory.
arch/alpha/fake_syscall.cc:
base/remote_gdb.cc:
sim/exec_context.hh:
sim/prog.cc:
sim/simple_cpu.cc:
    Get rid of redundant ExecContext PC field.
sim/main.cc:
    Add -n option to suppress loading default.ini.
    Added a little more help to the help message.
sim/main.cc:
    Oops... make sure we still load it when we don't say '-n'.
sim/main.cc:
    Minor formatting.
sim/exetrace.cc:
sim/exetrace.hh:
    Merge full-system & non-full-system exetrace code.
base/cprintf.cc:
base/cprintf.hh:
    Previous two commits were (somewhat) broken... this is the real one
test/cprintftest.cc:
    more testing
base/remote_gdb.cc:
base/remote_gdb.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/pc_event.cc:
sim/pc_event.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/system.cc:
sim/system.hh:
    Moved a lot of full-system variables out of SimpleCPU so that they can
    (eventually) be used with the detailed CPU model.  Several fields
    moved into the ExecContext, while a few others moved into a new System
    object (which replaces the old Kernel object, for now at least).
sim/exetrace.cc:
sim/pc_event.cc:
sim/pc_event.hh:
sim/simple_cpu.cc:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
    - Many g++ 3.2 fixes

    - Added Makefile magic to allow a comprehensive build of
    all simulator variants on all archtectures.  'make all'
    or 'make TARGET=<arch> all_flavors'

    - Added container adaptors and associative_table.  Don't
    use these quite yet -- they are very expensive to
    compile.  Am currently converting them over to boost::mpl.
    They are used by the new BHGP prefetcher.

    - Moved md_sysreg_t reg_t entries to isa_traits.  PISA
    does not have these sorts of registers.

    - Moved ipr accesses to theISAEngineTraits because they
    are not generally applicable.  These are #ifdef FULL_SYSTEM
    in the simulator code -- eventually this should get worked
    into the traits structure.
base/fifo_buffer.cc:
base/fifo_buffer.hh:
    Initial add of this incredibly usefull utility object
arch/alpha/ev5.cc:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/remote_gdb.cc:
sim/exec_context.cc:
sim/exec_context.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/system.cc:
    Implement some interval statistics for full system mode.
    Create a callpal function that is called when a callpal occurs so it's easier
    to manipulate the statics.
    Rework the vtophys stuff to make it a bit cleaner.
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
    Keep track of all callpals in the interval stats
base/res_list.hh:
base/sched_list.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/hybrid_pred.hh:
sim/main.cc:
sim/predictor.hh:
sim/prog.cc:
sim/sat_counter.hh:

    TA DA!!!!

    The giant, huge, amazing, i-hope-i-never-have-to-do-that-again,

    CLUSTERING MERGE!!!!

    \
base/fifo_buffer.hh:
sim/exetrace.hh:
    Minor adjustments for GCC 3 compatibility
    Turn ptrace features back on
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/ev5.cc:
arch/alpha/fake_syscall.cc:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/remote_gdb.hh:
dev/alpha_console.cc:
dev/simple_disk.cc:
dev/simple_disk.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/exetrace.hh:
sim/memtest.cc:
sim/memtest.hh:
sim/prog.cc:
sim/prog.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/system.cc:
sim/system.hh:
    Get rid of almost all old-style object names.  This commit is equivalent
    to running the following script on the current head:

    #! /bin/sh

    find \( -name '*.cc' -o -name '*.hh' \) -exec perl -pi -e '\
    s/\bmemory_object\b(?!\.hh)/FunctionalMemory/g;\
    s/\bvirtual_memory\b(?!\.hh)/VirtualMemory/g;\
    s/\bmain_memory\b(?!\.hh)/MainMemory/g;\
    s/\bphysical_memory\b(?!\.hh)/PhysicalMemory/g;\
    s/\bspec_memory\b(?!\.hh)/SpeculativeMemory/g;\
    s/\bMemObj\b(?!\.hh)/TimingMemObj/g;\
    s/\bmemory_translation\b(?!\.hh)/AddressTranslator/g;\
    s/\balpha_tlb\b(?!\.hh)/AlphaTlb/g;\
    s/\balpha_itb\b(?!\.hh)/AlphaItb/g;\
    s/\balpha_dtb\b(?!\.hh)/AlphaDtb/g;\
    s/\bmemory_controller\b(?!\.hh)/MemoryController/g;\
    s/\bstorebuffer_t\b(?!\.hh)/StoreBuffer/g;\
    s/\bstorebuffer_entry_t\b(?!\.hh)/StoreBufferEntry/g;\
    s/\bcreate_vector_t\b(?!\.hh)/CreateVector/g;\
    s/\bcv_spec_state\b(?!\.hh)/CreateVecSpecState/g;\
    s/\bspec_state_list\b(?!\.hh)/SpecStateList/g;\
    s/\bdyn_inst_t\b(?!\.hh)/DynInst/g;' {} \;
arch/alpha/fake_syscall.cc:
sim/exec_context.hh:
sim/memtest.hh:
sim/simple_cpu.cc:
    Renamed files to better match new object names:
    base_memory.{cc,hh} --> functional_memory.{cc,hh}
    mem_obj.{cc,hh} --> timing_mem_obj.{cc,hh}
sim/exec_context.cc:
sim/exec_context.hh:
sim/prog.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Detailed CPU now compiles in full-system mode (but doesn't run, so I
    didn't add it to the makefile).

    SLAT code is now protected by '#ifdef USE_SLAT', since it's not currently
    compatible with full-system mode.  Also, slat.cc is not compiled by
    default.  We will need a makefile option to do '-DUSE_SLAT' and add
    slat.cc to the source list.

    CPU::Thread object is gone; these are now just bare SpecExecContexts.

    Changed all remaining {read,write}_{byte,half,word,qword} sets of methods
    to just read/write template methods, where possible.
sim/system.cc:
sim/system.hh:
    Make the system boot flag a paramter
arch/alpha/ev5.hh:
sim/intr_control.hh:
    The ethernet device was interrupting on the wrong interrupt line.  Line 0x17
    is too high (it's higher than the clock interrupt) and it doesn't correspond
    with the spl protection in the driver source.

    To solve this, we hack in support to support multiple interrupts at a single
    level and have scsi and ethernet share the same interrupt level.
dev/etherbus.cc:
dev/etherint.hh:
    Make the bus call back to the ethernet interface when the transfer is
    complete.  This allows the interface to do the next request in the transmit
    buffer if there is one.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
    Add etherdump object which accepts packets and spits them out in tcpdump
    format for analysis with tcpdump and ethereal.

    Make the etherbus support the dump object
dev/etherint.cc:
    make the ethernet interface a SimObject that you can refer to
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
    Add a different connection type between ethernet interfaces.
    The ether link is a unidirectional fixed bandwidth link.  To simulate
    a full duplex 100MB/s ethernet, you need two etherlinks. It's just much
    easier to simulate a full duplex link this way.  Maybe encapsulate this into
    another bidirectional link sometime.
sim/exec_context.hh:
sim/main.cc:
sim/simple_cpu.cc:
sim/system.cc:
    Add a halted state to the simulator and only actually exit the simulator
    when all systems have halted.  While we're at it, remove an if statement
    from the common code path in SimpleCPU::tick
sim/exec_context.hh:
sim/simple_cpu.cc:
    IntervalStatsObject -> IntervalStats
test/Makefile:
    Make this work again
base/cprintf.hh:
    #include guard
arch/alpha/alpha_memory.cc:
arch/alpha/vtophys.cc:
base/remote_gdb.cc:
dev/alpha_console.cc:
dev/console.cc:
dev/disk_image.cc:
dev/etherbus.cc:
dev/simple_disk.cc:
sim/eventq.cc:
sim/pc_event.cc:
sim/simple_cpu.cc:
    since cprintf properly deals with 64-bit types, stop using FMT* as much as
    possible
base/circlebuf.cc:
base/inet.cc:
base/inet.hh:
base/object_file.cc:
base/res_list.hh:
    convert some stdio stuff to use cprintf/c++ streams
dev/console.cc:
dev/console.hh:
    convert some stdio stuff to use cprintf/c++ streams
    better use of format strings
sim/exec_context.hh:
sim/exetrace.cc:
sim/exetrace.hh:
    - Make SLAT work with new execution context

    - Temporarily fix include file problems (circular includes)
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/fake_syscall.cc:
sim/eventq.hh:
sim/hybrid_pred.hh:
sim/main.cc:
    True and false are keywords in C++, don't use TRUE and FALSE
    This can be done with the following script:

    #!/bin/sh
    for each in `find . \( -name '*.cc' -o -name '*.hh' \)`; do
    perl -pi -e '\
    s/\bFALSE\b/false/g;\
    s/\bTRUE\b/true/g;' $each
    done
base/cprintf.cc:
base/cprintf.hh:
test/Makefile:
test/cprintftest.cc:
    Add support for 'terminators' to cprintf.  This is esentially a special
    manipulator that can cause some sort of event to occur when the stream
    is outputted.  (Will be used for panic, fatal, etc.)
base/cprintf.cc:
base/cprintf.hh:
    Another cleanup fo the cprintf stuff.  This should make it much easier to do
    panic, etc.
sim/simple_cpu.cc:
    Rename sim_num_refs to SIM:num_refs to match Steve's new naming
    in the detailed CPU stats.
base/cprintf.cc:
base/cprintf.hh:
    Get rid of the reference counting and the pass by value, and come up with
    a way to remove all of the temporary variables that are created, and only
    create one.  Should make the compiler's burden much less
sim/pc_event.hh:
    quell warning
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/fake_syscall.cc:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/inet.cc:
base/inet.hh:
base/object_file.cc:
base/object_file.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/trace.cc:
base/trace.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherpkt.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
sim/exetrace.hh:
sim/memtest.cc:
sim/memtest.hh:
sim/pc_event.cc:
sim/serialize.cc:
sim/serialize.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/system.cc:
    Change byte_t etc. to C99 standard int8_t etc.
    Other than old/host.h, all other changes were produced by this script:

    #! /bin/sh

    find \( -name '*.cc' -o -name '*.hh' -o -name '*.c' -o -name '*.h' -o -name 'machine.def' \) -exec perl -pi -e '\
    s/\bbyte_t\b(?!\.hh)/uint8_t/g;\
    s/\bsbyte_t\b(?!\.hh)/int8_t/g;\
    s/\bhalf_t\b(?!\.hh)/uint16_t/g;\
    s/\bshalf_t\b(?!\.hh)/int16_t/g;\
    s/\bword_t\b(?!\.hh)/uint32_t/g;\
    s/\bsword_t\b(?!\.hh)/int32_t/g;\
    s/\bqword_t\b(?!\.hh)/uint64_t/g;\
    s/\bsqword_t\b(?!\.hh)/int64_t/g;\
    s/\bbool_t\b(?!\.hh)/bool/g;\
    s/\bdfloat_t\b(?!\.hh)/double/g;\
    s/\bsfloat_t\b(?!\.hh)/float/g;' {} \;
sim/simple_cpu.cc:
    Assume preprocessor can do ANSI '##' token pasting.
arch/alpha/fake_syscall.cc:
base/misc.cc:
base/misc.hh:
base/pollevent.cc:
base/sched_list.hh:
base/socket.cc:
base/symtab.cc:
dev/console.cc:
dev/disk_image.cc:
dev/simple_disk.cc:
sim/base_cpu.cc:
sim/eventq.cc:
sim/intr_control.hh:
sim/main.cc:
sim/memtest.cc:
sim/param.cc:
sim/serialize.cc:
sim/sim_object.cc:
sim/simple_cpu.cc:
    Get closer to removing all FMT64 junk and myfprintf stuff
    Make panic, flatal, warn use cprintf.
    Start moving away from the old/misc.(cc|h) files.
dev/simple_disk.cc:
    Get rid of some FMT junk
dev/etherdump.cc:
dev/pcireg.h:
    u_int* -> uint*
dev/etherdump.cc:
    sys/time.h instead of time.h
arch/alpha/ev5.cc:
sim/exec_context.cc:
sim/exec_context.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Do some clean up in the manner that the interval stats object is created
    Also, use the interval stats range when doing my full-system istats.
    Finally, don't make the interval stats part of the exec_context since it makes
    little sense to do so.  We're only going to have one interval stats
    object (at least for now.)
base/mod_num.hh:
    Initial addition of a "modulo-number" class
sim/eventq.cc:
sim/eventq.hh:
    convert some stdio to iostream
sim/eventq.cc:
sim/eventq.hh:
sim/main.cc:
sim/sim_events.cc:
sim/sim_events.hh:
sim/simple_cpu.cc:
    Move some common events into a new sim_events file.  Rearrange some other
    things to move towards having only events in the main loop.
sim/eventq.hh:
    Change protections
base/pollevent.cc:
base/pollevent.hh:
    proper destruction
dev/console.cc:
    don't panic on connection error.  detach.
sim/eventq.cc:
sim/eventq.hh:
    Clean up event queue and add support for priorities
sim/eventq.cc:
sim/main.cc:
sim/memtest.cc:
sim/serialize.cc:
sim/sim_events.cc:
sim/sim_events.hh:
    Get rid of sim_exit_now and make it an event.
    Get rid of sim_dump_stats and make it an event.
    Main loop is now reduced to servicing the event queue, ticking the
    CPUs, and incrementing sim_cycle
sim/simple_cpu.hh:
    formatting nits
base/cprintf.hh:
dev/etherdump.cc:
dev/etherdump.hh:
sim/eventq.hh:
sim/sim_events.cc:
    - ANSI/ISO C++ fixes

    - Improve SLAT efficiency

    - Add build_test rule to compile across all archs
    and options.  This builds one simulator from each
    combination including the optimized Alpha simulator
    to run smt-test.  Please run this before committing.
base/misc.cc:
    make warnings less verbose
sim/eventq.hh:
    Generic function that will delay the calling of a member function until a
    specified cycle.

    Has problems if you use it with gcc 2.95, but 3.2 compiles it ok.
dev/etherbus.cc:
    Better debugging
dev/etherbus.cc:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
    Rework the EtherInt class to represent a generic Ethernet interface.  Any
    object that wishes to connect to another device and pass ethernet packets
    must export an ethernet interface.  This makes it possible to connect any
    two objects that have ethernet interfaces.  For example, one EtherDev can
    connect directly to another etherdev, or the two EtherDevs can each attach
    to one of the interfaces on an EtherLink to get a fixed bandwidth.
dev/ethertap.cc:
dev/ethertap.hh:
util/tap/Makefile:
util/tap/tap.cc:
    The ethertap device and ethertap utility allow a simulator to connect to a
    real physical ethernet.  Currently, the tap utility only works on OpenBSD,
    but that should be easily fixed.
dev/ethertap.cc:
dev/ethertap.hh:
    better bounds checking
base/cprintf.hh:
    change function names in cprintf
base/trace.cc:
base/trace.hh:
    Make DPRINTF work more like panic, fatal, warn, etc.  Also make it possible
    to redirect trace output to a file instead of stdout.
dev/etherlink.cc:
dev/etherlink.hh:
    Make EtherLink::Link Serializeable
arch/alpha/alpha_memory.cc:
base/remote_gdb.cc:
base/res_list.hh:
base/trace.cc:
base/trace.hh:
dev/console.cc:
dev/disk_image.cc:
dev/etherbus.cc:
dev/etherlink.cc:
dev/ethertap.cc:
dev/simple_disk.cc:
sim/eventq.cc:
sim/eventq.hh:
sim/pc_event.cc:
sim/serialize.cc:
sim/simple_cpu.cc:
    rework DPRINTF to automatically print the cycle and get the name of the
    object from which it was called.

    Additionally, while we're at it change 0x%x -> %#x
dev/disk_image.cc:
sim/pc_event.cc:
sim/serialize.cc:
    dont use c_str() if we don't have to
base/trace.cc:
    Only delete the stream if we created it
base/trace.cc:
base/trace.hh:
    Expose ostream to which tracing statements are sent via DebugOut()
dev/console.cc:
    carriage return not necessary
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
    Add support for accessing function arguments from a kernel function.
    The class behaves somewhat like a random access iterator so that the user can
    access any argument desired, but to get at the data, the user uses the
    casting operators to get at the data pointed to by the arguments
sim/pc_event.cc:
sim/pc_event.hh:
    inline
sim/pc_event.cc:
sim/pc_event.hh:
sim/system.cc:
sim/system.hh:
    create a pc based event that traps kernel printfs for debugging statements
arch/alpha/arguments.hh:
    rename to CopyData and use void * to avoid compiler problems
sim/pc_event.cc:
    Make Kernel::Printf take AlphaArguments as a parameter so that a user may
    add initial arguments to another version of the kernel function and then
    pass an offset arguments class to the function for printing the data.
    Also, while we're at it, remove the printing of the cycle.  That can be done
    by the caller.
base/trace.hh:
sim/pc_event.cc:
sim/pc_event.hh:
sim/system.cc:
sim/system.hh:
    Separate the printf event from the debugging printf event.  The kernel will
    call the debugging printf event m5printf.  There is also a raw version
    m5printfr that indicates to the simulator that it shouldn't print
    any extra information in the context of this debuggin printf because
    it would screw up fromatting.
sim/pc_event.cc:
    symmetry
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
    plug huge leak
arch/alpha/arguments.hh:
    Add std:: to list
arch/alpha/arguments.hh:
    make the execution context available
dev/etherlink.cc:
    formatting, typeo, paranoia
sim/system.cc:
sim/system.hh:
    enable the mbuf dump code
sim/pc_event.cc:
sim/pc_event.hh:
    Add a pc event for the kernel mbuf dump function
arch/alpha/fake_syscall.cc:
sim/main.cc:
    I can see no good reason at all for doing setjmp/longjmp
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
    reference count the argument data so that the data doesn't disappear before
    we're done using it.
sim/main.cc:
    move all signal stuff into main.cc
sim/sim_events.cc:
    Move termination and progress event initialization to sim_events
sim/debug.cc:
sim/debug.hh:
sim/main.cc:
sim/pc_event.cc:
sim/simple_cpu.cc:
    Move some of the debug break stuff to its own file
    Use SIGTRAP to initiate a break and set up the simulator to ignore the signal.
    This will make gdb automatically stop in these functions, but won't interfere
    with normal simulator workings.
sim/sim_events.cc:
    Id string
sim/sim_events.cc:
    make g++ 3 happy
base/cprintf.cc:
base/cprintf.hh:
base/misc.cc:
base/misc.hh:
base/trace.cc:
base/trace.hh:
    - Rename debug rule to dbg so it doesn't interfere
    with debug.cc.

    - Reorganize build_test so it generates dependencies
    correctly.

    - Remove HashTable from spec_memory and replace with
    SGI's hash_map extension.

    - Put cprintf/ArgList in namespace cp so it doesn't
    interfere with g++ 2.95 std::deque (comma operator
    gives problems -- this is a g++ 2.95 bug).

    - Fix FP register decode in dispatch.  PISA registers
    > 31 were being counted as FP registers and using
    up all of the FP hpysical registers.  The code in
    commit correctly identified FP registers so the
    bogus FP physical register usage was never cleared,
    locking up the machine.  This is why the SLAT didn't
    work correctly.  Added isa_traits::isFloatingPointRegister
    and ::isIntegerRegister to do this tracking in a
    machine-independent way.
sim/sim_events.cc:
    simple way to dump stats on specified cycles
sim/eventq.hh:
    Re-insert assignment of description string into event
sim/eventq.cc:
    If event is the head in remove() return
arch/alpha/fake_syscall.cc:
    Clustering changes....
    - clusters can share data using the ClusterSharedInfo structure
    - Pulled the register info file from the segmented IQ --> dispatch stage
    (this info can be used by the dispatch stage and any IQ model)
    - Segmented IQ's share the chain-info-table now
base/misc.hh:
    - Add m5_assert() macro to print the sim_cycle if the
    assert fails.

    - Add simple_trace, simple_trace_data and simple_trace_start
    parameters to generate a sim-safe-like trace for easy
    comparison with simplescalar results.  Needed for PISA
    debugging.
sim/sim_events.hh:
    remove extra space
sim/main.cc:
    Fix dump() for floss-reasons
    Segfault can now dump core
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Get rid of obsolete call from misguided thread scheduling experiment.
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
    add new alpha instructions for starting and ending intervals
dev/disk_image.cc:
dev/disk_image.hh:
    Make the copy-on-write disk image use hash_map
base/callback.hh:
    Generic callback class and callback queue for random use
sim/main.cc:
sim/sim_events.cc:
sim/sim_exit.hh:
    Move exit stuff into it's own file.  Make an exit callback queue so that
    generic callbacks can be invoked upon simulator exit
dev/disk_image.cc:
    give a mode that makes sense
dev/disk_image.cc:
dev/disk_image.hh:
    Rework the object implementation of the copy-on-write disk image.
    - Allow a child name and an initial table size to both be specified
    - Add a read only flag that determines if changes to the image are written
    back to disk.
    - If the flag is not read only, and there is no initial image to open, that's
    ok, just create an initial empty table.
    - If the table is to be written back to disk, schedule an ExitCallback to
    write the image back when the simulator exits.
base/callback.hh:
    make this work in g++ 3
base/misc.cc:
base/pollevent.cc:
base/pollevent.hh:
base/trace.hh:
sim/pc_event.cc:
sim/universe.cc:
    declare sim_cycle in one place
arch/alpha/alpha_memory.cc:
dev/alpha_console.cc:
    more sim_cycle cleanup
sim/eventq.hh:
    fix priority handling in the event queue:
    if an event is scheduled with a priority once, then don't overwrite the
    priority if it is subsequently scheduled without a priority
dev/console.cc:
    send a carriage return/newline pair to the output manually since cprintf
    and friends would interpret this and send out endl
dev/console.cc:
dev/console.hh:
    add option to save console output to a file
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Rework cache interface to avoid trying to loop inside of tick().
    Should work much more cleanly with timing memory now (even for
    multiprocessor systems).
sim/simple_cpu.cc:
    a whole bunch of cleanup foo
sim/eventq.cc:
    events can't be scheduled in the past anymore
sim/eventq.cc:
sim/eventq.hh:
    create doEventLoop(), this continually cycles through the event queue
    consuming events until there are none left
dev/console.hh:
    Make this work in g++ 3
sim/sim_events.cc:
sim/sim_events.hh:
    Make the act of ticking all cpus an event.  Automatically schedule it
    every cycle
sim/debug.cc:
sim/main.cc:
sim/sim_events.cc:
    rearrange code to get rid of sim_smt.cc
sim/main.cc:
    oops. bring back the SIM:cycle stat
arch/alpha/ev5.cc:
sim/simple_cpu.cc:
    move the break_ipl check to the point where the IPL is actually set
sim/debug.cc:
    Make the debug break event first in any given cycle
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Split I-cache and D-cache stall cycles out from idle cycles in statistics.
sim/prog.hh:
    - Replace SLAT maps with hash_maps

    - Add hash<> specializations for md_addr_t,
    counter_t, etc.

    - Increase max file descriptors from 15 to 100
    (parser00 was running out)
sim/simple_cpu.cc:
    A few baby steps toward full-system detailed CPU.
    ev5_trap() now sets both PC & NPC (not just NPC).
base/misc.cc:
base/trace.cc:
    New memory model
Doxyfile:

    Configuration file for doxygen. Generates documentation in /n/zizzer/z/m5docs.

    To generate docs, run "doxygen Doxyfile" in the root directory of your copy of the head.

    To comment your code you use a javadoc like syntax, a cstyle comment with 2 stars at the front (/**). For example

    /** Everything before the first period is a brief description. This is a detailed description.

    @param <name> description of parameter to function
    @retval <name/type> description of function return value.
    @sa (for see also) generate links to other class/enum/member/etc.
    */

    You should start your files out with a comment like:

    /** @file
    Brief description of the file.
    Detailed description if needed.
    */

    See TimingMemobj.hh for more examples.
dev/ethertap.cc:
    Make this work on OpenBSD
sim/main.cc:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
    Make it possible to set an exit code for the exit event.
    Also, make exit_now not visible to the rest of the simulator so that people
    will know to create an exit event.
    Finally, don't include callback.hh since we don't have to.
sim/sim_events.cc:
    use the SimExitEvent to make sure that we exit at the end of the cycle
arch/alpha/fake_syscall.cc:
    don't use exit_now() create a SimExitEvent()
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
    Add an instruction that causes M5 to exit, allowing processes running under
    simulation to cause the simulation to terminate
sim/simple_cpu.cc:
    in full system mode, don't panic on an unknown opcode
dev/disk_image.cc:
dev/disk_image.hh:
    convert stdio to streams
sim/system.cc:
    remove uneeded include
base/cprintf.cc:
    %p is an integer (more or less)
sim/system.cc:
sim/serialize.cc:
    missing include
dev/disk_image.cc:
    cast to correct types for proper interface usage
base/circlebuf.cc:
base/intmath.h:
base/remote_gdb.cc:
base/res_list.hh:
    In c++, we use std::min, std::max, true, and false, not ano of the other junk
sim/sim_events.cc:
    make a local copy of the data since the object can get deleted
dev/alpha_console.cc:
dev/alpha_console.hh:
    Added parameter for number of CPUs to console, defualt=1
sim/sim_events.cc:
sim/simple_cpu.cc:
sim/system.cc:
sim/system.hh:
    use cprintf.
    general cleanup
    remove unneeded c_str() calls.
base/cprintf.cc:
    make %% work
base/cprintf.cc:
    handle %% better
test/cprintftest.cc:
    better testing
arch/alpha/alpha_memory.cc:
    convert to use iostream and cprintf instead of stdio and fprintf
base/cprintf.cc:
    more accurately implement formatting for floating point numbers
test/cprintftest.cc:
    more tests
base/inifile.cc:
base/inifile.hh:
base/symtab.cc:
base/symtab.hh:
dev/disk_image.hh:
sim/base_cpu.cc:
test/Makefile:
    convert everything to use hash_map instead of my old hash table junk
base/hashmap.hh:
base/inifile.hh:
dev/disk_image.hh:
    since people don't agree on where hash_map belongs, pull it into the
    m5 namespace and include hashmap.hh whenever a hashtable is needed
sim/memtest.cc:
    Move Cache only calls (block_size, hit_latency, etc.) out of TimingMemObject and into CPUMemInterface. Changes to everywhere they were called on a TimingMemObj.
sim/param.hh:
    Fix handling of operator[] for EnumVectorParam classes.
    Also fix some line wrapping problems caused by adding 'std::'.
base/trace.cc:
base/trace.hh:
    Extend trace facility to either print immediately to an ostream or
    maintain a circular buffer of trace entries (dumpable from debugger
    by calling dumpTrace()).  Also change flags to use SimpleEnumVectorParam
    so we can just give a list of names instead of a big hex value.
sim/exetrace.cc:
sim/exetrace.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Integrate execution trace code into new trace facility.  Eliminates
    the need for a separate execution trace log.  Enable instruction tracing
    using --trace:flags=InstExec.
base/misc.cc:
    Dump trace buffer in panic().
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
sim/simple_cpu.cc:
    set up an annotations.hh file where inline annotation functions that do
    nothing exist.  This allows people to hack in annotations all in one file
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
    intervals are really annotations
arch/alpha/ev5.cc:
    Factor out more annotations
arch/alpha/ev5.cc:
sim/simple_cpu.cc:
    Make an Annotate namespace, and add a DumpStats method to it
dev/disk_image.cc:
sim/main.cc:
sim/sim_events.cc:
sim/sim_exit.hh:
    Normalize exit-related function names.
    Move exitNow() prototype to simexit.hh.
base/misc.cc:
base/trace.cc:
base/trace.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Minor cleanup on new tracing code:
    - namespace cleanup
    - fix bug in Trace::Log::dump
    - added new RawDumpRecord to put raw data in trace buffer
    (call Trace::rawDump, was Trace::dump)
    - added --trace:flags=All to set all trace flag bits
    - added --trace:dump_on_exit option to dump trace buffer on normal exit
    - DPRINTF now requires 'const char *' for format (not string) so it
    doesn't go away by the time buffer is dumped
sim/sat_counter.hh:
sim/serialize.hh:
    foo(void) --> foo()

    This commit is equivalent to doing the following in the sim directory:

    perl -pi -e 's/\(void\)/()/' *.cc *.hh
sim/base_cpu.hh:
sim/eventq.cc:
sim/hybrid_pred.cc:
sim/hybrid_pred.hh:
sim/memtest.cc:
sim/predictor.hh:
sim/sat_counter.cc:
sim/sat_counter.hh:
    Move dump() and reg_stats() implementations out of header files.
    Clean up #includes.
sim/exec_context.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/main.cc:
    Clean up identification and handling of prefetches and no-ops.
    Added is_data_prefettch() method to DynInst.  (One of these days
    we'll have to change all those functions to isFoo() style.)
    Changes nop count statistic... we were only counting Alpha UNOPs
    before, not all Alpha NOP forms.
sim/pc_event.cc:
sim/simple_cpu.cc:
    - Strip opt binaries after build

    - Update Makefile for new source files

    - Fix BHGP prefetcher to use compressed addresses

    - Fix FULL_SYSTEM compile problems (missing header includes)
base/inifile.cc:
    Make it possible to override variables in the inifile and on the command line
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    - Make the SLAT useable with SimpleCPU for quick
    and easy debugging.  This required refactoring some
    of the traits classes which should make them
    marginally more independent.

    - Fix bogus assert in the SLAT code.  Alias load/store
    values should only be assumed equivalent in non-spec mode.
sim/simple_cpu.cc:
    - Must send the saved address to the SLAT for all memory
    operations because execution could have overwritten
    the base register.
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Added Parameter for CPU identification number in Full System
    Primary CPU ID is 0, which is the default value
    Modified to start all CPU's in Halted status except the primary CPU
dev/alpha_console.cc:
    Added comments to code for needed implementation in order to boot second CPU
dev/alpha_console.cc:
sim/exec_context.cc:
sim/exec_context.hh:
sim/simple_cpu.cc:
sim/system.cc:
sim/system.hh:
    Added array of Execution Contexts to system.hh
    Used when trying to launch another CPU
    Added cpu_id to Full System ExecContext
    Fixed the launch in alpha_console.cc to access the correct exe_ctx
dev/alpha_console.cc:
sim/simple_cpu.cc:
    Fixed initializtion and launch of the second processor
    Added a gdb-alpha debug port for non-primary processor
    Cleaned up the .ini file of unneeded disk images
sim/simple_cpu.cc:
    Add cpu_id (see Ron's recent commit) to full-system detailed CPU.
base/trace.cc:
    Fix bug in calling dumpTrace() on partially filled trace buffer.
test/Makefile:
test/lru_test.cc:
    - Replace BHGP associative table with something
    simpler.

    - Add lru_test to test out new AssociativeTable
    class.
Doxyfile:
    Only create documentation for documnented classes
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
    cleanup and formatting
sim/simple_cpu.cc:
    Fix bus queueing delay and idle stats. Slight change to one scheduling case. Set req->time in SimpleCPU so delays are correctly computed.
sim/simple_cpu.cc:
    Don't do an icache fetch if we had an ITLB miss.
arch/alpha/alpha_memory.cc:
dev/alpha_console.cc:
sim/serialize.cc:
sim/serialize.hh:
    Replace include of inifile.hh in serialize.hh with forward decl
    of class IniFile.  Requires adding explicit include of inifile.hh
    in several .cc files.
sim/eventq.hh:
    Get rid of needless include of inifile.hh.
sim/main.cc:
base/inifile.cc:
base/inifile.hh:
    Check for unreferenced parameters to detect obsolete settings and
    typos.  A warning for an unreferenced parameter section can be
    suppressed by adding a 'unref_section_ok=y' parameter to the section.
    Warnings for any unreferenced parameters within a section can be
    suppressed by adding a 'unref_entries_ok=y' parameter to the section.
    (The value doesn't matter; the presence of the parameter is all that
    is tested.)

    By default any unreferenced parameter or parameter section warnings
    will cause the simulator to terminate.  Use the '-u' command-line
    option to suppress this behavior (at your own risk!).
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/pcireg.h:
dev/simple_disk.cc:
dev/simple_disk.hh:
sim/eventq.hh:
sim/serialize.hh:
sim/sim_object.hh:
    Add some Doxygen comments.  Mostly putting in markers for the file and classes
    Also some minor formatting fixes here and there
arch/alpha/ev5.cc:
    Reindent to 4 spaces (plus a few other very minor formatting changes).
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
    Reindent.
sim/eventq.hh:
    Don't even bother with the description unless TRACING_ON is defined.
    Not a big deal at this point, since TRACING_ON is currently hardcoded
    to 1 in base/trace.hh.
base/remote_gdb.cc:
base/trace.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/system.cc:
    Clarify debugging defines:
    - DEBUG is either defined or not, but is not given a value.  It should
    be tested with #ifdef.
    - TRACING_ON is always defined, either with a 0 or 1 value.  It should
    always be tested with #if.
    Automatically set TRACING_ON value according to whether DEBUG is defined.
    Added -Wundef to warnings to catch '#if DEBUG' cases.

    (Yes, '#if DEBUG' does the right thing if DEBUG is not defined, but the
    same is not true for '#ifdef TRACING_ON' if TRACING_ON is defined to 0.)

    In the long run, perhaps the uses of TRACING_ON outside of the trace
    package itself should be converted to use DEBUG.
sim/pc_event.cc:
    Looks like a lot of device code has never been compiled w/o TRACING_ON set;
    fix up several warnings (mostly unused variables).
sim/pc_event.cc:
    Oops... needs to compile w/o FULL_SYSTEM too.
base/trace.hh:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/sim_object.cc:
    Fix up parameter printing controls.  Parameters are always printed by
    default; new command-line parameter '-q' turns this off.  Old system
    was broken in two ways: there was no way to turn off printing in the
    optimized binary, and controlling printing with a trace flag bit (specified
    as an .ini parameter) meant that parameters parsed *before* trace:flags
    never got printed.

    Also added code to print the names of unspecified parameters as comments
    in the output.
base/remote_gdb.cc:
base/trace.hh:
    A couple more changes to get full-system to compile w/o tracing.
sim/simple_cpu.hh:
sim/simple_cpu.cc:
    - Add stats for simple SLAT profiling
sim/simple_cpu.cc:
    Extend HAVE_TSL protection so it can compile without TSL
base/trace.cc:
    Need to update flag strings to match enum... yuck.
sim/system.cc:
sim/system.hh:
    Build global list of system objects.
    Add gdb-callable printSystems() function so we can find system
    object pointers from inside debugger.
sim/eventq.cc:
sim/simple_cpu.cc:
base/pollevent.cc:
base/pollevent.hh:
    Move pollQueue handling into main event loop so it works regardless
    of the CPU model.
arch/alpha/ev5.cc:
    Protect IPRs etc. from being modified on misspeculated paths.
arch/alpha/ev5.hh:
    Eliminate some unused macros.
arch/alpha/alpha_memory.cc:
    Don't update IPRs for TLB misses on misspeculated instructions.
    Set req.flags PHYSICAL and UNCACHEABLE bits as appropriate
    based on results of translation.
sim/param.cc:
    Move ConfigHierarchy::Node definition into separate file so it can be
    included only where necessary.
arch/alpha/fake_syscall.cc:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/circlebuf.cc:
base/circlebuf.hh:
base/cprintf.hh:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/inifile.cc:
base/inifile.hh:
base/misc.hh:
base/mod_num.hh:
base/pollevent.cc:
base/remote_gdb.cc:
base/sched_list.hh:
base/socket.cc:
base/socket.hh:
base/str.cc:
base/str.hh:
base/symtab.cc:
dev/alpha_access.h:
dev/etherint.cc:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/debug.cc:
sim/hybrid_pred.cc:
sim/hybrid_pred.hh:
sim/param.cc:
sim/param.hh:
sim/pc_event.cc:
sim/predictor.hh:
sim/sat_counter.cc:
sim/sim_object.cc:
sim/simple_cpu.hh:
test/cprintftest.cc:
test/lru_test.cc:
test/nmtest.cc:
test/offtest.cc:
test/sized_test.cc:
test/symtest.cc:
util/tap/tap.cc:
    Add CVS Id tags
dev/alpha_console.cc:
dev/alpha_console.hh:
    Get rid of pmask field in MemReq; move address mask into devices
    by adding to common base class FunctionalMemory.
base/inifile.cc:
    Don't complain if "unref_section_ok" or "unref_entries_ok"
    are not referenced.
base/inifile.cc:
    Add functionality to "unref_entries_ok":
    Now, the RHS is parsed for a list of unreferenced entries, only these will be "OK"
    Note that this will not be needed very often...
base/trace.cc:
sim/exetrace.cc:
    Make trace cycle number position and format consistent between DPRINTF
    trace records and exetrace records.
sim/debug.cc:
    Add "debug" parameter context for global debug options.
    Add parameter "debug:break_cycles" to set DebugBreakEvent(s)
    from ini file/command line.
sim/pc_event.cc:
sim/system.hh:
    sched_break_pc() now sets a breakpoint on *all* systems.
    Use sched_break_pc_sys() to set a breakpoint on just one system.
sim/debug.cc:
sim/pc_event.cc:
base/cprintf_formats.hh:
    using namespace std
dev/alpha_console.cc:
sim/exec_context.cc:
sim/exec_context.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
arch/alpha/fake_syscall.cc:
sim/prog.cc:
    use accessor functions to set/get status to prepare to not call
    SimpleCPU::tick if there is nothing to do
sim/simple_cpu.cc:
    no more simplescalar here
base/trace.hh:
    Only set TRACING_ON according to DEBUG if it hasn't already been
    set on the command line.
base/trace.cc:
    If compiled with TRACING_ON=0, give an error if the user tries to
    turn on tracing.
sim/main.cc:
    Get rid of do-nothing segfault handler... if you get a segfault in an exit
    handler, you end up with an infinite recursion.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/pc_event.cc:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Full-system detailed CPU almost almost there.  Big reorganization of
    virtual address translation code, so we can tell an access is uncached
    soon enough to suppress it if it's on the wrong path: translation is its
    own step now, not hidden inside the (former) VirtualMemory object.
    Also a few other changes to avoid bad things on misspeculated paths.

    This commit results in *very* small changes in IPCs and MSIPCs (a
    few tenths of a percent max on the tests) because some wrong-path
    instructions get handled a little differently.
sim/main.cc:
    Put quotes around args with spaces when echoing command line.
sim/pc_event.cc:
    Process PC Events just before fetching the relevant instruction instead
    of just after the previous instruction.  Keeps us from missing events
    when we take off on misspeculated paths.

    ** Detailed CPU now gets to single-user prompt!! **
sim/base_cpu.hh:
sim/eventq.hh:
sim/main.cc:
sim/sim_events.cc:
sim/sim_events.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    get rid of the TickAllEvent and make it so each cpu has its own tick event.
    In the process, the implementation of the virtual functin tick() got moved
    into a non virtual function _tick() so that the tick event could be CPU
    specific and you wouldn't pay the virtual function call overhead.

    This is another step towards being able to not tick a cpu if it has nothing
    to do
sim/base_cpu.hh:
sim/simple_cpu.hh:
    Now that tick is called via an event, we no longer need a virtual function
sim/base_cpu.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    clean up the tick event stuff and get rid of the TickEvent template class
    and just make one for each class since you may want a different process()
    function anyway
base/trace.cc:
base/trace.hh:
sim/base_cpu.hh:
sim/pc_event.cc:
sim/pc_event.hh:
    Fix up branch predictor's return address stack when we do a SkipFuncEvent.
    Since there's no easy way to figure out what thread ID we're on from
    the SkipFuncEvent, we just fix thread 0's RAS... will need to fix this
    when we get SMT full-system up.

    Also:
    - Moved RAS tracing stuff to DPRINTFs; added BranchPredRAS trace flag.
    - Made BadAddrEvent derive from SkipFuncEvent to eliminate code duplication.
base/trace.cc:
sim/eventq.cc:
sim/eventq.hh:
sim/serialize.cc:
    Create a flags bitvector in the event to store flags.  Holds what used to be
    squashed and scheduled, and also contains a new flag for auto delete.

    The auto delete flag will make the eventq responsible for calling delete on
    an event.  This makes 'delete this' unnecessary in the process() function.
    This is most beneficial for events that get squashed since process() never
    gets called, and one might want to have the data reclaimed.

    To use the autodelete functionality with squash, a few events were cleaned up
    and reorganized
sim/exec_context.cc:
sim/exec_context.hh:
sim/pc_event.cc:
sim/simple_cpu.cc:
    Add thread_num field to ExecContext so it knows which CPU thread
    context it represents.  Need this for the SkipFuncEvent RAS fixup,
    but seems generally useful.
dev/etherdump.cc:
    use time.h instead of sys/time.h
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    move the tick schedule() to where it's needed
dev/alpha_console.cc:
dev/alpha_console.hh:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/intr_control.cc:
sim/intr_control.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    get rid of the processor SimObject and move all of the interrupt stuff into
    BaseCPU since it really is part of the CPU anyway
sim/exec_context.hh:
    fix store conditional
sim/exec_context.hh:
    clean up conditional store so that it's more understandable
sim/base_cpu.cc:
sim/base_cpu.hh:
    move interrupt set/clear routines into the .cc file and make them virtual
    so that CPUs derived from BaseCPU can modify the behaviour of the interrupt
    routine.
base/trace.cc:
base/trace.hh:
    New trace flags generation via perl script.  Now if you want to add a
    flag you just type it once (in the script) and all the C++ is generated
    automagically.  Also supports "compound" flags that can be specified
    on the command line and map to multiple regular flags.

    Switched trace flags from 64-bit bitmap to vector<bool> for scalability.
base/trace.cc:
    comment out the offending assign since it is commented as not needed
base/trace.cc:
    Get rid of useless code.
sim/base_cpu.cc:
sim/base_cpu.hh:
    change variable name to avoid confusion
arch/alpha/ev5.cc:
sim/simple_cpu.cc:
    Remove a bunch of istats stuff and insert some annotations for where they
    were.
sim/debug.cc:
    add a function to force stats to be dumped from the debugger
sim/base_cpu.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Don't schedule tickEvent until it is known that there will be something to do
test/Makefile:
    Make tests compile again
test/Makefile:
    Make the whole build process for tests a bit simpler
util/tap/Makefile:
    make this build again, clean stuff up
sim/exec_context.cc:
sim/simple_cpu.cc:
    make stuff compile when not FULL_SYSTEM
sim/main.cc:
    Add the name of the execution host to the output
sim/main.cc:
    Don't free() data returned by getenv.
    besides, free() is a function, not an operator like sizeof
sim/eventq.cc:
    That assertion should have never been committed
sim/simple_cpu.cc:
    don't tick here
sim/eventq.cc:
    the squashed flag should be cleared once the event has actually been processed
sim/simple_cpu.cc:
    we can get here with a dcache miss as well.
sim/simple_cpu.cc:
    only schedule the event if it is not already scheduled.
arch/alpha/fake_syscall.cc:
    Zero out syscall arg buffer to avoid copying garbage into simulator space.
sim/exec_context.hh:
    Translation in non fullsystem mode. And use the FALRU class to implement FA LRU caches.
sim/base_cpu.hh:
sim/exec_context.cc:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Reorganize code a bit so that multiple CPUs can properly work with the
    new tick as event stuff.
arch/alpha/arguments.hh:
base/cprintf.hh:
base/refcnt.hh:
dev/etherpkt.hh:
    Make a refcounted base class that contains the refcounting stuff and make
    everything use it
sim/main.cc:
    don't print out the host if we didn't find one
dev/alpha_console.cc:
dev/alpha_console.hh:
    s/memreq/MemReq/
base/trace.cc:
    Add support to echo trace output (DPRINTF etc.) to cerr as well as
    the trace buffer.  From gdb, call "echoTrace(1)" to enable, or
    "echoTrace(0)" to disable.  As a side effect, semantics of setting
    both trace:bufsize and trace:file are different now (will buffer
    and send to file, where old version would just buffer), but I doubt
    anyone ever did that anyway.  See comments in file for more details.
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/debug.cc:
sim/eventq.cc:
sim/eventq.hh:
sim/memtest.cc:
sim/memtest.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Revamp event debug/tracing structure.
    - virtual const char *description() method replaces description string
    constructor argument.  Lets us associate a fixed description string
    with each class of events with basically no overhead.
    - virtual void trace(char *action) method lets event subclasses
    customize tracing DPRINTF call to put in additional information.
    Currently only used by WritebackEvent (to print sequence number
    of associated instruction).
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.hh:
    Fix up full-system events for new debug structure.
base/trace.cc:
    Looks like g++ 3 doesn't like "string = bool ? string : char*".
sim/simple_cpu.cc:
    the caches currently won't completion events for UNCACHEABLE accesses, so
    don't send any.
    Warning, this is a HACK!
dev/etherdump.cc:
sim/main.cc:
    cleanup includes, and remove some #ifdef cruft for BFD
sim/sim_exit.hh:
    Added GDB-callable exitNow() using char *
sim/sim_events.hh:
    Need to include eventq.hh here.
test/Makefile:
    There are no OPT_FLAGS
arch/alpha/fake_syscall.cc:
dev/etherdump.cc:
sim/eventq.cc:
sim/main.cc:
sim/memtest.cc:
sim/serialize.cc:
sim/sim_events.cc:
sim/sim_time.hh:
sim/simple_cpu.cc:
sim/system.cc:
    Get rid of sim.h & sim_smt.hh.  Most of what was in those was obsolete anyway.
    Move needed externs into universe.hh & stats.hh, plus new header file
    sim_time.hh.
sim/memtest.cc:
sim/memtest.hh:
    Update memtest cpu to new tickEvent stuff
base/remote_gdb.cc:
    Adding returns to make insure happy.
sim/simple_cpu.cc:
    Rework Interporcessor Interrupts to properly signal second CPU, and unsuspend it
sim/intr_control.hh:
    Fix clock interrupt to signal both proccesors correctly in MP system
sim/system.cc:
    Fix seg fault in single proccesor mode from last commit, MP now boots with 2 CPUs
sim/simple_cpu.cc:
sim/system.cc:
sim/system.hh:
    Changes to genaralize the interupt scheme to variable number of proccessors
base/misc.cc:
    only dump the trace buffer if tracing is turned on
base/str.cc:
    properly deal with the case where there is only one string in the list
base/cprintf.cc:
base/cprintf.hh:
    Add csprintf() to print to a string (sort of like sprintf())
base/cprintf.cc:
    be consistent about resetting parameters to original values
base/cprintf.cc:
    cleanup
base/statistics.cc:
base/statistics.hh:
    Finally commit my new stats package and stop tinkering with it.

    This new stats package has support for all sorts of stuff.
    Documentation will appear in the code in a future commit.
test/Makefile:
test/stattest.cc:
    add tests for the statistics package.  This exercises all sorts of different
    capabilities of the stats package and can be used for examples.
util/rundiff:
    rundiff utility
    Normal diff reads in all of both input files and tries to generate a minimal
    diff, for super long trace files, this is bad because it takes forever and
    you run out of memory.  rundiff is designed to scan the input files and
    compare only 2000 lines at a time.  This way memory won't run out and a user
    can use fifos for input files.
sim/exetrace.cc:
    Print all reg results as 0x%016x.
arch/alpha/fake_syscall.cc:
base/misc.cc:
base/misc.hh:
base/pollevent.cc:
base/pollevent.hh:
base/statistics.hh:
base/trace.cc:
base/trace.hh:
dev/alpha_console.cc:
dev/etherbus.cc:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/debug.cc:
sim/eventq.cc:
sim/eventq.hh:
sim/exec_context.hh:
sim/exetrace.hh:
sim/hybrid_pred.hh:
sim/main.cc:
sim/memtest.cc:
sim/memtest.hh:
sim/pc_event.cc:
sim/prog.hh:
sim/sat_counter.hh:
sim/serialize.cc:
sim/sim_events.cc:
sim/sim_events.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/universe.cc:
test/nmtest.cc:
test/stattest.cc:
test/symtest.cc:
    Global variable renaming.  Basically equivalent to the following perl:

    s/\btick_t\b/Tick/g;
    s/\bsim_cycle\b/curTick/g;
    s/\bcounter_t\b/Counter/g;
    s/\bsim_freq\b/ticksPerSecond/g;
dev/console.cc:
dev/etherbus.cc:
dev/etherdump.cc:
dev/etherlink.cc:
dev/ethertap.cc:
    Get rid of some explicit externs (use header files!).
dev/ethertap.cc:
    Include for panic().
arch/alpha/alpha_memory.cc:
sim/exec_context.hh:
    Various bug fixes. Charge all writebacks to thread 0
sim/eventq.cc:
sim/eventq.hh:
sim/main.cc:
    rework the event loop a bit so that we can prepare for dealing with
    asynchronous events properly.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
base/refcnt.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
sim/exec_context.hh:
sim/memtest.cc:
sim/memtest.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Initial move to reference counting MemReq objects. Switched to STL containers for storage in the memory hierarchy.
sim/exec_context.hh:
    Fix LL/SC and got 1-6 CPUs working by fixing clock interrupt
sim/simple_cpu.cc:
    Add the IIC as a selectable cache tag. Fix translation for now with a quick hack.
sim/exec_context.hh:
    Put detection logic on failed Store Conditionals to help detect deadlock situations
util/term/Makefile:
util/term/term.c:
    Whittle down netcat to the bare minimum to connect to another machine
    and add the proper stuff to do some terminal handling to make this utility
    sufficient for connecting to m5 to get a console
util/term/Makefile:
    add an install target
base/pollevent.cc:
sim/async.hh:
sim/main.cc:
    Don't create events in signal handlers since it really isn't safe.  I'm not
    positive if some bugs I've seen were caused by this, but we may as well
    be safe
base/pollevent.cc:
base/pollevent.hh:
dev/console.cc:
dev/console.hh:
sim/async.hh:
sim/main.cc:
    - clean up the pollevent stuff and just do the poll whenever requested since
    we will request it with the proper frequency
    - add an alarm to poll once every second in addition to waiting for sigio

    - remove all of the telnet crap since I'm never planning on implementing it
    - fix detaching and re-attaching of consoles
base/pollevent.cc:
base/pollevent.hh:
sim/main.cc:
    only handle/raise SIGALRM if we're polling
sim/memtest.cc:
sim/cache/lzss_compression.hh:
sim/cache/null_compression.hh:
    Initial check in of Compression stuff and IIC subblocking.
base/remote_gdb.cc:
    Get rid of needless extern.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/fake_syscall.cc:
dev/alpha_console.cc:
dev/alpha_console.hh:
sim/exec_context.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Rename fault type and fault codes as follows:
    s/md_fault_type/Fault/g;
    s/md_fault_none/No_Fault/g;
    s/md_fault_mcheck/Machine_Check_Fault/g;
    s/md_fault_opdec/Unimplemented_Opcode_Fault/g;
    s/md_fault_alignment/Alignment_Fault/g;
    s/md_fault_overflow/Integer_Overflow_Fault/g;
    s/md_fault_reset/Reset_Fault/g;
    s/md_fault_arith/Arithmetic_Fault/g;
    s/md_fault_interrupt/Interrupt_Fault/g;
    s/md_fault_ndtb_miss/Ndtb_Miss_Fault/g;
    s/md_fault_pdtb_miss/Pdtb_Miss_Fault/g;
    s/md_fault_dtb_fault/Dtb_Fault_Fault/g;
    s/md_fault_dtb_acv/Dtb_Acv_Fault/g;
    s/md_fault_itb_miss/Itb_Miss_Fault/g;
    s/md_fault_itb_fault/Itb_Fault_Fault/g;
    s/md_fault_itb_acv/Itb_Acv_Fault/g;
    s/md_fault_fen/Fen_Fault/g;
    s/md_fault_pal/Pal_Fault/g;
    s/md_fault_NUM/Num_Faults/g;

    Also changed 'enum md_fault_type' to just 'Fault' where possible.
sim/exec_context.cc:
sim/exec_context.hh:
    Add a constructor to specify a memory without a process
sim/eventq.hh:
    clean up a bit.
    When events are resecheduled or removed from the schedule, they are no longer
    squashed.  (Only scheduled events can be squashed.)
sim/simple_cpu.hh:
    check to see if the tick event was squashed.  If it was squashed, then it must
    be rescheduled since squashed events are scheduled.
sim/exec_context.cc:
sim/exec_context.hh:
    This new constructor is only for non FULL_SYSTEM
base/statistics.cc:
base/statistics.hh:
test/stattest.cc:
    Remove unused variable
    dumpStats -> dump
    initStats -> init
    use const string & instead of const char *
    make Base constructor explicit
    more consistent formatting widths
sim/main.cc:
sim/sim_events.cc:
    make the new stats package useable in the simulator
base/statistics.cc:
base/statistics.hh:
test/stattest.cc:
    create two standard stats that are to be used for calculations:
    elapsedTicks - is the number of ticks that has elapsed during this
    simulation.  Currently, this is just curTick, but this may change when
    we have checkpointing.
    elapsedSeconds - is the number of simulated seconds that have elapsed during
    the simulation.  Currently, this is just elapsedTicks / ticksPerSecond.
sim/main.cc:
    Need to initialize stats much sooner so that SimObject constructors can
    register statistics
base/statistics.cc:
    - use the stat_print_descriptions variable that the old stats package provides
    this is just a quick hack for now.  When the old stats package goes away,
    we'll move this.
    - Fix the sorting algorithm so it works as I had intended
    - Make the output field widths equivalent to the old stats package
base/statistics.cc:
    clean up memory
sim/sim_events.cc:
sim/sim_events.hh:
    Use autodelete
sim/sim_events.cc:
    oops.  didn't mean to commit this part
util/tap/Makefile:
    call it m5tap instead of ethertap
sim/exec_context.hh:
    Get rid of a couple of unnecessary forward class declarations.
sim/memtest.cc:
sim/memtest.hh:
    Adds compression to the memory hierarchy as well as using ExecContext to access memory. Added a few related config files.
base/cprintf.cc:
    Default fill char is space, regardless of what stream fill char is.
sim/exetrace.cc:
    Convert some of the hairier format things to ccprintf.
base/statistics.cc:
    try getting the sorting a bit better
arch/alpha/arguments.hh:
base/refcnt.hh:
base/statistics.hh:
dev/etherpkt.hh:
    s/refcounted/RefCounted/
    s/refcnt/RefCountingPtr/
arch/alpha/fake_syscall.cc:
    Zero out register files for newly created threads to make non-full-system
    MP runs deterministic.
sim/exetrace.cc:
    Don't trace the results of NOPs or prefetches (for easier comparison
    with traces from new decoder).
sim/exetrace.cc:
    Don't trace branch link values written back to R31 either.
    Also put a ifdef TARGET_ALPHA around this hack.
sim/exetrace.cc:
    Need another ifdef TARGET_ALPHA...
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/arguments.cc:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/fake_syscall.cc:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/object_file.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/symtab.cc:
base/symtab.hh:
dev/alpha_console.cc:
dev/simple_disk.cc:
dev/simple_disk.hh:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/exetrace.hh:
sim/memtest.cc:
sim/memtest.hh:
sim/pc_event.cc:
sim/pc_event.hh:
sim/prog.cc:
sim/prog.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/system.cc:
sim/system.hh:
test/nmtest.cc:
test/symtest.cc:
    Massive renaming to (almost) eliminate all md_* and MD_* names
    in preparation for total exorcism of machine.def.

    Most of the changes in this commit were performed with the
    following perl script (perl -pi <script> <files>).  A small
    amount of manual fixup was needed to (mostly getting rid of
    the Addr typedefs in the various memory objects now that
    the former md_addr_t has that name).

    # rename machine-dependent types and constants (will be moving into ISA traits object)
    s/md_addr_t/Addr/g;
    s/md_intreg_t/IntReg/g;
    s/md_gpr_t/IntRegFile/g;
    s/md_fpreg_t/FloatReg/g;
    s/md_fpr_t/FloatRegFile/g;
    s/md_ctrlreg_t/MiscReg/g;
    s/md_ctrl_t/MiscRegFile/g;
    s/md_ipr_t/InternalProcReg/g;
    s/md_anyreg_t/AnyReg/g;
    s/md_inst_t/MachInst/g;
    s/regs_t/RegFile/g;
    # manually fix declaration in old/regs.h and a few forward decls
    s/struct RegFile/RegFile/g;
    s/MD_NUM_IREGS/NumIntRegs/g;
    s/MD_NUM_FREGS/NumFloatRegs/g;
    s/MD_NUM_CREGS/NumMiscRegs/g;
    s/MD_IPR_NUM/NumInternalProcRegs/g;
    s/MD_TOTAL_REGS/TotalNumRegs/g;
    s/MD_REG_ZERO/ZeroReg/g;
base/statistics.hh:
test/stattest.cc:
    Create a functor() wrapper for the stats package.  This wrapper makes it
    possible to write an actual function or functor that is evaluated in a
    Formula
base/statistics.hh:
test/stattest.cc:
    Implement operator += for formulas.  This allows us to build a formula without
    knowing all variables involved at compile time
sim/sim_object.cc:
sim/sim_object.hh:
    Make a different regStats pass for the new stats package
base/statistics.cc:
base/statistics.hh:
sim/main.cc:
    Move simulator specific stuff to its own file.
    rename elapsedFoo to simFoo so it's clear we're talking about what's been
    simulated.
    Use the functor method to get the time.
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/main.cc:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Convert instruction counting to new stats package.
    Convert the rest of SimpleCPU to new stats
    Do a bit of cleanup while we're at it
base/cprintf.cc:
    attempt to deal with the badbit problem
sim/base_cpu.hh:
sim/simple_cpu.cc:
    no need for reg_stats to be pure virtual
base/statistics.cc:
base/statistics.hh:
sim/simple_cpu.hh:
test/stattest.cc:
    change names of stat classes so they are simpler
base/statistics.cc:
    no unregestering stats
base/statistics.cc:
base/statistics.hh:
sim/main.cc:
test/stattest.cc:
    make it so that none of the constructors for the various stats objects
    take any parameters so that users may put them in arrays and stuff.  Instead
    provide initialization functions for the objects that needed parameters, and
    provide a way to verify that all statistics that need initialization do
    get initialized.
sim/cache/lzss_compression.hh:
    Compression fixes. Added trivial data support to the IIC. Set the max write size in the compressed memory to 1024 bytes
sim/memtest.cc:
sim/memtest.hh:
    Added 'percent_uncacheable' option to MemTest
base/statistics.cc:
base/statistics.hh:
    keep track of more data in distributions
    use a struct to pass data to the display function
    take underflow and overflow out of the array
base/statistics.cc:
    support for printing vector totals
sim/memtest.cc:
sim/memtest.hh:
    Fix uncacheables to go to their own memory space.
sim/memtest.cc:
    Change default percentage of uncacheables to 10%
base/statistics.cc:
base/statistics.hh:
    Correctly calculate vector totals.

    When a formula operates on vectors, it is incorrect to do calculate
    the formula for each vector element, and then sum the final formula
    vector.  The correct way is to sum the individual vectors at the leaves
    of the expression tree.  And then perform the calculation as if it were
    on scalar values.

    Assume we have vectors A, and B, and X = A * B
    The old way would have been: total(X) = total(A * B)
    The new way is total(X) = total(A) * total(B)

    Per thread miss rates are and example of something that would be calculated
    incorrectly.  If you were to sum all of the miss rates, you could get
    a number greater than one.  Calculating the overall miss rate should
    just be overall misses / overall accesses
base/statistics.cc:
base/statistics.hh:
    Create a #define STAT_DISPLAY_COMPAT that makes the new stat package output
    match the old one.
arch/isa_parser.py:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/arguments.cc:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/fake_syscall.cc:
arch/alpha/isa_desc:
arch/alpha/isa_traits.hh:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/bitfield.hh:
base/circlebuf.hh:
base/object_file.hh:
base/remote_gdb.cc:
base/symtab.hh:
dev/alpha_console.cc:
dev/console.cc:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/main.cc:
sim/op_class.hh:
sim/pc_event.cc:
sim/pc_event.hh:
sim/prog.cc:
sim/prog.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/static_inst.cc:
sim/static_inst.hh:
sim/system.cc:
sim/system.hh:
    New ISA description system.  No more machine.def!
    Instructions are now decoded into StaticInst objects, and all static
    instruction properties (including execution behavior) are associated
    with those objects.  Extended documentation in progress.
    Currently supports Alpha only; PISA will not compile.
    Use END_OF_MACHINE_DOT_DEF tag to extract previous version.
arch/isa_parser.py:
    Make it more obvious that you shouldn't edit decoder.cc, and
    harder to do so accidentally.
arch/alpha/isa_desc:
base/statistics.cc:
sim/exec_context.hh:
    make stuff compile in g++ 3.x
    fix some bad formatting
Doxyfile:
    Put generated docs in local directory docs/doxygen.
    Don't bother generating LaTeX, and a few other minor tweaks.
arch/isa_parser.py:
arch/alpha/isa_desc:
    - Decouple isa_desc operand types from C++ types.
    - Handle signed operand writebacks.
    - Add a few comments to suppress doxygen warnings on decoder.cc.
sim/static_inst.cc:
sim/static_inst.hh:
    Add some basic decode cache hash-table stats dumping (ifdef'd out).
sim/static_inst.cc:
    Make it compile w/gcc3.
sim/static_inst.cc:
    ostream doesn't seem to exist in 2.95
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
    TLB statistics
arch/alpha/ev5.cc:
    always pass the execution context to an annotation
arch/alpha/ev5.cc:
    revert a bunch of crap from the last commit that I didn't want yet.
arch/isa_parser.py:
    make it so that the ext source directory is grabbed from the right place
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/isa_desc:
arch/alpha/vtophys.cc:
base/remote_gdb.cc:
dev/alpha_console.cc:
sim/exec_context.hh:
sim/simple_cpu.cc:
    get rid of MD_IPR_foo and call it IPR_foo
    add some comments to describe what the various PALtemp registers do
    formatting
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/simple_cpu.cc:
    Keep a list of execution contexts in BaseCPU
    Provide a mechanism to register per execution context statistics.
base/socket.cc:
base/remote_gdb.cc:
dev/console.cc:
dev/ethertap.cc:
    don't panic if accept fails
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    keep track of fraction of cycles that are idle
base/statistics.hh:
    make proxy nodes work better in formulas.  (Now totals should work).
sim/op_class.hh:
    Document OpClass enum.
sim/op_class.hh:
    Need to document file for file members (enum, globals, etc.) to be extracted
arch/alpha/faults.cc:
arch/alpha/faults.hh:
arch/alpha/isa_traits.hh:
    Move Fault into its own file, and provide a function to get the string name
    of a fault
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/osfpal.cc:
arch/alpha/osfpal.hh:
    move PAL code defines and such into their own file.  Also provide a function
    to get the name of a PAL code
arch/alpha/osfpal.cc:
    make this actually compile and add it to the makefile
kern/tru64/tru64.hh:
    dummy class for differentiating Tru64
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
    Stuff on tru64 system calls
arch/alpha/ev5.cc:
arch/alpha/isa_desc:
sim/exec_context.cc:
sim/exec_context.hh:
    Add a bunch of full system statistics
base/statistics.cc:
base/statistics.hh:
sim/sim_events.cc:
    support for printing stats to a file.  For now we will continue to print
    to standard out so that the whole regression thing doesn't break.
    While we're at it, move the Stat param context to the new stats package
sim/exec_context.hh:
sim/main.cc:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
    Today saw the wholesale slaughter of greened's code. When we asked the accused, Erik Hallnor, why he did it he responded, 'Because I was bored. And the underlying prefetch cache was soon to be 2 generations out of date.'
sim/base_cpu.hh:
sim/exec_context.cc:
    added a std::vector and using namespace std
arch/alpha/fake_syscall.cc:
    Avoid conflicts with #defines in headers
arch/alpha/fake_syscall.cc:
    I think this is what steve had in mind.
base/endian.hh:
    get rid of the simplescalar endianness junk and make it a bit simpler
base/cprintf.cc:
base/cprintf.hh:
base/cprintf_formats.hh:
base/statistics.cc:
test/cprintftest.cc:
    Break out the cprintf formatting stuff into per-type formatting so that we
    can do special formatting based on type.  This makes %c work correctly for
    integer types.  It also allows me to add a workaround for string format widths.
    Finally, it allows me to accept stringstream directly as an argument without
    having to use the .str() member.
Doxyfile:
    Update Doxyfile to new version of doxygen and to use the newly install graphviz package.
Doxyfile:
    Remove . from the file paths, instead of ..
base/cprintf.cc:
base/cprintf_formats.hh:
base/statistics.cc:
test/cprintftest.cc:
    Fix printing of strings.  Seems that I just can't do what I want with
    templates.  They're too smart for they're own good.

    Fix format field widths for floating point numbers.

    Remove some .str()'s that are no longer needed because cprintf supports them.
base/statistics.cc:
base/statistics.hh:
test/stattest.cc:
    Make internal design a bit more consistent.
    Re-work Bins and Vectors and how they work together to remove a level
    of indirection.
base/statistics.cc:
base/statistics.hh:
    revert that last change
base/statistics.cc:
base/statistics.hh:
test/stattest.cc:
    let's try this again.  This time we'll make DistStat classes initialize
    their bins.
    Also add a test for this
base/statistics.hh:
    Proxy -> VectorProxy
Doxyfile:
    Don't hide undocumented classes. This helps when tracking includes through the new graphs.
Doxyfile:
    Make things run faster until documentation errors are gone
sim/prog.cc:
sim/simple_cpu.cc:
    Change declarations to match defenitions.
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/pcireg.h:
dev/simple_disk.cc:
dev/simple_disk.hh:
sim/eventq.hh:
sim/serialize.hh:
sim/sim_object.hh:
sim/simple_cpu.cc:
    Removal of 1200 doxygen warnings. The 600 left are mostly from StaticInstBase and decoder.cc. I basically un-documented the partially documented code by changing /** to /*.
arch/alpha/ev5.cc:
    Add FULL_SYSTEM protection to match header file.
Doxyfile:
dev/alpha_console.hh:
dev/etherint.hh:
dev/simple_disk.hh:
sim/simple_cpu.cc:
sim/static_inst.hh:
sim/cache/null_compression.hh:
    Down to 464 warnings, all in static_inst.hh or decoder.cc. Punt on the template instantiation thing by making them invisible to doxygen.
arch/alpha/alpha_memory.cc:
base/statistics.cc:
base/statistics.hh:
sim/simple_cpu.cc:
test/stattest.cc:
    New way of specifying information about printing stats.
    old way:
    stat.setFormat(name, ...);
    new way:
    stat
    .name(...)
    .desc(...)
    .prereq(...)
    .
    .
    ;

    This allows you to specify any information about the stats, and do it in any
    order.  It also cleans up the kinda crufty setFormat interfaces.
LICENSE:
    This is the M5 license as agreed upon by the original M5 authors, and blessed
    by the University of Michigan technology transfer office.

    OK by Doug Hockstad <dhocksta@umich.edu>
base/statistics.hh:
    missing_math is only for stats, so move it into its own place
base/statistics.cc:
test/stattest.cc:
    Fix stats sorting
base/statistics.cc:
base/statistics.hh:
test/stattest.cc:
    Fix description printing stuff.  Add a flag to the test script to turn
    descriptions on/off
base/str.hh:
    wrapper to convert values to strings via stringstream
base/statistics.hh:
    nitpick
base/statistics.cc:
base/statistics.hh:
test/stattest.cc:
    Rework the printing of statistics to make the PrintOne function not need
    to know about the stats themselves.  Also remove the overloading of function
    names for getting and setting parameters.
base/statistics.cc:
    duh
base/statistics.cc:
    Changes for _name issues
base/statistics.cc:
base/statistics.hh:
    Reorganize the base Stat class a bit and clean up handling of data
base/statistics.cc:
base/statistics.hh:
    Rework the stat printing stuff a bit so that the formatting parts need to know
    as little as possible about the type of stat being printed.
base/statistics.hh:
    maybe not all vector stats will be registered in the future.  (VectorProxies)
base/statistics.hh:
test/stattest.cc:
    VectorDistribution stat.  To be used for per-thread distributions.  Still need
    to implement total and zero()
arch/alpha/isa_traits.hh:
sim/static_inst.hh:
    don't use stdint.h, use either inttypes.h or host.h
sim/main.cc:
    unneeded
arch/alpha/isa_desc:
    only linux seems to support the rounding mode stuff right now
base/statistics.hh:
test/stattest.cc:
    VectorStandardDeviation and VectorAverageDeviation
base/statistics.cc:
    just make sure the size is correct
base/statistics.hh:
    use pointers internally instead of references
arch/alpha/faults.cc:
base/bitfield.hh:
sim/cache/lzss_compression.hh:
sim/cache/null_compression.hh:
sim/op_class.hh:
sim/sim_time.hh:
sim/static_inst.cc:
sim/static_inst.hh:
test/stattest.cc:
    consistent $Id$ tags
test/bitvectest.cc:
test/circletest.cc:
test/cprintftest.cc:
test/initest.cc:
test/lru_test.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/sized_test.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
arch/isa_parser.py:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/isa_parser.py:
arch/alpha/faults.cc:
arch/alpha/faults.hh:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/osfpal.hh:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
util/tap/tap.cc:
base/bitfield.hh:
base/callback.hh:
base/circlebuf.cc:
base/circlebuf.hh:
base/cprintf.cc:
base/cprintf.hh:
base/cprintf_formats.hh:
base/date.cc:
base/dbl_list.hh:
base/endian.hh:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/hashmap.hh:
base/inet.cc:
base/inet.hh:
base/inifile.cc:
base/inifile.hh:
base/intmath.cc:
base/intmath.h:
base/misc.cc:
base/misc.hh:
base/mod_num.hh:
base/object_file.cc:
base/object_file.hh:
base/pollevent.cc:
base/pollevent.hh:
base/range.hh:
base/refcnt.hh:
base/remote_gdb.hh:
base/res_list.hh:
base/sched_list.hh:
base/socket.cc:
base/socket.hh:
base/statistics.cc:
base/statistics.hh:
base/str.cc:
base/str.hh:
base/symtab.cc:
base/symtab.hh:
base/trace.cc:
base/trace.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/pcireg.h:
dev/simple_disk.cc:
dev/simple_disk.hh:
kern/tru64/tru64.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
sim/cache/null_compression.hh:
sim/async.hh:
sim/debug.cc:
sim/debug.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/intr_control.cc:
sim/intr_control.hh:
sim/memtest.cc:
sim/memtest.hh:
sim/op_class.hh:
sim/param.cc:
sim/param.hh:
sim/pc_event.cc:
sim/pc_event.hh:
sim/predictor.hh:
sim/sat_counter.cc:
sim/sat_counter.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/sim_time.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/static_inst.cc:
sim/static_inst.hh:
sim/std_types.hh:
sim/system.cc:
sim/system.hh:
sim/universe.cc:
sim/exec_context.cc:
sim/exec_context.hh:
    license
base/date.cc:
    move
test/stattest.cc:
    remove dave's scary container stuff
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/simple_cpu.cc:
    rename the exec context list xc to contexts
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/fake_syscall.cc:
dev/alpha_console.cc:
sim/exec_context.hh:
sim/memtest.cc:
sim/prog.cc:
sim/prog.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/system.cc:
sim/system.hh:
    s/exe_ctx/xc/g
sim/base_cpu.cc:
    Can't assume that context[0] exists.
sim/cache/lzss_compression.cc:
sim/cache/lzss_compression.hh:
    Our compression code free and clear.
arch/alpha/fake_syscall.cc:
base/range.hh:
base/statistics.hh:
sim/param.cc:
sim/sim_object.cc:
    Changes to build with g++-3.3.  Mostly added a bunch of includes of
    assert.h (not sure why older versions didn't need this).  Also fixed
    up a couple other new warnings.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/ev5.cc:
arch/alpha/fake_syscall.cc:
arch/alpha/isa_traits.hh:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/etherdump.cc:
dev/simple_disk.cc:
sim/simple_cpu.cc:
sim/system.cc:
sim/system.hh:
    a little style
sim/eventq.cc:
sim/main.cc:
sim/prog.cc:
sim/simple_cpu.cc:
sim/smt.hh:
    smt.h -> smt.hh
    add license
base/statistics.hh:
    missing_math.hh isn't really needed I guess
arch/alpha/arguments.hh:
arch/alpha/fake_syscall.cc:
arch/alpha/isa_traits.hh:
base/hashmap.hh:
base/inet.cc:
base/inet.hh:
base/misc.cc:
base/pollevent.cc:
base/socket.cc:
base/statistics.hh:
base/symtab.cc:
base/symtab.hh:
base/trace.hh:
dev/alpha_console.hh:
dev/etherlink.hh:
dev/etherpkt.hh:
sim/eventq.hh:
sim/exec_context.hh:
sim/exetrace.hh:
sim/host.hh:
sim/main.cc:
sim/param.hh:
sim/serialize.hh:
sim/sim_object.cc:
sim/simple_cpu.cc:
sim/static_inst.hh:
sim/universe.cc:
test/stattest.cc:
    Get rid of simplescalar host.h file and create our own host.hh file that has
    less junk.  (with our license.)  While we're at it, we consolidate all of
    the hashtable junk into one file hashmap.hh.  (use this file if you need a
    hash_map.)
Doxyfile:
    Avoid infinite recursion on build/src link.
arch/alpha/isa_desc:
sim/static_inst.hh:
    Add comments to get rid of doxygen warnings (and occasionally, as an
    accidental side effect, make the code more maintainable).
Doxyfile:
    Turn off information messages and route error messages to stderr.
arch/isa_parser.py:
arch/alpha/isa_desc:
sim/static_inst.hh:
    - Add some comments clarifying the semantics of StaticInst flags.
    - Make minor tweaks to the ISA description code to make corner cases
    consistent with the above comments :-).
    - Get rid of insn_counting code... instruction mix doesn't really change
    through the pipeline, and the overall mix can already be derived from
    existing stats.  Plus it keeps changing when the ISA flags change
    even though the pipeline doesn't care.
sim/hybrid_pred.cc:
sim/hybrid_pred.hh:
    So said Steve Raasch:xi
    "I know that the following files should be under our license"
base/fast_alloc.cc:
base/fast_alloc.hh:
    David Wood said I could have my own code back :-).
sim/sim_object.cc:
sim/sim_object.hh:
    create a regFormulas pass that will go AFTER the regStats pass.
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/debug.cc:
sim/eventq.cc:
sim/exec_context.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/hybrid_pred.cc:
sim/hybrid_pred.hh:
sim/intr_control.hh:
sim/main.cc:
sim/memtest.cc:
sim/memtest.hh:
sim/op_class.hh:
sim/param.cc:
sim/param.hh:
sim/pc_event.hh:
sim/predictor.hh:
sim/prog.cc:
sim/prog.hh:
sim/sat_counter.cc:
sim/sat_counter.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_object.hh:
sim/sim_time.hh:
sim/simple_cpu.hh:
sim/smt.hh:
sim/static_inst.cc:
sim/static_inst.hh:
sim/std_types.hh:
sim/system.cc:
    style police
base/statistics.cc:
base/statistics.hh:
test/stattest.cc:
    initial cut at a 2d vector stat
base/statistics.cc:
base/statistics.hh:
    Added a std:: and removed an unused bool
arch/alpha/fake_syscall.cc:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/prog.cc:
sim/prog.hh:
    Steve Reinhardt says "I wrote these myself from scratch"
base/date.cc:
    I probably changed this to a string in the first place, but it should be
    a const char *
sim/main.cc:
    make this compile again
base/random.cc:
base/random.hh:
sim/main.cc:
    Get rid of the Simplescalar random number junk.
    Since I didn't realize that we didn't even use it until after I wrote a
    simple replacement, I figure I'll commit the replacement in case we ever
    need it.
base/str.hh:
sim/main.cc:
    quote may be more generally useful
sim/main.cc:
sim/sim_object.cc:
sim/sim_object.hh:
    Make the old stats package a bit more self contained to prepare for
    future extrication
sim/main.cc:
sim/sim_time.cc:
sim/sim_time.hh:
    consolidate all of the time handling stuff
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/main.cc:
sim/smt.hh:
    instead of initializing max_threads_per_cpu in main(), we turn it into
    a static function and initialize it upon the first call

    Users of this should beware that all CPUs must be built before this function
    can be used.
sim/main.cc:
sim/universe.cc:
    sim_running_systems makes more sense in universe.cc
sim/main.cc:
    this is not a simplescalar file, use our copyright
    say that the simulator is M5 and display our copyright
    cleanup
    change a few things here and there to use our style
    use endl instead of "\n"  (for future portablility)
sim/async.hh:
sim/main.cc:
sim/system.cc:
sim/system.hh:
sim/universe.cc:
    - Clean up a few simplescalar comments from main.cc that Nate missed.
    - Add some comments and some doxygen documentation.
    - Move sim_running_systems to static System::numSystemsRunning.
arch/alpha/ev5.cc:
    Update num_running_systems to System::numSystemsRunning for full-sys too.
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/smt.hh:
    instead of polling all CPUs to find out the max number of threads across
    all CPUs, just have the CPUs themselves update the variable as they are
    created.
arch/alpha/isa_desc:
    First pass at fixing cvtst... not tested.
arch/alpha/ev5.cc:
base/statistics.cc:
base/statistics.hh:
arch/alpha/isa_desc:
    Just use the TYPEFUNC not FULLFUNC
arch/alpha/ev5.cc:
base/statistics.cc:
base/statistics.hh:
    committing from the wrong directory is a bad thing
arch/alpha/isa_desc:
    I hope a final solution for the cmptxx issue.
base/statistics.cc:
    All printable stats must first be initialized, so throw an assertion if they
    are not.  This ought to help in debugging a bit.
base/statistics.cc:
base/statistics.hh:
    Two new flags: nozero, and nonan.  This will supress printing stats if they
    are zero or NAN.  For example, it will cause vector elements to be skipped
    if there is no value, or it will cause distribution buckets to be skipped.
    (or an entire scalar stat to be skipped.)  This can be used in conjunction
    with prereq.  The difference with prereq, is that prereq just checks if the
    other stat has ANY values, and won't selectively ignore individual vector
    elements.
base/statistics.hh:
    this does not belong here
arch/alpha/isa_desc:
    Just happened to notice small insidious bug in itofs.
arch/isa_parser.py:
    New isa description language feature: multiple constants can be
    provided for a decode statement, e.g.:
    decode OP {
    0, 1: foo();
    2, 3: bar();
    }
    Documentation update included at no extra charge.
sim/param.hh:
    this can be const
sim/exec_context.cc:
    be more terse
arch/alpha/isa_desc:
    Revamp decoding of IEEE FP instructions (opcode 0x16).  I think we've
    got all the bases covered now.

    Also implemented cvtql/v & cvtql/sv (actually the same instruction
    from M5's perspective).
arch/isa_parser.py:
    - If isa_desc defines the global Python variable rcs_id, echo it
    into the output decoder.cc.
    - Only print last three components of ISA description path name in output.
    - Add RCS id string to this file.
arch/alpha/isa_desc:
    Add RCS id string.
arch/isa_parser.py:
    Get it right.
arch/isa_parser.py:
    Oone more little glitch...
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
    add support for mach syscalls.
base/trace.cc:
base/trace.hh:
    Some reorganization and cleanup.
    Add the ability to ignore trace output from certain sources.  The option is
    --trace:ignore.  It takes a space separated list of SimObjects to ignore.
    The SimObject is listed in the normal dotted herarchy notation.  (e.g.
    system0.cpu0.DL1) If an object is specified, the *all* child objects are
    ignored as well.  You can use a wildcard (*) to match any object.

    To ignore all trace statements from system1:
    --trace:ignore"system1"

    To ignore all DL1 statements:
    --trace:ignore="*.*.DL1"
sim/main.cc:
    Try the HOST varilable if HOSTNAME isn't found
sim/exetrace.cc:
sim/exetrace.hh:
    Minor tweeks to instruction execution tracing:
    - add a correct-path sequence number to all instructions
    - add colon characters to help delimit the instruction disassembly
arch/alpha/ev5.cc:
    Move all of the kernel statistics into the .cc file while I am still messing
    around with them.
    Add support for tracking context switches, and mode switches.
    More detailed tracking of ipl changes.
    Don't display zeroes for stats such as syscalls, ipls, faults, since zeroes
    are very common and there are a ton of stats.
base/hashmap.hh:
    don't forget about the hash_multimap
    oh, and string is used in here
base/str.cc:
    convert strings that represent bool values to a bool
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/ev5.cc:
    rework the tlb lookup code so that it uses a map instead of a linear
    search.
base/statistics.cc:
    a tiny bit of debugging assistance
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
sim/exec_context.hh:
    No need for these functions to be virtual.  Given that, they don't need to
    have the same interface.  This eliminates a useless check in an expensive
    function.
arch/alpha/isa_desc:
    This is an quick fix for the SimpleSclar-FP-Ops-Don't-Work-Right bug
    The SS_COMPATIBLE_FP #define at the top of the file forces the precision to match SS.
    This will change the precision for ALL CPU's.

    Nate will be making a change shortly so that this not done for Full System
arch/alpha/alpha_memory.cc:
    use i-> instead of (*i).    (what was I thinking?)
    also try to do i-> only once if it can be helped.
base/remote_gdb.cc:
sim/simple_cpu.cc:
    Move remote debugger code to where it belongs
    clean it up a tad while we're at it.
arch/alpha/isa_desc:
    Changes for the SS FP bug:
    SS-style FP done only if SS_COMPATIBLE_FP is defined in the makefile
arch/alpha/isa_traits.hh:
sim/memtest.cc:
sim/memtest.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/cache/lzss_compression.cc:
sim/cache/lzss_compression.hh:
    The new memory hierarchy. There is still some more changes to come, but this works now. IIC compression is broken, but no one else cares. DMA coherence might be broken (no way to test atm). There are doxygen warnings that I will clear up when I can stay connected for more than 3 minutes.
Doxyfile:

    Turn Graphics back on since we have squashed the warnings.
base/misc.hh:
    Add #include <assert.h> for those who use m5_assert() macro.
    Somehow g++ 3.3 is pickier about this than 3.2.
sim/exetrace.hh:
sim/simple_cpu.cc:
sim/std_types.hh:
    Style fixes... mostly changing 'struct foo_bar' to 'FooBar' for some
    older parts of the code.
Doxyfile:
    Always have a detailed section.
sim/host.hh:
    Get rid of an old simplescalar comment (plus improve some other comments).
base/statistics.cc:
base/statistics.hh:
    provide a way to get at the subdesc
base/statistics.hh:
    Make it possible to counte a sample more than once
base/statistics.cc:
    print the right value
base/statistics.cc:
base/statistics.hh:
    A bit of debugging support
base/statistics.cc:
base/statistics.hh:
    be more consistent
base/statistics.hh:
    use the correct axis
base/statistics.hh:
    remove dead code
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/sim_object.cc:
    Stats now sent by default to a file called "m5.stats".  Get the old
    behavior back by saying "--stats:file=cerr" on cmd line.

    Parameters and config-file stuff also sent to stats file where they belong.

    A few informational messages are sent to both cerr and to the stats file.
    Default output is pretty minimal now.
arch/alpha/faults.cc:
base/bitfield.hh:
base/random.cc:
base/random.hh:
sim/static_inst.cc:
test/stattest.cc:
    Fix RCS Id strings.
sim/base_cpu.hh:
sim/main.cc:
    Check if user forgot to specify any CPUs and print a meaningful
    error message (not just "improperly exited event loop!").
base/statistics.cc:
base/statistics.hh:
    Make subsequent calls to flags() add more flags instead of change them.
    Also add the concept of a reserved flag that the user is not allowed to
    set.  (Basically for passing around extra parameters in the stats package.)
sim/debug.cc:
sim/param.cc:
sim/param.hh:
sim/prog.cc:
sim/sim_events.cc:
    Check that VectorParam objects are valid before we let them be
    referenced.  Fix up a few places where we were just referencing them
    w/o checking.

    Also some const cleanup on Param object methods.
sim/sim_object.cc:
sim/sim_object.hh:
    Print SimObject class name when complaining about missing/broekn params.
base/inifile.cc:
    Add "-undef" to cpp flags to not define system-specific macros.
    (A '#define linux 1' was giving me trouble.)
base/statistics.hh:
    add support fo subnaming in the y direction for 2d vectors.  make the printing of it pretty and compatible with the old style.  also, suppress printing of a total for 2d vector if they x dimension is just 1.
base/statistics.cc:
    rework a lot of the stuff between #ifdef STAT_DISPLAY_COMPAT so it's neater and
    also more accurate.  add support for printing subdescriptions.
LICENSE:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/fake_syscall.cc:
arch/alpha/faults.cc:
arch/alpha/faults.hh:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/osfpal.hh:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/bitfield.hh:
base/callback.hh:
base/circlebuf.cc:
base/circlebuf.hh:
base/cprintf.cc:
base/cprintf.hh:
base/cprintf_formats.hh:
base/date.cc:
base/dbl_list.hh:
base/endian.hh:
base/fast_alloc.cc:
base/fast_alloc.hh:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/hashmap.hh:
base/inet.cc:
base/inet.hh:
base/inifile.cc:
base/inifile.hh:
base/intmath.cc:
base/misc.cc:
base/misc.hh:
base/mod_num.hh:
base/object_file.cc:
base/object_file.hh:
base/pollevent.cc:
base/pollevent.hh:
base/random.cc:
base/random.hh:
base/range.hh:
base/refcnt.hh:
base/remote_gdb.hh:
base/res_list.hh:
base/sched_list.hh:
base/socket.cc:
base/socket.hh:
base/statistics.cc:
base/statistics.hh:
base/str.cc:
base/str.hh:
base/symtab.cc:
base/symtab.hh:
base/trace.cc:
base/trace.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
kern/tru64/tru64.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
sim/async.hh:
sim/base_cpu.cc:
sim/base_cpu.hh:
sim/debug.cc:
sim/debug.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/exec_context.cc:
sim/exec_context.hh:
sim/exetrace.cc:
sim/exetrace.hh:
sim/host.hh:
sim/hybrid_pred.cc:
sim/hybrid_pred.hh:
sim/intr_control.cc:
sim/intr_control.hh:
sim/main.cc:
sim/memtest.cc:
sim/memtest.hh:
sim/op_class.hh:
sim/param.cc:
sim/param.hh:
sim/pc_event.cc:
sim/pc_event.hh:
sim/predictor.hh:
sim/prog.cc:
sim/prog.hh:
sim/sat_counter.cc:
sim/sat_counter.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/cache/lzss_compression.cc:
sim/cache/lzss_compression.hh:
sim/cache/null_compression.hh:
sim/sim_time.cc:
sim/sim_time.hh:
sim/simple_cpu.cc:
sim/simple_cpu.hh:
sim/smt.hh:
sim/static_inst.cc:
sim/static_inst.hh:
sim/std_types.hh:
sim/system.cc:
sim/system.hh:
sim/universe.cc:
test/bitvectest.cc:
test/circletest.cc:
test/cprintftest.cc:
test/initest.cc:
test/lru_test.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/sized_test.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
util/tap/tap.cc:
arch/isa_parser.py:
    Add attribution to license.
sim/cache/lzss_compression.cc:
sim/cache/lzss_compression.hh:
    Extend the compression algorithm to handle upto 4096 byte blocks. Improve compression of single bytes that can be sign extended.
sim/cache/lzss_compression.hh:
    Remove some todos that I've already done.
sim/hybrid_pred.cc:
sim/hybrid_pred.hh:
sim/memtest.cc:
sim/prog.cc:
sim/sat_counter.cc:
sim/memtest.hh:
sim/predictor.hh:
sim/prog.hh:
sim/sat_counter.hh:
    the new stats package.  voila.  the move to bitkeeper can go on, figuring what's happening can happen later.
base/trace.cc:
test/Makefile:
test/cprintftest.cc:
test/tracetest.cc:
    separate the context stuff for tracing from the actual tracing facility to
    make it easier to test.
    Add a test for tracing

--HG--
extra : convert_revision : 28dd3568b0714296345f8a5cba282f0b937ce725
2003-10-07 10:41:54 -04:00