Move some common full-system CPU initialization from the
SimpleCPU & FullCPU constructors to AlphaISA::initCPU(). cpu/simple_cpu/simple_cpu.cc: Move some common full-system CPU initialization from the SimpleCPU & FullCPU constructors to AlphaISA::initCPU(). Make 'fault' local to SimpleCPU::tick. cpu/simple_cpu/simple_cpu.hh: Make 'fault' local to SimpleCPU::tick (not an object member). --HG-- extra : convert_revision : e878dedfff06aac0548aca8b14d66c18b8916895
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3 changed files with 10 additions and 14 deletions
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@ -47,6 +47,11 @@ void
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AlphaISA::initCPU(RegFile *regs)
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{
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initIPRs(regs);
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// CPU comes up with PAL regs enabled
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swap_palshadow(regs, true);
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regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault];
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regs->npc = regs->pc + sizeof(MachInst);
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}
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void
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@ -97,6 +102,7 @@ AlphaISA::initIPRs(RegFile *regs)
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bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
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ipr[IPR_PAL_BASE] = PAL_BASE;
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ipr[IPR_MCSR] = 0x6;
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}
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@ -126,19 +126,10 @@ SimpleCPU::SimpleCPU(const string &_name, Process *_process,
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#ifdef FULL_SYSTEM
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xc = new ExecContext(this, 0, system, itb, dtb, mem);
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// initialize CPU, including PC
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TheISA::initCPU(&xc->regs);
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IntReg *ipr = xc->regs.ipr;
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ipr[TheISA::IPR_MCSR] = 0x6;
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AlphaISA::swap_palshadow(&xc->regs, true);
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fault = Reset_Fault;
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xc->regs.pc = ipr[TheISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
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xc->regs.npc = xc->regs.pc + sizeof(MachInst);
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#else
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xc = new ExecContext(this, /* thread_num */ 0, _process, /* asid */ 0);
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fault = No_Fault;
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#endif // !FULL_SYSTEM
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icacheInterface = icache_interface;
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@ -524,8 +515,10 @@ SimpleCPU::tick()
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{
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traceData = NULL;
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Fault fault = No_Fault;
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#ifdef FULL_SYSTEM
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if (fault == No_Fault && AlphaISA::check_interrupts &&
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if (AlphaISA::check_interrupts &&
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xc->cpu->check_interrupts() &&
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!PC_PAL(xc->regs.pc) &&
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status() != IcacheMissComplete) {
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@ -154,9 +154,6 @@ class SimpleCPU : public BaseCPU
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// current instruction
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MachInst inst;
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// current fault status
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Fault fault;
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// Refcounted pointer to the one memory request.
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MemReqPtr memReq;
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