Remove the uncacheable bit 39 check (needs to be merged in with head tree
if Tru64 is to continue to be supported on Turbolaser) and fixed
translation of physical addresses by clearing PA<42:35> when the real
uncachable bit (43) is set
arch/alpha/ev5.hh:
Change to support 256 ASNs and seperate VA_SPACE checks for EV5 and EV6
also add support proper translation of uncacheable physical addresses
dev/ide_ctrl.cc:
Fix to work with real address translation
--HG--
extra : convert_revision : aa3d1c284b8271d4763a8da2509c91bbcf83189a
This commit is contained in:
Andrew Schultz
parent
675b849b50
commit
f5c7b1358c
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@ -101,25 +101,7 @@ AlphaTLB::checkCacheability(MemReqPtr &req)
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* to catch a weird case where both are used, which shouldn't happen.
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*/
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if (req->paddr & PA_UNCACHED_BIT_40 ||
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req->paddr & PA_UNCACHED_BIT_39) {
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#ifdef DEBUG
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if (req->paddr & PA_UNCACHED_BIT_40) {
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if(uncacheBit39)
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panic("Bit 40 access follows bit 39 access, PA=%x\n",
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req->paddr);
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uncacheBit40 = true;
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} else if (req->paddr & PA_UNCACHED_BIT_39) {
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if(uncacheBit40)
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panic("Bit 39 acceess follows bit 40 access, PA=%x\n",
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req->paddr);
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uncacheBit39 = true;
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}
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#endif
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if (req->paddr & PA_UNCACHED_BIT_43) {
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// IPR memory space not implemented
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if (PA_IPR_SPACE(req->paddr))
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if (!req->xc->misspeculating())
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@ -128,6 +110,9 @@ AlphaTLB::checkCacheability(MemReqPtr &req)
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// mark request as uncacheable
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req->flags |= UNCACHEABLE;
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// Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
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req->paddr &= PA_UNCACHED_MASK;
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}
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}
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@ -313,10 +298,10 @@ AlphaITB::translate(MemReqPtr &req) const
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return ITB_Acv_Fault;
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}
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// Check for "superpage" mapping: when SP<1> is set, and
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// VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>.
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if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
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VA_SPACE(req->vaddr) == 2) {
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// VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
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// VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
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if (VA_SPACE_EV6(req->vaddr) == 0x7e) {
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// only valid in kernel mode
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if (ICM_CM(ipr[AlphaISA::IPR_ICM]) != AlphaISA::mode_kernel) {
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@ -328,11 +313,10 @@ AlphaITB::translate(MemReqPtr &req) const
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req->paddr = req->vaddr & PA_IMPL_MASK;
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// sign extend the physical address properly
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if (req->paddr & PA_UNCACHED_BIT_39 ||
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req->paddr & PA_UNCACHED_BIT_40)
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req->paddr |= 0xf0000000000ULL;
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if (req->paddr & PA_UNCACHED_BIT_40)
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req->paddr |= ULL(0xf0000000000);
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else
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req->paddr &= 0xffffffffffULL;
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req->paddr &= ULL(0xffffffffff);
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} else {
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// not a physical address: need to look up pte
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@ -499,10 +483,8 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
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return DTB_Fault_Fault;
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}
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// Check for "superpage" mapping: when SP<1> is set, and
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// VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>.
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if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
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VA_SPACE(req->vaddr) == 2) {
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// Check for "superpage" mapping
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if (VA_SPACE_EV6(req->vaddr) == 0x7e) {
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// only valid in kernel mode
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if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) !=
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@ -517,11 +499,10 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
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req->paddr = req->vaddr & PA_IMPL_MASK;
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// sign extend the physical address properly
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if (req->paddr & PA_UNCACHED_BIT_39 ||
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req->paddr & PA_UNCACHED_BIT_40)
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req->paddr |= 0xf0000000000ULL;
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if (req->paddr & PA_UNCACHED_BIT_40)
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req->paddr |= ULL(0xf0000000000);
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else
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req->paddr &= 0xffffffffffULL;
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req->paddr &= ULL(0xffffffffff);
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} else {
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if (write)
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@ -32,8 +32,8 @@
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#define ALT_MODE_AM(X) (((X) >> 3) & 0x3)
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#define DTB_CM_CM(X) (((X) >> 3) & 0x3)
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#define DTB_ASN_ASN(X) (((X) >> 57) & 0x7f)
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#define DTB_PTE_PPN(X) (((X) >> 32) & 0x07ffffff)
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#define DTB_ASN_ASN(X) (((X) >> 57) & 0xff)
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#define DTB_PTE_PPN(X) (((X) >> 32) & 0x07fffffff)
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#define DTB_PTE_XRE(X) (((X) >> 8) & 0xf)
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#define DTB_PTE_XWE(X) (((X) >> 12) & 0xf)
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#define DTB_PTE_FONR(X) (((X) >> 1) & 0x1)
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@ -42,8 +42,8 @@
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#define DTB_PTE_ASMA(X) (((X) >> 4) & 0x1)
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#define ICM_CM(X) (((X) >> 3) & 0x3)
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#define ITB_ASN_ASN(X) (((X) >> 4) & 0x7f)
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#define ITB_PTE_PPN(X) (((X) >> 32) & 0x07ffffff)
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#define ITB_ASN_ASN(X) (((X) >> 4) & 0xff)
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#define ITB_PTE_PPN(X) (((X) >> 32) & 0x07fffffff)
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#define ITB_PTE_XRE(X) (((X) >> 8) & 0xf)
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#define ITB_PTE_FONR(X) (((X) >> 1) & 0x1)
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#define ITB_PTE_FONW(X) (((X) >> 2) & 0x1)
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@ -54,12 +54,15 @@
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#define VA_IMPL_MASK ULL(0x000007ffffffffff)
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#define VA_IMPL(X) ((X) & VA_IMPL_MASK)
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#define VA_VPN(X) (VA_IMPL(X) >> 13)
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#define VA_SPACE(X) (((X) >> 41) & 0x3)
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#define VA_SPACE_EV5(X) (((X) >> 41) & 0x3)
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#define VA_SPACE_EV6(X) (((X) >> 41) & 0x7f)
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#define VA_POFS(X) ((X) & 0x1fff)
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#define PA_IMPL_MASK ULL(0xfffffffffff) // for Tsunami
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#define PA_UNCACHED_BIT_39 ULL(0x8000000000)
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#define PA_UNCACHED_BIT_40 ULL(0x10000000000)
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#define PA_UNCACHED_BIT_43 ULL(0x80000000000)
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#define PA_UNCACHED_MASK ULL(0x807ffffffff) // Clear PA<42:35>
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#define PA_IPR_SPACE(X) ((X) >= ULL(0xFFFFFF00000))
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#define PA_PFN2PA(X) ((X) << 13)
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@ -357,7 +357,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data)
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pioInterface->addAddrRange(pri_cmd_addr,
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pri_cmd_addr + pri_cmd_size - 1);
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pri_cmd_addr = ((pri_cmd_addr | 0xf0000000000ULL) & PA_IMPL_MASK);
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pri_cmd_addr = pri_cmd_addr & PA_UNCACHED_MASK;
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break;
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case PCI0_BASE_ADDR1:
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@ -366,7 +366,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data)
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pioInterface->addAddrRange(pri_ctrl_addr,
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pri_ctrl_addr + pri_ctrl_size - 1);
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pri_ctrl_addr = ((pri_ctrl_addr | 0xf0000000000ULL) & PA_IMPL_MASK);
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pri_ctrl_addr = pri_ctrl_addr & PA_UNCACHED_MASK;
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break;
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case PCI0_BASE_ADDR2:
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@ -375,7 +375,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data)
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pioInterface->addAddrRange(sec_cmd_addr,
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sec_cmd_addr + sec_cmd_size - 1);
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sec_cmd_addr = ((sec_cmd_addr | 0xf0000000000ULL) & PA_IMPL_MASK);
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sec_cmd_addr = sec_cmd_addr & PA_UNCACHED_MASK;
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break;
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case PCI0_BASE_ADDR3:
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@ -384,7 +384,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data)
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pioInterface->addAddrRange(sec_ctrl_addr,
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sec_ctrl_addr + sec_ctrl_size - 1);
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sec_ctrl_addr = ((sec_ctrl_addr | 0xf0000000000ULL) & PA_IMPL_MASK);
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sec_ctrl_addr = sec_ctrl_addr & PA_UNCACHED_MASK;
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break;
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case PCI0_BASE_ADDR4:
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@ -392,7 +392,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data)
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if (pioInterface)
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pioInterface->addAddrRange(bmi_addr, bmi_addr + bmi_size - 1);
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bmi_addr = ((bmi_addr | 0xf0000000000ULL) & PA_IMPL_MASK);
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bmi_addr = bmi_addr & PA_UNCACHED_MASK;
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break;
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}
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}
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