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Remove copys from isa_desc, and implement a store and forward bus bridge

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arch/alpha/isa_desc:
    Just to make sure, remove the new copy instructions until everything works.

--HG--
extra : convert_revision : cdd3d4c8fa415175aaee04f4a99340dcf82dbc3a
This commit is contained in:
Erik Hallnor 2004-02-29 22:41:11 -05:00
parent 7f688ba6a9
commit cbc42f1d71
1 changed files with 6 additions and 6 deletions
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12
arch/alpha/isa_desc
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@ -1854,9 +1854,9 @@ decode OPCODE default Unknown::unknown() {
0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }});
0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED);
0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED);
0x20: copy_load({{EA = Ra;}},
{{memAccessObj->copySrcTranslate(EA);}},
IsMemRef, IsLoad, IsCopy);
//0x20: copy_load({{EA = Ra;}},
// {{memAccessObj->copySrcTranslate(EA);}},
// IsMemRef, IsLoad, IsCopy);
}
format LoadOrPrefetch {
@ -1876,9 +1876,9 @@ decode OPCODE default Unknown::unknown() {
0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }});
0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }});
0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }});
0x24: copy_store({{EA = Rb;}},
{{memAccessObj->copy(EA);}},
IsMemRef, IsStore, IsCopy);
//0x24: copy_store({{EA = Rb;}},
// {{memAccessObj->copy(EA);}},
// IsMemRef, IsStore, IsCopy);
}
format StoreCond {