Try to get the correct license on various files
remove stuff that is ambiguous
Clean up code a bit
arch/alpha/aout_machdep.h:
Add M5 License
docs/stl.hh:
M5 license
base/remote_gdb.cc:
Most of this is mine, so stick in the m5 license
dev/console.hh:
Clean up comments
merge simple() and out() into one function.
dev/console.hh:
dev/console.cc:
m5 license
dev/console.cc:
merge simple and out.
remove dead code
dev/console.cc:
Remove comments that weren't mine.
Clean up code
dev/console.hh:
update names
dev/alpha_console.cc:
use new interface
--HG--
extra : convert_revision : 3cd2357e1525db43c2ef9e89a9b47a47861d6af9
This commit is contained in:
Nathan Binkert
parent
940c214759
commit
b177f696ff
6 changed files with 175 additions and 106 deletions
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@ -1,4 +1,30 @@
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/* $Id$ */
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/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
|
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __AOUT_MACHDEP_H__
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#define __AOUT_MACHDEP_H__
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@ -1,4 +1,31 @@
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/* $Id$ */
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/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1990, 1993
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* The Regents of the University of California. All rights reserved.
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@ -139,7 +139,7 @@ AlphaConsole::write(MemReqPtr req, const uint8_t *data)
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}
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if (paddr == offsetof(AlphaAccess, outputChar)) {
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console->simple((char)(val & 0xff));
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console->out((char)(val & 0xff), false);
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return No_Fault;
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}
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147
dev/console.cc
147
dev/console.cc
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@ -1,4 +1,30 @@
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/* $Id$ */
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/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* User Console Definitions
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@ -26,15 +52,6 @@
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using namespace std;
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// check whether an int is pending
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inline bool
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IntPending(int status, int mask)
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{ return (status & mask) != 0; }
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inline bool
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IntTransition(int ostaus, int omask, int nstatus, int nmask)
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{ return IntPending(ostaus, omask) != IntPending(nstatus, nmask); }
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////////////////////////////////////////////////////////////////////////
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//
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//
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@ -56,7 +73,7 @@ SimConsole::Event::process(int revent)
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SimConsole::SimConsole(const string &name, const string &file, int num)
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: SimObject(name), event(NULL), number(num), in_fd(-1), out_fd(-1),
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listener(NULL), txbuf(16384), rxbuf(16384), outfile(NULL),
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intr_status(0), intr_enable(0), intr(NULL)
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_status(0), _enable(0), intr(NULL)
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{
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if (!file.empty())
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outfile = new ofstream(file.c_str());
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@ -182,13 +199,6 @@ SimConsole::write(const uint8_t *buf, size_t len)
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return ret;
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}
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///////////////////////////////////////////////////////////////////////
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// ConfigureTerm turns off all character processing by the host OS so
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// the launched OS can control it.
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//
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// We ignore anything except stdin; the sconsole program runs this
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// same code on the ttys for the slave consoles before connecting.
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//
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void
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SimConsole::configTerm()
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{
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@ -210,18 +220,6 @@ SimConsole::configTerm()
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}
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}
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///////////////////////////////////////////////////////////////////////
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// console i/o
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//
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///////////////////////////////////////////////////////////////////////
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//
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// Console input.
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// Returns -1 if there is no character pending, otherwise returns the
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// char. Calling this function clears the input int (if no further
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// chars are pending).
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//
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int
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SimConsole::in()
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{
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@ -234,21 +232,13 @@ SimConsole::in()
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rxbuf.read(&c, 1);
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DPRINTF(Console, "in: \'%c\' %#02x status: %#x\n",
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isprint(c) ? c : ' ', c, intr_status);
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isprint(c) ? c : ' ', c, _status);
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return c;
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}
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///////////////////////////////////////////////////////////////////////
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//
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// Console output.
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// NOTE: this very rudimentary device generates a TX int as soon as
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// a character is output, since it has unlimited TX buffer capacity.
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//
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// Console output.
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// Uses sim_console_out to perform functionality similar to 'write'
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void
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SimConsole::out(char c)
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SimConsole::out(char c, bool raise_int)
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{
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txbuf.write(c);
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@ -258,59 +248,39 @@ SimConsole::out(char c)
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if (outfile)
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outfile->write(&c, 1);
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raiseInt(TransmitInterrupt);
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if (raise_int)
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raiseInt(TransmitInterrupt);
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DPRINTF(Console, "out: \'%c\' %#02x status: %#x\n",
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isprint(c) ? c : ' ', (int)c, intr_status);
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}
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// Simple console output used by Alpha firmware (not by the OS) -
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// outputs the character to console n, and doesn't raise any
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// interrupts
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void
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SimConsole::simple(char c)
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{
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txbuf.write(c);
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if (out_fd >= 0)
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write(c);
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if (outfile)
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outfile->write(&c, 1);
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DPRINTF(Console, "simple char: \'%c\' %#02x\n",
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DPRINTF(Console, "out: \'%c\' %#02x",
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isprint(c) ? c : ' ', (int)c);
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if (raise_int)
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DPRINTF(Console, "status: %#x\n", _status);
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else
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DPRINTF(Console, "\n");
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}
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// Read the current interrupt status of this console.
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int
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SimConsole::intStatus()
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{
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#if 0
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DPRINTF(Console, "interrupt %d status: %#x\n",
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number, intr_status);
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#endif
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return intr_status;
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}
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inline bool
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MaskStatus(int status, int mask)
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{ return (status & mask) != 0; }
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int
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SimConsole::clearInt(int i)
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{
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int old_status = intr_status;
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intr_status &= ~i;
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if (IntTransition(old_status, intr_enable, intr_status, intr_enable) &&
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intr)
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int old = _status;
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_status &= ~i;
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if (MaskStatus(old, _enable) != MaskStatus(_status, _enable) && intr)
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intr->clear(TheISA::INTLEVEL_IRQ0);
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return old_status;
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return old;
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}
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void
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SimConsole::raiseInt(int i)
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{
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int old = intr_status;
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intr_status |= i;
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if (IntTransition(old, intr_enable, intr_status, intr_enable) && intr)
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int old = _status;
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_status |= i;
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if (MaskStatus(old, _enable) != MaskStatus(_status, _enable) && intr)
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intr->post(TheISA::INTLEVEL_IRQ0);
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}
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@ -320,27 +290,22 @@ SimConsole::initInt(IntrControl *i)
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if (intr)
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panic("Console has already been initialized.");
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// note: intr_status and intr_enable will normally be 0, since
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// cs is statically allocated. When restoring from a checkpoint,
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// these fields will be set, so don't touch them here.
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intr = i; // interrupt handler
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intr = i;
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}
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// Set the interrupt enable bits.
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void
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SimConsole::setInt(int bits)
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{
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int old_enable;
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int old;
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if (bits & ~(TransmitInterrupt | ReceiveInterrupt))
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panic("An interrupt was not set!");
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old_enable = intr_enable;
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intr_enable |= bits;
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old = _enable;
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_enable |= bits;
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if (IntTransition(intr_status, old_enable, intr_status, intr_enable) &&
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intr) {
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if (IntPending(intr_status, intr_enable))
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if (MaskStatus(_status, old) != MaskStatus(_status, _enable) && intr) {
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if (MaskStatus(_status, _enable))
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intr->post(TheISA::INTLEVEL_IRQ0);
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else
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intr->clear(TheISA::INTLEVEL_IRQ0);
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@ -356,7 +321,7 @@ SimConsole::serialize()
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void
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SimConsole::unserialize(IniFile &db, const std::string &category,
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ConfigNode *node)
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ConfigNode *node)
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{
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panic("Unimplemented");
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}
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@ -1,4 +1,30 @@
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/* $Id$ */
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/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
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/* @file
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* User Console Interface
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@ -69,8 +95,8 @@ class SimConsole : public SimObject
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protected:
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// interrupt status/enable
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int intr_status;
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int intr_enable;
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int _status;
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int _enable;
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// interrupt handle
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IntrControl *intr;
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@ -79,16 +105,13 @@ class SimConsole : public SimObject
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/////////////////
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// OS interface
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// Input a character from the console. Returns the character (if
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// any) or -1 if there is no character pending on this console. If
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// no further characters are pending, the (input) interrupt is
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// cleared.
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// Get a character from the console.
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// return of -1 means there is no character pending.
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// Interrupts are cleared when the buffer is empty.
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int in();
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// Output a character to the console. This never fails, as this
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// device doesn't model finite buffering capacity.
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void out(char c);
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void simple(char c);
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// Send a character to the console
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void out(char c, bool raise_int = true);
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enum {
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TransmitInterrupt = 1,
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@ -96,7 +119,7 @@ class SimConsole : public SimObject
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|||
};
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||||
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||||
// Read the current interrupt status of this console.
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||||
int intStatus();
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||||
int intStatus() { return _status; }
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||||
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||||
// Set the interrupt enable bits.
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||||
int clearInt(int i);
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||||
|
|
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|||
28
docs/stl.hh
28
docs/stl.hh
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@ -1,3 +1,31 @@
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|||
/*
|
||||
* Copyright (c) 2003 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* Dummy definitions of STL classes to pick up relationships in doxygen.
|
||||
|
|
|
|||
Loading…
Reference in a new issue