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Clean up a few spots where we weren't handling of misspeculation correctly.

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arch/alpha/ev5.cc:
    Don't call kernelStats.hwrei() or system->breakpoint() on misspeculated paths.
arch/alpha/isa_desc:
    Don't write reegs.intrflag, do Annotate::Callpal, or call xc->syscall
    on misspeculated paths.

--HG--
extra : convert_revision : e73b96fbe4ac5be85fb20aa218fd05fd56d5b2f3
This commit is contained in:
Steve Reinhardt 2003-10-28 09:09:45 -08:00
parent cec7f73abf
commit 1820520697
2 changed files with 17 additions and 8 deletions
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8
arch/alpha/ev5.cc
View file

@ -168,11 +168,11 @@ ExecContext::hwrei()
if (!PC_PAL(regs.pc))
return Unimplemented_Opcode_Fault;
kernelStats.hwrei();
regs.npc = ipr[AlphaISA::IPR_EXC_ADDR];
setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
if (!misspeculating()) {
kernelStats.hwrei();
if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
AlphaISA::swap_palshadow(&regs, false);
@ -560,7 +560,7 @@ ExecContext::simPalCheck(int palFunc)
case PAL::bpt:
case PAL::bugchk:
if (system->breakpoint())
if (!misspeculating() && system->breakpoint())
return false;
break;
}

17
arch/alpha/isa_desc
View file

@ -2322,11 +2322,15 @@ decode OPCODE default Unknown::unknown() {
format BasicOperate {
0xe000: rc({{
Ra = xc->regs.intrflag;
xc->regs.intrflag = 0;
if (!xc->misspeculating()) {
xc->regs.intrflag = 0;
}
}}, No_OpClass);
0xf000: rs({{
Ra = xc->regs.intrflag;
xc->regs.intrflag = 1;
if (!xc->misspeculating()) {
xc->regs.intrflag = 1;
}
}}, No_OpClass);
}
#else
@ -2343,7 +2347,9 @@ decode OPCODE default Unknown::unknown() {
// on this PAL call (including maybe suppress it)
bool dopal = xc->simPalCheck(palFunc);
Annotate::Callpal(xc, palFunc);
if (!xc->misspeculating()) {
Annotate::Callpal(xc, palFunc);
}
if (dopal) {
if (!xc->misspeculating()) {
@ -2360,7 +2366,10 @@ decode OPCODE default Unknown::unknown() {
if (!xc->misspeculating())
SimExit("halt instruction encountered");
}});
0x83: callsys({{ xc->syscall(); }});
0x83: callsys({{
if (!xc->misspeculating())
xc->syscall();
}});
// Read uniq reg into ABI return value register (r0)
0x9e: rduniq({{ R0 = Runiq; }});
// Write uniq reg with value from ABI arg register (r16)