Commit graph

457 commits

Author SHA1 Message Date
Andreas Sandberg
d0ffd2f9b8 test: Make the memtest and memcheck tests functional only
The memtest and memcheck are not designed to test timing. Make them
functional only to make ref diffs less noisy in the future.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-09-22 10:49:09 +01:00
Andreas Sandberg
ada0e2f02f tests, arm: Make switcheroo and checkpoint tests functional
Switcheroo and checkpoint tests should generally be considered to be
successful if they run to completion.  Remove all reference output
files from the switcheroo and checkopint tests to make them purely
functional.

Change-Id: I70b47853bd662b7a33716d9e0d2154b16077f9dc
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-09-16 09:14:31 +01:00
Steve Reinhardt
608a37c844 tests: remove EIO tests
An email sent to gem5-users and gem5-dev asking if anyone was
still using EIO traces got no responses, so it seems like it's
not worth maintaining this any longer.
2016-08-13 23:07:28 -04:00
Andreas Sandberg
55ed9609f1 stats: Update to match classic memory changes 2016-08-12 14:12:59 +01:00
Curtis Dunham
ae445c0348 stats: update references 2016-08-02 11:34:32 +01:00
Curtis Dunham
84f138ba96 stats: update references 2016-07-21 17:19:18 +01:00
Abdul Mutaal Ahmad
9c20880fb5 mem: tester for new HMC configuration
This patch provides the example test script to configure different HMC
architecture and run traffic through traffic generator.

Committed by Jason Lowe-Power <jason@lowepower.com>
2016-07-01 09:48:43 -05:00
Andreas Sandberg
9c8710430e stats: Update stats to reflect ARM changes 2016-06-21 16:42:04 +01:00
Andreas Sandberg
efb7fb6f85 mem: Resolve TrafficGen trace relative to the config
The traffic generator currently resolves relative trace paths relative
to gem5's current working directory. This can lead to surprising
results for relative paths where the expectation would normally be
that they are resolved relative to the configuration file. This
changeset implements config-relative trace file lookups. The old
behavior is kept as a fallback for configs that expect that behavior.

Change-Id: I1bda4e16725842666ffc37dcb6838c23a6ff138c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-06-20 14:49:37 +01:00
Steve Reinhardt
54aeb1a187 stats: update EIO stats 2016-06-12 20:02:49 -04:00
Andreas Sandberg
85997e66a0 stats: Add power stats to test references
Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 17:16:44 +01:00
Steve Reinhardt
672c06a01d stats: update EIO stats 2016-06-06 00:18:34 -04:00
Andreas Sandberg
1d933447fc stats: Update to match ARM ISA changes 2016-06-02 14:14:36 +01:00
Curtis Dunham
dafec4a515 stats: update and fix e273e86a873d 2016-05-31 16:55:47 +01:00
Curtis Dunham
62b6ff22ec stats: update for snoop filter tweak
--HG--
extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 11:07:18 +01:00
Steve Reinhardt
2ae8b365c1 tests: update EIO ref stats for removed cache stats
Complaints about changes in EIO tests were due to reference files
that still have removed cache stats from cset 11454:e55afadc4e19.
2016-05-07 14:43:06 -04:00
Andreas Sandberg
b80f568bcf tests: Remove stale reference output files
Remove test reference files that are not generated any more:

    * chair.cook.ppm: This file should be generated by eon and not
      mcf, so it shouldn't be included as an output from mcf.

    * system.pc.terminal: The terminal device has been renamed so this
      file is no longer generated.

Change-Id: I3962efe1ff25479ca276115f7564eccb5fac8cf9
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-04-28 15:16:52 +01:00
Andreas Hansson
8845aae4da tests: Add a basic memcheck regression
This patch adds a simple regression that calls the existing
memcheck.py script.

--HG--
rename : tests/configs/learning-gem5-p1-simple.py => tests/configs/memcheck.py
rename : tests/quick/se/70.tgen/test.py => tests/quick/se/51.memcheck/test.py
2016-04-25 03:46:12 -04:00
Andreas Hansson
b006ad26d4 stats: Update stats to reflect cache changes
Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.
2016-04-21 04:48:24 -04:00
Andreas Hansson
d9193d1b20 stats: Match current behaviour
Small changes to the branch predictor and BTB caused stats changes
throughout.
2016-04-09 12:13:40 -04:00
Curtis Dunham
1d61224a8b stats: update stats for thermals, indirect BP 2016-04-08 11:01:45 -05:00
Steve Reinhardt
d7c083864c stats: update stats for ld.so support
Additional auxv entries leads to more instructions in start-up
while walking the list, along with different cache conflicts
wrt stack entries.
2016-03-17 10:32:53 -07:00
Steve Reinhardt
4fc69db8f8 stats: update stats for mmap changes 2016-03-17 10:30:58 -07:00
Steve Reinhardt
9d8fec0d90 stats: update stats for mmap() change.
SE O3 runs see an additional reg read per mmap() call.
2016-03-17 10:25:11 -07:00
Steve Reinhardt
807e2705b4 stats: update gpu-ruby-GPU_RfO stats
Output changed way back in this cset:

changeset:   11345:b6a66a90e0a1
user:        John Kalamatianos <john.kalamatianos@amd.com>
summary:     gpu: fix bugs with MemFence, Flat Instrs and Resource utilization
2016-02-18 10:42:03 -05:00
Krishnendra Nathella
cabd4768c7 cpu: Fix LLSC atomic CPU wakeup
Writes to locked memory addresses (LLSC) did not wake up the locking
CPU. This can lead to deadlocks on multi-core runs. In AtomicSimpleCPU,
recvAtomicSnoop was checking if the incoming packet was an invalidation
(isInvalidate) and only then handled a locked snoop. But, writes are
seen instead of invalidates when running without caches (fast-forward
configurations). As as simple fix, now handleLockedSnoop is also called
even if the incoming snoop packet are from writes.
2015-07-19 15:03:30 -05:00
Matteo Andreozzi
496a8c6c92 cpu: TraceGen fix for tick frequency check
Bug fix for check on protobuf file frequency being different than
global frequency.

The ASCII encoder script is also fixed, and the example trace used in
the regressions is updated.
2016-02-24 04:16:55 -05:00
Andreas Hansson
c6cede244b stats: Update stats to reflect changes to cache and crossbar 2016-02-10 04:08:27 -05:00
Steve Reinhardt
ce35c06c6e stats: update EIO stats for recent changes 2016-02-06 01:35:03 -05:00
Tony Gutierrez
1285d639eb stats: update stats to after GPU checkin 2016-01-22 10:42:13 -05:00
Tony Gutierrez
1a7d3f9fcb gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
Steve Reinhardt
2b49d3b6ca tests: update EIO reference outputs 2015-12-28 15:43:06 -05:00
Anthony Gutierrez
4935f0d5ff stats: bump stats to reflect ruby tester changes 2015-12-12 17:27:38 -05:00
Andreas Sandberg
bbcbe028fe stats: Update to reflect changes to PCI handling 2015-12-05 00:11:25 +00:00
Andreas Sandberg
5a249e03a4 stats: Update to reflect changes to RealView platform code 2015-12-04 00:19:05 +00:00
Nilay Vaish
de489e1997 stats: updates due to recent chagnesets 2015-11-16 05:08:57 -06:00
Nilay Vaish
e1385784f2 stats: remove wb_penalized and wb_penalized_rate 2015-11-16 04:58:29 -06:00
Andreas Hansson
324bc9771d stats: Update stats to match cache changes 2015-11-06 03:26:50 -05:00
Joel Hestness
735c4a8766 stats: Update for UDelayEvent quiesce change 2015-10-10 16:45:41 -05:00
Andreas Sandberg
17dbb49294 tests: Update SMT tests to correctly configure CPUs
The 01.hello-2T-smt test case for the O3 CPU didn't correctly setup
the number of threads before creating interrupt controllers, which
confused the constructor in BaseCPU. This changeset adds SMT support
to the test configuration infrastructure.

--HG--
rename : tests/configs/o3-timing.py => tests/configs/o3-timing-mt.py
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
2015-10-05 13:13:23 -05:00
Steve Reinhardt
d1811cc6cf stats: update EIO stats for snoop filter changes 2015-10-02 01:04:12 -04:00
Mitch Hayenga
582a0148b4 config,cpu: Add SMT support to Atomic and Timing CPUs
Adds SMT support to the "simple" CPU models so that they can be
used with other SMT-supported CPUs. Example usage: this enables
the TimingSimpleCPU to be used to warmup caches before swapping to
detailed mode with the in-order or out-of-order based CPU models.
2015-09-30 11:14:19 -05:00
Andreas Hansson
806e1fbf0f stats: Update stats to reflect snoop-filter changes 2015-09-25 07:27:03 -04:00
Nilay Vaish
928d4b4ba8 stats: updates due to changes to MOESI_hammer 2015-09-16 22:17:54 -05:00
Nilay Vaish
c5058c0c00 stats: slight changes to MOESI_CMP_token.
Due slight change to latency for the reissue table.
2015-09-16 11:59:57 -05:00
Jason Lowe-Power
fdf2a6f439 stats: files for regression tests for Learning gem5 scripts
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-09-16 09:35:36 -05:00
Jason Lowe-Power
29dd04cfe9 tests: Add tests for the Learning gem5 scripts
These tests will ensure that Learning gem5 scripts are always up to date with
the changes in the mainline of gem5.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-09-16 09:35:36 -05:00
Nilay Vaish
0d6a6dfd7b stats: updates due to recent changesets including d0934b57735a 2015-09-15 08:14:09 -05:00
Nilay Vaish
66941163e5 stats: updates due to recent changes. 2015-08-30 12:24:19 -05:00
Joel Hestness
93c173a95e stats: Bump for MessageBuffer, cache latency changes 2015-08-14 01:19:34 -05:00