stats: update EIO stats
This commit is contained in:
Steve Reinhardt
parent
b6d20c25c3
commit
672c06a01d
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@ -1,10 +1,12 @@
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Redirecting stdout to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic/simout
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Redirecting stderr to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic/simerr
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled May 7 2016 13:41:33
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gem5 started May 7 2016 13:42:02
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gem5 executing on zizzer, pid 51296
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command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic
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gem5 compiled Jun 5 2016 19:50:43
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gem5 started Jun 5 2016 20:05:34
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gem5 executing on zizzer, pid 54386
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command line: /z/stever/hg/gem5/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re /z/stever/hg/gem5/tests/testing/../run.py quick/se/20.eio-short/alpha/eio/simple-atomic
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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@ -0,0 +1,152 @@
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000250 # Number of seconds simulated
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sim_ticks 250015500 # Number of ticks simulated
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final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1086021 # Simulator instruction rate (inst/s)
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host_op_rate 1085950 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 542974724 # Simulator tick rate (ticks/s)
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host_mem_usage 223156 # Number of bytes of host memory used
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host_seconds 0.46 # Real time elapsed on the host
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sim_insts 500001 # Number of instructions simulated
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sim_ops 500001 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 2000076 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 872600 # Number of bytes read from this memory
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system.physmem.bytes_read::total 2872676 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 2000076 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 2000076 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::cpu.data 417562 # Number of bytes written to this memory
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system.physmem.bytes_written::total 417562 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 500019 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 124435 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 624454 # Number of read requests responded to by this memory
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system.physmem.num_writes::cpu.data 56340 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 56340 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 7999808012 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 3490183609 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 11489991621 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 7999808012 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 7999808012 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 1670144451 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 1670144451 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 7999808012 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 5160328060 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 13160136072 # Total bandwidth to/from this memory (bytes/s)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 124435 # DTB read hits
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system.cpu.dtb.read_misses 8 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 124443 # DTB read accesses
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system.cpu.dtb.write_hits 56340 # DTB write hits
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system.cpu.dtb.write_misses 10 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 56350 # DTB write accesses
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system.cpu.dtb.data_hits 180775 # DTB hits
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system.cpu.dtb.data_misses 18 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 180793 # DTB accesses
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system.cpu.itb.fetch_hits 500019 # ITB hits
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system.cpu.itb.fetch_misses 13 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 500032 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 18 # Number of system calls
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system.cpu.numCycles 500032 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 500001 # Number of instructions committed
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system.cpu.committedOps 500001 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 474689 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 32 # Number of float alu accesses
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system.cpu.num_func_calls 14357 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls
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system.cpu.num_int_insts 474689 # number of integer instructions
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system.cpu.num_fp_insts 32 # number of float instructions
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system.cpu.num_int_register_reads 654286 # number of times the integer registers were read
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system.cpu.num_int_register_writes 371542 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 32 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
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system.cpu.num_mem_refs 180793 # number of memory refs
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system.cpu.num_load_insts 124443 # Number of load instructions
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system.cpu.num_store_insts 56350 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 500032 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.Branches 59023 # Number of branches fetched
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system.cpu.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
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system.cpu.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction
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system.cpu.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
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system.cpu.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction
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system.cpu.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction
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system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::total 500019 # Class of executed instruction
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system.membus.trans_dist::ReadReq 624454 # Transaction distribution
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system.membus.trans_dist::ReadResp 624454 # Transaction distribution
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system.membus.trans_dist::WriteReq 56340 # Transaction distribution
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system.membus.trans_dist::WriteResp 56340 # Transaction distribution
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system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1000038 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 361550 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 1361588 # Packet count per connected master and slave (bytes)
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system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2000076 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1290162 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size::total 3290238 # Cumulative packet size per connected master and slave (bytes)
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system.membus.snoops 0 # Total snoops (count)
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system.membus.snoop_fanout::samples 680794 # Request fanout histogram
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system.membus.snoop_fanout::mean 0.734464 # Request fanout histogram
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system.membus.snoop_fanout::stdev 0.441618 # Request fanout histogram
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system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::0 180775 26.55% 26.55% # Request fanout histogram
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system.membus.snoop_fanout::1 500019 73.45% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::min_value 0 # Request fanout histogram
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system.membus.snoop_fanout::max_value 1 # Request fanout histogram
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system.membus.snoop_fanout::total 680794 # Request fanout histogram
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---------- End Simulation Statistics ----------
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@ -1,10 +1,12 @@
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Redirecting stdout to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing/simout
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Redirecting stderr to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing/simerr
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled May 7 2016 13:41:33
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gem5 started May 7 2016 13:42:14
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gem5 executing on zizzer, pid 51342
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command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing
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gem5 compiled Jun 5 2016 19:50:43
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gem5 started Jun 5 2016 20:04:44
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gem5 executing on zizzer, pid 54380
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command line: /z/stever/hg/gem5/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re /z/stever/hg/gem5/tests/testing/../run.py quick/se/20.eio-short/alpha/eio/simple-timing
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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@ -0,0 +1,497 @@
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000733 # Number of seconds simulated
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sim_ticks 733071500 # Number of ticks simulated
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final_tick 733071500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 528622 # Simulator instruction rate (inst/s)
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host_op_rate 528606 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 774988448 # Simulator tick rate (ticks/s)
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host_mem_usage 232700 # Number of bytes of host memory used
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host_seconds 0.95 # Real time elapsed on the host
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sim_insts 500001 # Number of instructions simulated
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sim_ops 500001 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 25792 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 29056 # Number of bytes read from this memory
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system.physmem.bytes_read::total 54848 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 25792 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 25792 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 403 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 454 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 857 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 35183471 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 39635970 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 74819441 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 35183471 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 35183471 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 35183471 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 39635970 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 74819441 # Total bandwidth to/from this memory (bytes/s)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 124435 # DTB read hits
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system.cpu.dtb.read_misses 8 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 124443 # DTB read accesses
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system.cpu.dtb.write_hits 56340 # DTB write hits
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system.cpu.dtb.write_misses 10 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 56350 # DTB write accesses
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system.cpu.dtb.data_hits 180775 # DTB hits
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system.cpu.dtb.data_misses 18 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 180793 # DTB accesses
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system.cpu.itb.fetch_hits 500020 # ITB hits
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system.cpu.itb.fetch_misses 13 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 500033 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 18 # Number of system calls
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system.cpu.numCycles 1466143 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 500001 # Number of instructions committed
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system.cpu.committedOps 500001 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 474689 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 32 # Number of float alu accesses
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system.cpu.num_func_calls 14357 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls
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system.cpu.num_int_insts 474689 # number of integer instructions
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system.cpu.num_fp_insts 32 # number of float instructions
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system.cpu.num_int_register_reads 654286 # number of times the integer registers were read
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system.cpu.num_int_register_writes 371542 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 32 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
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system.cpu.num_mem_refs 180793 # number of memory refs
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system.cpu.num_load_insts 124443 # Number of load instructions
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system.cpu.num_store_insts 56350 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 1466143 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.Branches 59023 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 500019 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 286.668758 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 180321 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 454 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 397.182819 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 286.668758 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.069987 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.069987 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 454 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 426 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.110840 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 362004 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 362004 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 180321 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 180321 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 180321 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 180321 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 315 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 139 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 139 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 454 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 454 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 454 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 454 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 19530000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 19530000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8618000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 8618000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 28148000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 28148000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 28148000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 28148000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 124435 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 56340 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 180775 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 180775 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002531 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.002531 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002467 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.002511 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.002511 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002511 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002511 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 139 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 454 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 454 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19215000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 19215000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8479000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8479000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27694000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 27694000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27694000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 27694000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002531 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002531 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002467 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002511 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002511 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 264.585152 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 499617 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 403 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1239.744417 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 264.585152 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.129192 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.129192 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 403 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 403 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.196777 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 1000443 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 1000443 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 499617 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 499617 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 499617 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 499617 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 499617 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 499617 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 403 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 403 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 403 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 403 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 403 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 403 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 24986500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 24986500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 24986500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 24986500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 24986500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 24986500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 500020 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 500020 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 500020 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 500020 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 500020 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000806 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000806 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000806 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000806 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000806 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000806 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62001.240695 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 62001.240695 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 62001.240695 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 62001.240695 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 62001.240695 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 62001.240695 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 403 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 403 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 403 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 403 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 403 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 403 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24583500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 24583500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24583500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 24583500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24583500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 24583500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000806 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000806 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000806 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61001.240695 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61001.240695 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61001.240695 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 61001.240695 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61001.240695 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 61001.240695 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 480.680597 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 718 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 264.590924 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 216.089673 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008075 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006595 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.014669 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 718 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 714 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021912 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 7713 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 7713 # Number of data accesses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 139 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 139 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 403 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 403 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 315 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 315 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 403 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 454 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 857 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 403 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 454 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 857 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8270500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 8270500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 23979000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 23979000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18742500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 18742500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 23979000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 27013000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 50992000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 23979000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 27013000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 50992000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 139 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 139 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 403 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 403 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 315 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 315 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 403 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 454 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 857 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 403 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 454 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 857 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.240695 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.240695 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.240695 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59500.583431 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.240695 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59500.583431 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 139 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 139 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 403 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 403 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 315 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 315 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 403 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 857 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 403 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 857 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6880500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6880500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19949000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19949000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15592500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15592500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19949000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22473000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 42422000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19949000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22473000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 42422000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.240695 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.240695 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.240695 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.583431 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.240695 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.583431 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 857 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 718 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 139 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 139 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 403 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 315 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 806 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 908 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 1714 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 25792 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 54848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 857 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 857 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 857 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 428500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 604500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 681000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 718 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 139 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 139 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 718 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 54848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 54848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 857 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 857 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 857 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 857500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4285000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -682,13 +682,14 @@ size=4194304
|
|||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
point_of_coherency=true
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -696,6 +697,13 @@ width=16
|
|||
master=system.physmem.port
|
||||
slave=system.system_port system.l2c.mem_side
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
|
|
|
|||
|
|
@ -15,7 +15,16 @@
|
|||
},
|
||||
"name": "membus",
|
||||
"point_of_coherency": true,
|
||||
"snoop_filter": null,
|
||||
"snoop_filter": {
|
||||
"name": "snoop_filter",
|
||||
"system": "system",
|
||||
"max_capacity": 8388608,
|
||||
"eventq_index": 0,
|
||||
"cxx_class": "SnoopFilter",
|
||||
"path": "system.membus.snoop_filter",
|
||||
"type": "SnoopFilter",
|
||||
"lookup_latency": 1
|
||||
},
|
||||
"forward_latency": 4,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"system": "system",
|
||||
|
|
|
|||
|
|
@ -7,3 +7,5 @@ gzip: stdout: Broken pipe
|
|||
gzip: stdout: Broken pipe
|
||||
|
||||
gzip: stdout: Broken pipe
|
||||
|
||||
gzip: stdout: Broken pipe
|
||||
|
|
|
|||
|
|
@ -1,10 +1,12 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled May 7 2016 13:41:33
|
||||
gem5 started May 7 2016 13:41:50
|
||||
gem5 executing on zizzer, pid 51237
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp
|
||||
gem5 compiled Jun 5 2016 19:50:43
|
||||
gem5 started Jun 5 2016 19:51:07
|
||||
gem5 executing on zizzer, pid 54308
|
||||
command line: /z/stever/hg/gem5/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re /z/stever/hg/gem5/tests/testing/../run.py quick/se/30.eio-mp/alpha/eio/simple-atomic-mp
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -666,13 +666,14 @@ size=4194304
|
|||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
point_of_coherency=true
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -680,6 +681,13 @@ width=16
|
|||
master=system.physmem.port
|
||||
slave=system.system_port system.l2c.mem_side
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
|
|
|
|||
|
|
@ -15,7 +15,16 @@
|
|||
},
|
||||
"name": "membus",
|
||||
"point_of_coherency": true,
|
||||
"snoop_filter": null,
|
||||
"snoop_filter": {
|
||||
"name": "snoop_filter",
|
||||
"system": "system",
|
||||
"max_capacity": 8388608,
|
||||
"eventq_index": 0,
|
||||
"cxx_class": "SnoopFilter",
|
||||
"path": "system.membus.snoop_filter",
|
||||
"type": "SnoopFilter",
|
||||
"lookup_latency": 1
|
||||
},
|
||||
"forward_latency": 4,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"system": "system",
|
||||
|
|
|
|||
|
|
@ -3,6 +3,9 @@ warn: Prefetch instructions in Alpha do not do anything
|
|||
warn: Prefetch instructions in Alpha do not do anything
|
||||
|
||||
gzip: stdout: Broken pipe
|
||||
stdout: Broken pipe
|
||||
|
||||
gzip: stdout: Broken pipe
|
||||
|
||||
gzip: stdout: Broken pipe
|
||||
|
||||
gzip: stdout: Broken pipe
|
||||
|
|
|
|||
|
|
@ -1,10 +1,12 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled May 7 2016 13:41:33
|
||||
gem5 started May 7 2016 13:41:50
|
||||
gem5 executing on zizzer, pid 51213
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
|
||||
gem5 compiled Jun 5 2016 19:50:43
|
||||
gem5 started Jun 5 2016 20:00:38
|
||||
gem5 executing on zizzer, pid 54353
|
||||
command line: /z/stever/hg/gem5/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re /z/stever/hg/gem5/tests/testing/../run.py quick/se/30.eio-mp/alpha/eio/simple-timing-mp
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -16,4 +18,4 @@ main dictionary has 1245 entries
|
|||
49508 bytes wasted
|
||||
49508 bytes wasted
|
||||
49508 bytes wasted
|
||||
>>>>Exiting @ tick 733914500 because a thread reached the max instruction count
|
||||
>>>>Exiting @ tick 734771500 because a thread reached the max instruction count
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
Loading…
Reference in a new issue