test: Make the memtest and memcheck tests functional only
The memtest and memcheck are not designed to test timing. Make them functional only to make ref diffs less noisy in the future. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Andreas Sandberg
parent
39663dc77c
commit
d0ffd2f9b8
File diff suppressed because it is too large
Load diff
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@ -1,83 +0,0 @@
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warn: rounding error > tolerance
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1.250000 rounded to 1
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warn: rounding error > tolerance
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1.250000 rounded to 1
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warn: rounding error > tolerance
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1.250000 rounded to 1
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warn: rounding error > tolerance
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1.250000 rounded to 1
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warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
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warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
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system.cpu1: completed 10000 read, 5477 write accesses @993312
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system.cpu2: completed 10000 read, 5544 write accesses @996128
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system.cpu0: completed 10000 read, 5458 write accesses @996536
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system.cpu3: completed 10000 read, 5546 write accesses @998087
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system.cpu4: completed 10000 read, 5425 write accesses @1001440
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system.cpu7: completed 10000 read, 5725 write accesses @1002290
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system.cpu5: completed 10000 read, 5563 write accesses @1012962
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system.cpu6: completed 10000 read, 5626 write accesses @1026878
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system.cpu2: completed 20000 read, 11014 write accesses @1990757
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system.cpu7: completed 20000 read, 11213 write accesses @1998586
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system.cpu4: completed 20000 read, 10862 write accesses @2006179
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system.cpu1: completed 20000 read, 11109 write accesses @2009839
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system.cpu0: completed 20000 read, 11055 write accesses @2010590
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system.cpu3: completed 20000 read, 11147 write accesses @2011164
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system.cpu6: completed 20000 read, 11117 write accesses @2017946
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system.cpu5: completed 20000 read, 11249 write accesses @2044887
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system.cpu2: completed 30000 read, 16622 write accesses @2998924
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system.cpu7: completed 30000 read, 16766 write accesses @3010333
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system.cpu6: completed 30000 read, 16539 write accesses @3010945
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system.cpu0: completed 30000 read, 16681 write accesses @3021428
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system.cpu3: completed 30000 read, 16672 write accesses @3029534
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system.cpu1: completed 30000 read, 16667 write accesses @3029754
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system.cpu4: completed 30000 read, 16456 write accesses @3042339
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system.cpu5: completed 30000 read, 16900 write accesses @3057264
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system.cpu2: completed 40000 read, 22183 write accesses @4005170
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system.cpu0: completed 40000 read, 22112 write accesses @4017560
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system.cpu4: completed 40000 read, 21876 write accesses @4020474
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system.cpu7: completed 40000 read, 22317 write accesses @4024853
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system.cpu1: completed 40000 read, 22148 write accesses @4025120
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system.cpu3: completed 40000 read, 22291 write accesses @4025351
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system.cpu6: completed 40000 read, 22140 write accesses @4027478
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system.cpu5: completed 40000 read, 22522 write accesses @4053741
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system.cpu0: completed 50000 read, 27630 write accesses @5009643
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system.cpu3: completed 50000 read, 27709 write accesses @5018121
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system.cpu4: completed 50000 read, 27303 write accesses @5018876
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system.cpu2: completed 50000 read, 27685 write accesses @5024854
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system.cpu6: completed 50000 read, 27549 write accesses @5033153
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system.cpu7: completed 50000 read, 27925 write accesses @5035089
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system.cpu1: completed 50000 read, 27578 write accesses @5049644
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system.cpu5: completed 50000 read, 28161 write accesses @5067105
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system.cpu2: completed 60000 read, 33061 write accesses @6010104
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system.cpu3: completed 60000 read, 33252 write accesses @6011525
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system.cpu0: completed 60000 read, 33086 write accesses @6024049
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system.cpu7: completed 60000 read, 33494 write accesses @6044846
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system.cpu5: completed 60000 read, 33651 write accesses @6053289
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system.cpu4: completed 60000 read, 33094 write accesses @6056073
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system.cpu6: completed 60000 read, 33179 write accesses @6057027
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system.cpu1: completed 60000 read, 33046 write accesses @6072711
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system.cpu3: completed 70000 read, 38860 write accesses @7016441
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system.cpu2: completed 70000 read, 38631 write accesses @7032041
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system.cpu0: completed 70000 read, 38682 write accesses @7034544
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system.cpu5: completed 70000 read, 39256 write accesses @7040358
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system.cpu4: completed 70000 read, 38757 write accesses @7060040
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system.cpu6: completed 70000 read, 38734 write accesses @7064210
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system.cpu1: completed 70000 read, 38475 write accesses @7072466
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system.cpu7: completed 70000 read, 39003 write accesses @7074119
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system.cpu2: completed 80000 read, 44130 write accesses @8023565
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system.cpu3: completed 80000 read, 44287 write accesses @8037401
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system.cpu0: completed 80000 read, 44183 write accesses @8039617
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system.cpu7: completed 80000 read, 44442 write accesses @8065674
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system.cpu6: completed 80000 read, 44372 write accesses @8065734
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system.cpu4: completed 80000 read, 44321 write accesses @8067105
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system.cpu5: completed 80000 read, 45042 write accesses @8083622
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system.cpu1: completed 80000 read, 43978 write accesses @8094612
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system.cpu2: completed 90000 read, 49635 write accesses @9035560
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system.cpu0: completed 90000 read, 49823 write accesses @9061621
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system.cpu6: completed 90000 read, 50006 write accesses @9066745
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system.cpu3: completed 90000 read, 49847 write accesses @9070290
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system.cpu7: completed 90000 read, 49983 write accesses @9079579
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system.cpu4: completed 90000 read, 49962 write accesses @9089553
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system.cpu5: completed 90000 read, 50588 write accesses @9109500
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system.cpu1: completed 90000 read, 49692 write accesses @9124269
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system.cpu2: completed 100000 read, 55115 write accesses @10021833
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@ -1,11 +0,0 @@
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Jan 21 2016 14:01:33
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gem5 started Jan 21 2016 14:02:10
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gem5 executing on zizzer, pid 44714
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command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level
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Global frequency set at 1000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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Exiting @ tick 10021833 because maximum number of loads reached
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File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
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@ -1,83 +0,0 @@
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warn: rounding error > tolerance
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1.250000 rounded to 1
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warn: rounding error > tolerance
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1.250000 rounded to 1
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warn: rounding error > tolerance
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1.250000 rounded to 1
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warn: rounding error > tolerance
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1.250000 rounded to 1
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warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
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warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
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system.cpu0: completed 10000 read, 5508 write accesses @738866
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system.cpu3: completed 10000 read, 5629 write accesses @739336
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system.cpu1: completed 10000 read, 5566 write accesses @740014
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system.cpu2: completed 10000 read, 5452 write accesses @740145
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system.cpu7: completed 10000 read, 5492 write accesses @749235
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system.cpu6: completed 10000 read, 5560 write accesses @753933
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system.cpu4: completed 10000 read, 5642 write accesses @754605
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system.cpu5: completed 10000 read, 5631 write accesses @755018
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system.cpu0: completed 20000 read, 11092 write accesses @1475405
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system.cpu3: completed 20000 read, 11222 write accesses @1487700
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system.cpu7: completed 20000 read, 11015 write accesses @1488166
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system.cpu5: completed 20000 read, 11145 write accesses @1493697
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system.cpu1: completed 20000 read, 11221 write accesses @1496331
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system.cpu2: completed 20000 read, 11098 write accesses @1497419
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system.cpu4: completed 20000 read, 11227 write accesses @1505460
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system.cpu6: completed 20000 read, 11297 write accesses @1522234
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system.cpu2: completed 30000 read, 16610 write accesses @2227880
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system.cpu5: completed 30000 read, 16694 write accesses @2227884
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system.cpu7: completed 30000 read, 16430 write accesses @2229017
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system.cpu0: completed 30000 read, 16662 write accesses @2230891
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system.cpu3: completed 30000 read, 16917 write accesses @2234709
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system.cpu1: completed 30000 read, 16703 write accesses @2243507
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system.cpu4: completed 30000 read, 16821 write accesses @2245691
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system.cpu6: completed 30000 read, 16865 write accesses @2274986
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system.cpu2: completed 40000 read, 22186 write accesses @2969541
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system.cpu7: completed 40000 read, 21963 write accesses @2976706
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system.cpu5: completed 40000 read, 22081 write accesses @2977360
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system.cpu0: completed 40000 read, 22245 write accesses @2983600
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system.cpu4: completed 40000 read, 22353 write accesses @2983927
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system.cpu3: completed 40000 read, 22562 write accesses @2989463
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system.cpu1: completed 40000 read, 22203 write accesses @2993172
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system.cpu6: completed 40000 read, 22494 write accesses @3024614
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system.cpu5: completed 50000 read, 27602 write accesses @3707212
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system.cpu2: completed 50000 read, 27827 write accesses @3709656
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system.cpu0: completed 50000 read, 27788 write accesses @3720088
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system.cpu7: completed 50000 read, 27585 write accesses @3729952
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system.cpu3: completed 50000 read, 28225 write accesses @3741336
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system.cpu1: completed 50000 read, 27693 write accesses @3741643
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system.cpu4: completed 50000 read, 28024 write accesses @3746153
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system.cpu6: completed 50000 read, 27944 write accesses @3769575
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system.cpu2: completed 60000 read, 33396 write accesses @4457825
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system.cpu7: completed 60000 read, 33181 write accesses @4461083
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system.cpu0: completed 60000 read, 33524 write accesses @4471000
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system.cpu5: completed 60000 read, 33268 write accesses @4471818
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system.cpu3: completed 60000 read, 33936 write accesses @4490069
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system.cpu1: completed 60000 read, 33523 write accesses @4502736
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system.cpu4: completed 60000 read, 33611 write accesses @4508744
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system.cpu6: completed 60000 read, 33455 write accesses @4516682
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system.cpu2: completed 70000 read, 39052 write accesses @5195824
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system.cpu7: completed 70000 read, 38804 write accesses @5216520
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system.cpu0: completed 70000 read, 39132 write accesses @5221104
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system.cpu5: completed 70000 read, 38946 write accesses @5224763
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system.cpu3: completed 70000 read, 39374 write accesses @5234775
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system.cpu1: completed 70000 read, 39108 write accesses @5247582
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system.cpu4: completed 70000 read, 39073 write accesses @5249170
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system.cpu6: completed 70000 read, 38942 write accesses @5256670
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system.cpu2: completed 80000 read, 44560 write accesses @5927724
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system.cpu5: completed 80000 read, 44421 write accesses @5949764
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system.cpu3: completed 80000 read, 44834 write accesses @5973715
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system.cpu0: completed 80000 read, 44677 write accesses @5979429
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system.cpu7: completed 80000 read, 44408 write accesses @5979747
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system.cpu1: completed 80000 read, 44732 write accesses @5992417
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system.cpu4: completed 80000 read, 44550 write accesses @5998783
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system.cpu6: completed 80000 read, 44539 write accesses @6005684
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system.cpu2: completed 90000 read, 50191 write accesses @6684061
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system.cpu5: completed 90000 read, 50073 write accesses @6691954
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system.cpu3: completed 90000 read, 50398 write accesses @6725412
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system.cpu1: completed 90000 read, 50260 write accesses @6729032
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system.cpu7: completed 90000 read, 49856 write accesses @6729292
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system.cpu0: completed 90000 read, 50333 write accesses @6730369
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system.cpu4: completed 90000 read, 50097 write accesses @6738499
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system.cpu6: completed 90000 read, 50144 write accesses @6754135
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system.cpu5: completed 100000 read, 55687 write accesses @7436579
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@ -1,11 +0,0 @@
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Jan 21 2016 14:06:59
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gem5 started Jan 21 2016 14:07:35
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gem5 executing on zizzer, pid 50082
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command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
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Global frequency set at 1000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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Exiting @ tick 7436579 because maximum number of loads reached
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File diff suppressed because it is too large
Load diff
File diff suppressed because one or more lines are too long
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@ -1,83 +0,0 @@
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warn: rounding error > tolerance
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1.250000 rounded to 1
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warn: rounding error > tolerance
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1.250000 rounded to 1
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warn: rounding error > tolerance
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1.250000 rounded to 1
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warn: rounding error > tolerance
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1.250000 rounded to 1
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warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
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warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
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system.cpu6: completed 10000 read, 5414 write accesses @600125
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system.cpu3: completed 10000 read, 5553 write accesses @601190
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system.cpu5: completed 10000 read, 5522 write accesses @610184
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system.cpu2: completed 10000 read, 5553 write accesses @610543
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system.cpu1: completed 10000 read, 5553 write accesses @610637
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system.cpu7: completed 10000 read, 5548 write accesses @613961
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system.cpu4: completed 10000 read, 5672 write accesses @625096
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system.cpu0: completed 10000 read, 5578 write accesses @625819
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system.cpu3: completed 20000 read, 11222 write accesses @1210787
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system.cpu2: completed 20000 read, 11113 write accesses @1216356
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system.cpu6: completed 20000 read, 11010 write accesses @1217399
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system.cpu7: completed 20000 read, 10915 write accesses @1224868
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system.cpu1: completed 20000 read, 11109 write accesses @1227113
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system.cpu5: completed 20000 read, 11172 write accesses @1228690
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system.cpu0: completed 20000 read, 11076 write accesses @1241151
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system.cpu4: completed 20000 read, 11317 write accesses @1252011
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system.cpu3: completed 30000 read, 16793 write accesses @1808510
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system.cpu2: completed 30000 read, 16719 write accesses @1811663
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system.cpu6: completed 30000 read, 16607 write accesses @1829544
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system.cpu1: completed 30000 read, 16700 write accesses @1832567
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system.cpu7: completed 30000 read, 16359 write accesses @1837933
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system.cpu5: completed 30000 read, 16722 write accesses @1842350
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system.cpu0: completed 30000 read, 16567 write accesses @1855038
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system.cpu4: completed 30000 read, 16806 write accesses @1868367
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system.cpu2: completed 40000 read, 22363 write accesses @2439233
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system.cpu3: completed 40000 read, 22637 write accesses @2443609
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system.cpu6: completed 40000 read, 22031 write accesses @2444868
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system.cpu1: completed 40000 read, 22136 write accesses @2454083
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system.cpu7: completed 40000 read, 22019 write accesses @2462426
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system.cpu0: completed 40000 read, 22102 write accesses @2464718
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system.cpu5: completed 40000 read, 22391 write accesses @2467086
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system.cpu4: completed 40000 read, 22274 write accesses @2476956
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system.cpu2: completed 50000 read, 27787 write accesses @3042124
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system.cpu6: completed 50000 read, 27603 write accesses @3052498
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system.cpu3: completed 50000 read, 28345 write accesses @3055004
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system.cpu1: completed 50000 read, 27635 write accesses @3062785
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system.cpu7: completed 50000 read, 27487 write accesses @3068425
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system.cpu0: completed 50000 read, 27611 write accesses @3068440
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system.cpu5: completed 50000 read, 27987 write accesses @3072420
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system.cpu4: completed 50000 read, 27913 write accesses @3101440
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system.cpu2: completed 60000 read, 33280 write accesses @3652049
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system.cpu3: completed 60000 read, 33864 write accesses @3668867
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system.cpu0: completed 60000 read, 33089 write accesses @3675395
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system.cpu7: completed 60000 read, 33087 write accesses @3676487
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system.cpu1: completed 60000 read, 33182 write accesses @3678705
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system.cpu6: completed 60000 read, 33377 write accesses @3680817
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system.cpu5: completed 60000 read, 33479 write accesses @3694370
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system.cpu4: completed 60000 read, 33302 write accesses @3701614
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system.cpu2: completed 70000 read, 38766 write accesses @4250473
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system.cpu0: completed 70000 read, 38578 write accesses @4284716
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system.cpu3: completed 70000 read, 39510 write accesses @4292337
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system.cpu1: completed 70000 read, 38741 write accesses @4292636
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system.cpu6: completed 70000 read, 39114 write accesses @4297860
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system.cpu7: completed 70000 read, 38662 write accesses @4300070
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system.cpu5: completed 70000 read, 38961 write accesses @4315101
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system.cpu4: completed 70000 read, 38876 write accesses @4320121
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system.cpu2: completed 80000 read, 44272 write accesses @4868351
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system.cpu3: completed 80000 read, 45140 write accesses @4896693
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system.cpu6: completed 80000 read, 44453 write accesses @4900088
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system.cpu0: completed 80000 read, 44159 write accesses @4900273
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system.cpu1: completed 80000 read, 44332 write accesses @4908589
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system.cpu7: completed 80000 read, 44332 write accesses @4918776
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system.cpu5: completed 80000 read, 44375 write accesses @4922197
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system.cpu4: completed 80000 read, 44529 write accesses @4935812
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system.cpu2: completed 90000 read, 49875 write accesses @5488123
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system.cpu3: completed 90000 read, 50614 write accesses @5502669
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system.cpu0: completed 90000 read, 49682 write accesses @5505213
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system.cpu6: completed 90000 read, 50248 write accesses @5520798
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system.cpu1: completed 90000 read, 49915 write accesses @5525318
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system.cpu7: completed 90000 read, 49900 write accesses @5530195
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system.cpu5: completed 90000 read, 50114 write accesses @5537728
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system.cpu4: completed 90000 read, 50125 write accesses @5550036
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system.cpu2: completed 100000 read, 55518 write accesses @6099346
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@ -1,11 +0,0 @@
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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||||
|
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gem5 compiled Jan 21 2016 14:12:23
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gem5 started Jan 21 2016 14:12:59
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gem5 executing on zizzer, pid 55396
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command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
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Global frequency set at 1000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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Exiting @ tick 6099346 because maximum number of loads reached
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File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
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@ -1,83 +0,0 @@
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warn: rounding error > tolerance
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1.250000 rounded to 1
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warn: rounding error > tolerance
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1.250000 rounded to 1
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||||
warn: rounding error > tolerance
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1.250000 rounded to 1
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||||
warn: rounding error > tolerance
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1.250000 rounded to 1
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warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
|
||||
system.cpu6: completed 10000 read, 5442 write accesses @464151
|
||||
system.cpu5: completed 10000 read, 5565 write accesses @467904
|
||||
system.cpu1: completed 10000 read, 5530 write accesses @472727
|
||||
system.cpu4: completed 10000 read, 5671 write accesses @474893
|
||||
system.cpu2: completed 10000 read, 5702 write accesses @475545
|
||||
system.cpu3: completed 10000 read, 5626 write accesses @475848
|
||||
system.cpu7: completed 10000 read, 5688 write accesses @476316
|
||||
system.cpu0: completed 10000 read, 5652 write accesses @477657
|
||||
system.cpu6: completed 20000 read, 11069 write accesses @933991
|
||||
system.cpu4: completed 20000 read, 11035 write accesses @941133
|
||||
system.cpu1: completed 20000 read, 11144 write accesses @942887
|
||||
system.cpu5: completed 20000 read, 11075 write accesses @943473
|
||||
system.cpu7: completed 20000 read, 11122 write accesses @946462
|
||||
system.cpu2: completed 20000 read, 11251 write accesses @952011
|
||||
system.cpu3: completed 20000 read, 11149 write accesses @953947
|
||||
system.cpu0: completed 20000 read, 11405 write accesses @958457
|
||||
system.cpu4: completed 30000 read, 16671 write accesses @1411581
|
||||
system.cpu5: completed 30000 read, 16602 write accesses @1411822
|
||||
system.cpu7: completed 30000 read, 16713 write accesses @1419018
|
||||
system.cpu6: completed 30000 read, 16615 write accesses @1420265
|
||||
system.cpu3: completed 30000 read, 16709 write accesses @1421765
|
||||
system.cpu1: completed 30000 read, 16889 write accesses @1427949
|
||||
system.cpu2: completed 30000 read, 16908 write accesses @1434738
|
||||
system.cpu0: completed 30000 read, 17031 write accesses @1444971
|
||||
system.cpu5: completed 40000 read, 22172 write accesses @1880249
|
||||
system.cpu3: completed 40000 read, 22160 write accesses @1893274
|
||||
system.cpu6: completed 40000 read, 22289 write accesses @1896273
|
||||
system.cpu1: completed 40000 read, 22624 write accesses @1896553
|
||||
system.cpu4: completed 40000 read, 22359 write accesses @1896744
|
||||
system.cpu7: completed 40000 read, 22432 write accesses @1900299
|
||||
system.cpu2: completed 40000 read, 22368 write accesses @1910277
|
||||
system.cpu0: completed 40000 read, 22621 write accesses @1917733
|
||||
system.cpu5: completed 50000 read, 27506 write accesses @2349190
|
||||
system.cpu6: completed 50000 read, 27893 write accesses @2366731
|
||||
system.cpu7: completed 50000 read, 27846 write accesses @2369147
|
||||
system.cpu3: completed 50000 read, 27646 write accesses @2369997
|
||||
system.cpu1: completed 50000 read, 27990 write accesses @2371485
|
||||
system.cpu2: completed 50000 read, 27913 write accesses @2374199
|
||||
system.cpu4: completed 50000 read, 27983 write accesses @2375243
|
||||
system.cpu0: completed 50000 read, 28279 write accesses @2400165
|
||||
system.cpu5: completed 60000 read, 33080 write accesses @2828614
|
||||
system.cpu3: completed 60000 read, 33257 write accesses @2839097
|
||||
system.cpu1: completed 60000 read, 33556 write accesses @2841959
|
||||
system.cpu6: completed 60000 read, 33572 write accesses @2843628
|
||||
system.cpu7: completed 60000 read, 33379 write accesses @2844087
|
||||
system.cpu2: completed 60000 read, 33471 write accesses @2846336
|
||||
system.cpu4: completed 60000 read, 33614 write accesses @2862059
|
||||
system.cpu0: completed 60000 read, 33892 write accesses @2874908
|
||||
system.cpu5: completed 70000 read, 38668 write accesses @3302644
|
||||
system.cpu3: completed 70000 read, 38773 write accesses @3312258
|
||||
system.cpu7: completed 70000 read, 38856 write accesses @3313701
|
||||
system.cpu1: completed 70000 read, 39110 write accesses @3314841
|
||||
system.cpu6: completed 70000 read, 39295 write accesses @3319370
|
||||
system.cpu2: completed 70000 read, 39264 write accesses @3327548
|
||||
system.cpu4: completed 70000 read, 39102 write accesses @3335340
|
||||
system.cpu0: completed 70000 read, 39326 write accesses @3351991
|
||||
system.cpu5: completed 80000 read, 44247 write accesses @3772436
|
||||
system.cpu3: completed 80000 read, 44360 write accesses @3783174
|
||||
system.cpu1: completed 80000 read, 44568 write accesses @3784069
|
||||
system.cpu6: completed 80000 read, 44689 write accesses @3792375
|
||||
system.cpu2: completed 80000 read, 44751 write accesses @3797997
|
||||
system.cpu7: completed 80000 read, 44339 write accesses @3798680
|
||||
system.cpu4: completed 80000 read, 44675 write accesses @3804996
|
||||
system.cpu0: completed 80000 read, 44775 write accesses @3826542
|
||||
system.cpu5: completed 90000 read, 49884 write accesses @4250135
|
||||
system.cpu3: completed 90000 read, 49904 write accesses @4252427
|
||||
system.cpu6: completed 90000 read, 50171 write accesses @4263343
|
||||
system.cpu1: completed 90000 read, 50197 write accesses @4265783
|
||||
system.cpu4: completed 90000 read, 50286 write accesses @4279784
|
||||
system.cpu7: completed 90000 read, 50179 write accesses @4284358
|
||||
system.cpu2: completed 90000 read, 50246 write accesses @4285069
|
||||
system.cpu0: completed 90000 read, 50200 write accesses @4290832
|
||||
system.cpu3: completed 100000 read, 55486 write accesses @4722948
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 21 2016 13:56:08
|
||||
gem5 started Jan 21 2016 13:56:42
|
||||
gem5 executing on zizzer, pid 39366
|
||||
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
|
||||
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 4722948 because maximum number of loads reached
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,83 +0,0 @@
|
|||
warn: rounding error > tolerance
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
1.250000 rounded to 1
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
|
||||
system.cpu0: completed 10000 read, 5571 write accesses @752421
|
||||
system.cpu5: completed 10000 read, 5518 write accesses @761420
|
||||
system.cpu4: completed 10000 read, 5515 write accesses @761995
|
||||
system.cpu1: completed 10000 read, 5545 write accesses @770340
|
||||
system.cpu7: completed 10000 read, 5536 write accesses @773657
|
||||
system.cpu3: completed 10000 read, 5634 write accesses @778030
|
||||
system.cpu6: completed 10000 read, 5641 write accesses @782742
|
||||
system.cpu2: completed 10000 read, 5665 write accesses @783711
|
||||
system.cpu4: completed 20000 read, 10969 write accesses @1519216
|
||||
system.cpu1: completed 20000 read, 11064 write accesses @1534419
|
||||
system.cpu0: completed 20000 read, 11217 write accesses @1534668
|
||||
system.cpu5: completed 20000 read, 11140 write accesses @1535434
|
||||
system.cpu3: completed 20000 read, 11134 write accesses @1543210
|
||||
system.cpu7: completed 20000 read, 11062 write accesses @1544582
|
||||
system.cpu2: completed 20000 read, 11296 write accesses @1546737
|
||||
system.cpu6: completed 20000 read, 11124 write accesses @1559617
|
||||
system.cpu4: completed 30000 read, 16555 write accesses @2275552
|
||||
system.cpu0: completed 30000 read, 16802 write accesses @2300818
|
||||
system.cpu1: completed 30000 read, 16697 write accesses @2303774
|
||||
system.cpu7: completed 30000 read, 16517 write accesses @2305690
|
||||
system.cpu3: completed 30000 read, 16547 write accesses @2312240
|
||||
system.cpu2: completed 30000 read, 16835 write accesses @2313552
|
||||
system.cpu5: completed 30000 read, 16782 write accesses @2322286
|
||||
system.cpu6: completed 30000 read, 16591 write accesses @2331245
|
||||
system.cpu4: completed 40000 read, 22197 write accesses @3047291
|
||||
system.cpu1: completed 40000 read, 22254 write accesses @3080372
|
||||
system.cpu5: completed 40000 read, 22355 write accesses @3084185
|
||||
system.cpu2: completed 40000 read, 22372 write accesses @3086032
|
||||
system.cpu3: completed 40000 read, 22166 write accesses @3086541
|
||||
system.cpu7: completed 40000 read, 22080 write accesses @3086779
|
||||
system.cpu0: completed 40000 read, 22498 write accesses @3087817
|
||||
system.cpu6: completed 40000 read, 22224 write accesses @3104629
|
||||
system.cpu4: completed 50000 read, 27651 write accesses @3808654
|
||||
system.cpu3: completed 50000 read, 27619 write accesses @3840689
|
||||
system.cpu2: completed 50000 read, 27948 write accesses @3842577
|
||||
system.cpu5: completed 50000 read, 27826 write accesses @3846119
|
||||
system.cpu1: completed 50000 read, 27919 write accesses @3856612
|
||||
system.cpu0: completed 50000 read, 27967 write accesses @3862756
|
||||
system.cpu7: completed 50000 read, 27662 write accesses @3864061
|
||||
system.cpu6: completed 50000 read, 27847 write accesses @3874888
|
||||
system.cpu4: completed 60000 read, 33289 write accesses @4579441
|
||||
system.cpu5: completed 60000 read, 33335 write accesses @4610406
|
||||
system.cpu2: completed 60000 read, 33617 write accesses @4620490
|
||||
system.cpu3: completed 60000 read, 33206 write accesses @4625510
|
||||
system.cpu0: completed 60000 read, 33552 write accesses @4626939
|
||||
system.cpu1: completed 60000 read, 33496 write accesses @4630810
|
||||
system.cpu7: completed 60000 read, 33243 write accesses @4635014
|
||||
system.cpu6: completed 60000 read, 33291 write accesses @4642013
|
||||
system.cpu4: completed 70000 read, 39076 write accesses @5364272
|
||||
system.cpu5: completed 70000 read, 38991 write accesses @5366681
|
||||
system.cpu2: completed 70000 read, 39149 write accesses @5384888
|
||||
system.cpu7: completed 70000 read, 38759 write accesses @5402266
|
||||
system.cpu0: completed 70000 read, 39059 write accesses @5403051
|
||||
system.cpu3: completed 70000 read, 38849 write accesses @5406812
|
||||
system.cpu1: completed 70000 read, 39130 write accesses @5408848
|
||||
system.cpu6: completed 70000 read, 38893 write accesses @5418265
|
||||
system.cpu5: completed 80000 read, 44444 write accesses @6131768
|
||||
system.cpu4: completed 80000 read, 44664 write accesses @6143607
|
||||
system.cpu2: completed 80000 read, 44926 write accesses @6155809
|
||||
system.cpu7: completed 80000 read, 44252 write accesses @6163509
|
||||
system.cpu0: completed 80000 read, 44649 write accesses @6169693
|
||||
system.cpu1: completed 80000 read, 44753 write accesses @6180727
|
||||
system.cpu3: completed 80000 read, 44403 write accesses @6182843
|
||||
system.cpu6: completed 80000 read, 44456 write accesses @6189312
|
||||
system.cpu5: completed 90000 read, 50182 write accesses @6910395
|
||||
system.cpu7: completed 90000 read, 49674 write accesses @6913652
|
||||
system.cpu2: completed 90000 read, 50514 write accesses @6919272
|
||||
system.cpu0: completed 90000 read, 50099 write accesses @6923145
|
||||
system.cpu4: completed 90000 read, 50279 write accesses @6924731
|
||||
system.cpu1: completed 90000 read, 50283 write accesses @6951674
|
||||
system.cpu3: completed 90000 read, 50165 write accesses @6956300
|
||||
system.cpu6: completed 90000 read, 50051 write accesses @6959913
|
||||
system.cpu5: completed 100000 read, 55705 write accesses @7678882
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 21 2016 13:49:21
|
||||
gem5 started Jan 21 2016 13:50:03
|
||||
gem5 executing on zizzer, pid 34009
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby
|
||||
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 7678882 because maximum number of loads reached
|
||||
|
|
@ -1,798 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.007679 # Number of seconds simulated
|
||||
sim_ticks 7678882 # Number of ticks simulated
|
||||
final_tick 7678882 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 172641 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 467856 # Number of bytes of host memory used
|
||||
host_seconds 44.48 # Real time elapsed on the host
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39687936 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_read::total 39687936 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 39686592 # Number of bytes written to this memory
|
||||
system.mem_ctrls.bytes_written::total 39686592 # Number of bytes written to this memory
|
||||
system.mem_ctrls.num_reads::ruby.dir_cntrl0 620124 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_reads::total 620124 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 620103 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 620103 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 5168452387 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 5168452387 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 5168277361 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 5168277361 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 10336729748 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 10336729748 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 620135 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 620103 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 620135 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 620103 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 38814144 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 874432 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 39178240 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 39688640 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 39686592 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.servicedByWrQ 13663 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 7899 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrls.perBankRdBursts::0 76107 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 76000 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 75939 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 75805 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 75453 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 75733 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 75604 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 75830 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 76774 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 76710 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 76671 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 76539 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 76175 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 76456 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 76301 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 76534 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 1460 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 7678686 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::6 620135 # Read request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::6 620103 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 19 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 184 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 983 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::3 3255 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::4 7746 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::5 15554 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::6 26175 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::7 37685 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::8 47133 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::9 52357 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::10 54286 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::11 51593 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::12 44542 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::13 37610 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::14 32124 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::15 28105 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::16 25786 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::17 24080 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::18 22962 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::19 21687 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::20 19844 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::21 17181 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::22 13705 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::23 9888 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::24 6282 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::25 3447 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::26 1554 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::27 523 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::28 143 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::29 35 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::30 4 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 18 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::33 122 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::34 330 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::35 810 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::36 1760 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::37 3235 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::38 5017 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::39 8822 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::40 11772 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::41 14646 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::42 17978 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::43 20446 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::44 22363 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::45 23166 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::46 24550 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::47 25656 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::48 26802 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::49 28849 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::50 30890 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::51 32798 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::52 34545 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::53 37340 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::54 41995 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::55 65965 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::56 58297 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::57 24690 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::58 18242 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::59 13049 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::60 8033 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::61 4660 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 2636 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 2690 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 246538 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 316.347760 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 240.406220 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 226.949392 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 34759 14.10% 14.10% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 76086 30.86% 44.96% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 46939 19.04% 64.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 34923 14.17% 78.17% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 24196 9.81% 87.98% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 14479 5.87% 93.85% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 7763 3.15% 97.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 3969 1.61% 98.61% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 3424 1.39% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 246538 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 38260 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 15.850732 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 8.293167 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 11.882732 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::0-3 13623 35.61% 35.61% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::4-7 1256 3.28% 38.89% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::8-11 278 0.73% 39.62% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::12-15 163 0.43% 40.04% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-19 3078 8.04% 48.09% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::20-23 6049 15.81% 63.90% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::24-27 5774 15.09% 78.99% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::28-31 6360 16.62% 95.61% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::32-35 1623 4.24% 99.85% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::36-39 55 0.14% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::80-83 1 0.00% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 38260 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 38260 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 38260 100.00% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 38260 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 114599292 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 126122241 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 3032355 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 188.96 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 207.96 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 5054.66 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 5102.08 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 5168.54 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 5168.28 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 79.35 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 39.49 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 39.86 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 18.26 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 53.74 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 369343 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 602743 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 60.90 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 98.45 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 6.19 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 79.77 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 1863396360 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 1035220200 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 7566948480 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.writeEnergy 6345547776 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_0.refreshEnergy 501440160 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 5232384540 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 16562400 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 22561499916 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 2938.732659 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 10 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 256360 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 7420933 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_1.refreshEnergy 501440160 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_1.actBackEnergy 165908304 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 4460811600 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 5128160064 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 667.969052 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 7420896 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::REF 256360 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.cpu_clk_domain.clock 1 # Clock period in ticks
|
||||
system.cpu0.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.cpu0.num_reads 99754 # number of read accesses completed
|
||||
system.cpu0.num_writes 55550 # number of write accesses completed
|
||||
system.cpu1.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.cpu1.num_reads 99722 # number of read accesses completed
|
||||
system.cpu1.num_writes 55422 # number of write accesses completed
|
||||
system.cpu2.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.cpu2.num_reads 99859 # number of read accesses completed
|
||||
system.cpu2.num_writes 56114 # number of write accesses completed
|
||||
system.cpu3.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.cpu3.num_reads 99399 # number of read accesses completed
|
||||
system.cpu3.num_writes 55238 # number of write accesses completed
|
||||
system.cpu4.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.cpu4.num_reads 99564 # number of read accesses completed
|
||||
system.cpu4.num_writes 55685 # number of write accesses completed
|
||||
system.cpu5.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.cpu5.num_reads 100000 # number of read accesses completed
|
||||
system.cpu5.num_writes 55705 # number of write accesses completed
|
||||
system.cpu6.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.cpu6.num_reads 99381 # number of read accesses completed
|
||||
system.cpu6.num_writes 55293 # number of write accesses completed
|
||||
system.cpu7.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.cpu7.num_reads 99930 # number of read accesses completed
|
||||
system.cpu7.num_writes 55169 # number of write accesses completed
|
||||
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.delayHist::bucket_size 32 # delay histogram for all message
|
||||
system.ruby.delayHist::max_bucket 319 # delay histogram for all message
|
||||
system.ruby.delayHist::samples 1260795 # delay histogram for all message
|
||||
system.ruby.delayHist::mean 2.261395 # delay histogram for all message
|
||||
system.ruby.delayHist::stdev 7.584807 # delay histogram for all message
|
||||
system.ruby.delayHist | 1243450 98.62% 98.62% | 11474 0.91% 99.53% | 5225 0.41% 99.95% | 542 0.04% 99.99% | 89 0.01% 100.00% | 15 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
|
||||
system.ruby.delayHist::total 1260795 # delay histogram for all message
|
||||
system.ruby.outstanding_req_hist_seqr::bucket_size 2
|
||||
system.ruby.outstanding_req_hist_seqr::max_bucket 19
|
||||
system.ruby.outstanding_req_hist_seqr::samples 628584
|
||||
system.ruby.outstanding_req_hist_seqr::mean 15.998449
|
||||
system.ruby.outstanding_req_hist_seqr::gmean 15.997188
|
||||
system.ruby.outstanding_req_hist_seqr::stdev 0.125710
|
||||
system.ruby.outstanding_req_hist_seqr | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 31 0.00% 0.02% | 628449 99.98% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist_seqr::total 628584
|
||||
system.ruby.latency_hist_seqr::bucket_size 512
|
||||
system.ruby.latency_hist_seqr::max_bucket 5119
|
||||
system.ruby.latency_hist_seqr::samples 628456
|
||||
system.ruby.latency_hist_seqr::mean 1563.811233
|
||||
system.ruby.latency_hist_seqr::gmean 1541.792365
|
||||
system.ruby.latency_hist_seqr::stdev 262.265559
|
||||
system.ruby.latency_hist_seqr | 77 0.01% 0.01% | 6104 0.97% 0.98% | 298062 47.43% 48.41% | 297436 47.33% 95.74% | 26586 4.23% 99.97% | 191 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist_seqr::total 628456
|
||||
system.ruby.miss_latency_hist_seqr::bucket_size 512
|
||||
system.ruby.miss_latency_hist_seqr::max_bucket 5119
|
||||
system.ruby.miss_latency_hist_seqr::samples 628456
|
||||
system.ruby.miss_latency_hist_seqr::mean 1563.811233
|
||||
system.ruby.miss_latency_hist_seqr::gmean 1541.792365
|
||||
system.ruby.miss_latency_hist_seqr::stdev 262.265559
|
||||
system.ruby.miss_latency_hist_seqr | 77 0.01% 0.01% | 6104 0.97% 0.98% | 298062 47.43% 48.41% | 297436 47.33% 95.74% | 26586 4.23% 99.97% | 191 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist_seqr::total 628456
|
||||
system.ruby.L1Cache.incomplete_times_seqr 8337
|
||||
system.ruby.Directory.incomplete_times_seqr 620116
|
||||
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 78526 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 78526 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl1.cacheMemory.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl1.cacheMemory.demand_misses 78474 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl1.cacheMemory.demand_accesses 78474 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl1.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl2.cacheMemory.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl2.cacheMemory.demand_misses 78844 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl2.cacheMemory.demand_accesses 78844 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl2.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl3.cacheMemory.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl3.cacheMemory.demand_misses 78573 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl3.cacheMemory.demand_accesses 78573 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl3.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl4.cacheMemory.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl4.cacheMemory.demand_misses 78575 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl4.cacheMemory.demand_accesses 78575 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl4.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl5.cacheMemory.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl5.cacheMemory.demand_misses 78529 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl5.cacheMemory.demand_accesses 78529 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl5.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl6.cacheMemory.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl6.cacheMemory.demand_misses 78440 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl6.cacheMemory.demand_accesses 78440 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl6.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl7.cacheMemory.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl7.cacheMemory.demand_misses 78515 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl7.cacheMemory.demand_accesses 78515 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.l1_cntrl7.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers0.percent_links_utilized 5.128100
|
||||
system.ruby.network.routers0.msg_count.Control::2 78526
|
||||
system.ruby.network.routers0.msg_count.Data::2 77981
|
||||
system.ruby.network.routers0.msg_count.Response_Data::4 79531
|
||||
system.ruby.network.routers0.msg_count.Writeback_Control::3 78989
|
||||
system.ruby.network.routers0.msg_bytes.Control::2 628208
|
||||
system.ruby.network.routers0.msg_bytes.Data::2 5614632
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 5726232
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 631912
|
||||
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers1.percent_links_utilized 5.125007
|
||||
system.ruby.network.routers1.msg_count.Control::2 78474
|
||||
system.ruby.network.routers1.msg_count.Data::2 77933
|
||||
system.ruby.network.routers1.msg_count.Response_Data::4 79484
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::3 78946
|
||||
system.ruby.network.routers1.msg_bytes.Control::2 627792
|
||||
system.ruby.network.routers1.msg_bytes.Data::2 5611176
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 5722848
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 631568
|
||||
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers2.percent_links_utilized 5.149581
|
||||
system.ruby.network.routers2.msg_count.Control::2 78844
|
||||
system.ruby.network.routers2.msg_count.Data::2 78287
|
||||
system.ruby.network.routers2.msg_count.Response_Data::4 79885
|
||||
system.ruby.network.routers2.msg_count.Writeback_Control::3 79329
|
||||
system.ruby.network.routers2.msg_bytes.Control::2 630752
|
||||
system.ruby.network.routers2.msg_bytes.Data::2 5636664
|
||||
system.ruby.network.routers2.msg_bytes.Response_Data::4 5751720
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 634632
|
||||
system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers3.percent_links_utilized 5.132918
|
||||
system.ruby.network.routers3.msg_count.Control::2 78573
|
||||
system.ruby.network.routers3.msg_count.Data::2 78015
|
||||
system.ruby.network.routers3.msg_count.Response_Data::4 79645
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::3 79090
|
||||
system.ruby.network.routers3.msg_bytes.Control::2 628584
|
||||
system.ruby.network.routers3.msg_bytes.Data::2 5617080
|
||||
system.ruby.network.routers3.msg_bytes.Response_Data::4 5734440
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::3 632720
|
||||
system.ruby.network.routers4.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers4.percent_links_utilized 5.131284
|
||||
system.ruby.network.routers4.msg_count.Control::2 78575
|
||||
system.ruby.network.routers4.msg_count.Data::2 78023
|
||||
system.ruby.network.routers4.msg_count.Response_Data::4 79587
|
||||
system.ruby.network.routers4.msg_count.Writeback_Control::3 79036
|
||||
system.ruby.network.routers4.msg_bytes.Control::2 628600
|
||||
system.ruby.network.routers4.msg_bytes.Data::2 5617656
|
||||
system.ruby.network.routers4.msg_bytes.Response_Data::4 5730264
|
||||
system.ruby.network.routers4.msg_bytes.Writeback_Control::3 632288
|
||||
system.ruby.network.routers5.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers5.percent_links_utilized 5.129285
|
||||
system.ruby.network.routers5.msg_count.Control::2 78525
|
||||
system.ruby.network.routers5.msg_count.Data::2 77953
|
||||
system.ruby.network.routers5.msg_count.Response_Data::4 79596
|
||||
system.ruby.network.routers5.msg_count.Writeback_Control::3 79024
|
||||
system.ruby.network.routers5.msg_bytes.Control::2 628200
|
||||
system.ruby.network.routers5.msg_bytes.Data::2 5612616
|
||||
system.ruby.network.routers5.msg_bytes.Response_Data::4 5730912
|
||||
system.ruby.network.routers5.msg_bytes.Writeback_Control::3 632192
|
||||
system.ruby.network.routers6.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers6.percent_links_utilized 5.123636
|
||||
system.ruby.network.routers6.msg_count.Control::2 78440
|
||||
system.ruby.network.routers6.msg_count.Data::2 77859
|
||||
system.ruby.network.routers6.msg_count.Response_Data::4 79516
|
||||
system.ruby.network.routers6.msg_count.Writeback_Control::3 78937
|
||||
system.ruby.network.routers6.msg_bytes.Control::2 627520
|
||||
system.ruby.network.routers6.msg_bytes.Data::2 5605848
|
||||
system.ruby.network.routers6.msg_bytes.Response_Data::4 5725152
|
||||
system.ruby.network.routers6.msg_bytes.Writeback_Control::3 631496
|
||||
system.ruby.network.routers7.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers7.percent_links_utilized 5.127709
|
||||
system.ruby.network.routers7.msg_count.Control::2 78515
|
||||
system.ruby.network.routers7.msg_count.Data::2 77951
|
||||
system.ruby.network.routers7.msg_count.Response_Data::4 79549
|
||||
system.ruby.network.routers7.msg_count.Writeback_Control::3 78988
|
||||
system.ruby.network.routers7.msg_bytes.Control::2 628120
|
||||
system.ruby.network.routers7.msg_bytes.Data::2 5612472
|
||||
system.ruby.network.routers7.msg_bytes.Response_Data::4 5727528
|
||||
system.ruby.network.routers7.msg_bytes.Writeback_Control::3 631904
|
||||
system.ruby.network.routers8.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers8.percent_links_utilized 40.558977
|
||||
system.ruby.network.routers8.msg_count.Control::2 628472
|
||||
system.ruby.network.routers8.msg_count.Data::2 624002
|
||||
system.ruby.network.routers8.msg_count.Response_Data::4 620120
|
||||
system.ruby.network.routers8.msg_count.Writeback_Control::3 632339
|
||||
system.ruby.network.routers8.msg_bytes.Control::2 5027776
|
||||
system.ruby.network.routers8.msg_bytes.Data::2 44928144
|
||||
system.ruby.network.routers8.msg_bytes.Response_Data::4 44648640
|
||||
system.ruby.network.routers8.msg_bytes.Writeback_Control::3 5058712
|
||||
system.ruby.network.routers9.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers9.percent_links_utilized 9.067388
|
||||
system.ruby.network.routers9.msg_count.Control::2 628472
|
||||
system.ruby.network.routers9.msg_count.Data::2 624002
|
||||
system.ruby.network.routers9.msg_count.Response_Data::4 628456
|
||||
system.ruby.network.routers9.msg_count.Writeback_Control::3 632339
|
||||
system.ruby.network.routers9.msg_bytes.Control::2 5027776
|
||||
system.ruby.network.routers9.msg_bytes.Data::2 44928144
|
||||
system.ruby.network.routers9.msg_bytes.Response_Data::4 45248832
|
||||
system.ruby.network.routers9.msg_bytes.Writeback_Control::3 5058712
|
||||
system.ruby.network.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.msg_count.Control 1885416
|
||||
system.ruby.network.msg_count.Data 1872006
|
||||
system.ruby.network.msg_count.Response_Data 1885369
|
||||
system.ruby.network.msg_count.Writeback_Control 1897017
|
||||
system.ruby.network.msg_byte.Control 15083328
|
||||
system.ruby.network.msg_byte.Data 134784432
|
||||
system.ruby.network.msg_byte.Response_Data 135746568
|
||||
system.ruby.network.msg_byte.Writeback_Control 15176136
|
||||
system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.115953
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 78523
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 78989
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5653656
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 631912
|
||||
system.ruby.network.routers0.throttle1.link_utilization 5.140247
|
||||
system.ruby.network.routers0.throttle1.msg_count.Control::2 78526
|
||||
system.ruby.network.routers0.throttle1.msg_count.Data::2 77981
|
||||
system.ruby.network.routers0.throttle1.msg_count.Response_Data::4 1008
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 628208
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 5614632
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4 72576
|
||||
system.ruby.network.routers1.throttle0.link_utilization 5.112626
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Data::4 78471
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::3 78946
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::4 5649912
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::3 631568
|
||||
system.ruby.network.routers1.throttle1.link_utilization 5.137388
|
||||
system.ruby.network.routers1.throttle1.msg_count.Control::2 78474
|
||||
system.ruby.network.routers1.throttle1.msg_count.Data::2 77933
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1013
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Control::2 627792
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Data::2 5611176
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 72936
|
||||
system.ruby.network.routers2.throttle0.link_utilization 5.136920
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 78843
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 79329
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5676696
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 634632
|
||||
system.ruby.network.routers2.throttle1.link_utilization 5.162242
|
||||
system.ruby.network.routers2.throttle1.msg_count.Control::2 78844
|
||||
system.ruby.network.routers2.throttle1.msg_count.Data::2 78287
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 1042
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 630752
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Data::2 5636664
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 75024
|
||||
system.ruby.network.routers3.throttle0.link_utilization 5.119365
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 78570
|
||||
system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::3 79090
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 5657040
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::3 632720
|
||||
system.ruby.network.routers3.throttle1.link_utilization 5.146472
|
||||
system.ruby.network.routers3.throttle1.msg_count.Control::2 78573
|
||||
system.ruby.network.routers3.throttle1.msg_count.Data::2 78015
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Data::4 1075
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Control::2 628584
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Data::2 5617080
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::4 77400
|
||||
system.ruby.network.routers4.throttle0.link_utilization 5.119248
|
||||
system.ruby.network.routers4.throttle0.msg_count.Response_Data::4 78574
|
||||
system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::3 79036
|
||||
system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::4 5657328
|
||||
system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::3 632288
|
||||
system.ruby.network.routers4.throttle1.link_utilization 5.143320
|
||||
system.ruby.network.routers4.throttle1.msg_count.Control::2 78575
|
||||
system.ruby.network.routers4.throttle1.msg_count.Data::2 78023
|
||||
system.ruby.network.routers4.throttle1.msg_count.Response_Data::4 1013
|
||||
system.ruby.network.routers4.throttle1.msg_bytes.Control::2 628600
|
||||
system.ruby.network.routers4.throttle1.msg_bytes.Data::2 5617656
|
||||
system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4 72936
|
||||
system.ruby.network.routers5.throttle0.link_utilization 5.116279
|
||||
system.ruby.network.routers5.throttle0.msg_count.Response_Data::4 78525
|
||||
system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3 79024
|
||||
system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4 5653800
|
||||
system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3 632192
|
||||
system.ruby.network.routers5.throttle1.link_utilization 5.142292
|
||||
system.ruby.network.routers5.throttle1.msg_count.Control::2 78525
|
||||
system.ruby.network.routers5.throttle1.msg_count.Data::2 77953
|
||||
system.ruby.network.routers5.throttle1.msg_count.Response_Data::4 1071
|
||||
system.ruby.network.routers5.throttle1.msg_bytes.Control::2 628200
|
||||
system.ruby.network.routers5.throttle1.msg_bytes.Data::2 5612616
|
||||
system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::4 77112
|
||||
system.ruby.network.routers6.throttle0.link_utilization 5.110633
|
||||
system.ruby.network.routers6.throttle0.msg_count.Response_Data::4 78438
|
||||
system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3 78937
|
||||
system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4 5647536
|
||||
system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3 631496
|
||||
system.ruby.network.routers6.throttle1.link_utilization 5.136640
|
||||
system.ruby.network.routers6.throttle1.msg_count.Control::2 78440
|
||||
system.ruby.network.routers6.throttle1.msg_count.Data::2 77859
|
||||
system.ruby.network.routers6.throttle1.msg_count.Response_Data::4 1078
|
||||
system.ruby.network.routers6.throttle1.msg_bytes.Control::2 627520
|
||||
system.ruby.network.routers6.throttle1.msg_bytes.Data::2 5605848
|
||||
system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::4 77616
|
||||
system.ruby.network.routers7.throttle0.link_utilization 5.115302
|
||||
system.ruby.network.routers7.throttle0.msg_count.Response_Data::4 78512
|
||||
system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3 78988
|
||||
system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4 5652864
|
||||
system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3 631904
|
||||
system.ruby.network.routers7.throttle1.link_utilization 5.140117
|
||||
system.ruby.network.routers7.throttle1.msg_count.Control::2 78515
|
||||
system.ruby.network.routers7.throttle1.msg_count.Data::2 77951
|
||||
system.ruby.network.routers7.throttle1.msg_count.Response_Data::4 1037
|
||||
system.ruby.network.routers7.throttle1.msg_bytes.Control::2 628120
|
||||
system.ruby.network.routers7.throttle1.msg_bytes.Data::2 5612472
|
||||
system.ruby.network.routers7.throttle1.msg_bytes.Response_Data::4 74664
|
||||
system.ruby.network.routers8.throttle0.link_utilization 40.660151
|
||||
system.ruby.network.routers8.throttle0.msg_count.Control::2 628472
|
||||
system.ruby.network.routers8.throttle0.msg_count.Data::2 624002
|
||||
system.ruby.network.routers8.throttle0.msg_bytes.Control::2 5027776
|
||||
system.ruby.network.routers8.throttle0.msg_bytes.Data::2 44928144
|
||||
system.ruby.network.routers8.throttle1.link_utilization 40.457804
|
||||
system.ruby.network.routers8.throttle1.msg_count.Response_Data::4 620120
|
||||
system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3 632339
|
||||
system.ruby.network.routers8.throttle1.msg_bytes.Response_Data::4 44648640
|
||||
system.ruby.network.routers8.throttle1.msg_bytes.Writeback_Control::3 5058712
|
||||
system.ruby.network.routers9.throttle0.link_utilization 5.115953
|
||||
system.ruby.network.routers9.throttle0.msg_count.Response_Data::4 78523
|
||||
system.ruby.network.routers9.throttle0.msg_count.Writeback_Control::3 78989
|
||||
system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4 5653656
|
||||
system.ruby.network.routers9.throttle0.msg_bytes.Writeback_Control::3 631912
|
||||
system.ruby.network.routers9.throttle1.link_utilization 5.112626
|
||||
system.ruby.network.routers9.throttle1.msg_count.Response_Data::4 78471
|
||||
system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3 78946
|
||||
system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4 5649912
|
||||
system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3 631568
|
||||
system.ruby.network.routers9.throttle2.link_utilization 5.136920
|
||||
system.ruby.network.routers9.throttle2.msg_count.Response_Data::4 78843
|
||||
system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3 79329
|
||||
system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4 5676696
|
||||
system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3 634632
|
||||
system.ruby.network.routers9.throttle3.link_utilization 5.119365
|
||||
system.ruby.network.routers9.throttle3.msg_count.Response_Data::4 78570
|
||||
system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3 79090
|
||||
system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4 5657040
|
||||
system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3 632720
|
||||
system.ruby.network.routers9.throttle4.link_utilization 5.119248
|
||||
system.ruby.network.routers9.throttle4.msg_count.Response_Data::4 78574
|
||||
system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3 79036
|
||||
system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4 5657328
|
||||
system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3 632288
|
||||
system.ruby.network.routers9.throttle5.link_utilization 5.116298
|
||||
system.ruby.network.routers9.throttle5.msg_count.Response_Data::4 78525
|
||||
system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3 79024
|
||||
system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4 5653800
|
||||
system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3 632192
|
||||
system.ruby.network.routers9.throttle6.link_utilization 5.110633
|
||||
system.ruby.network.routers9.throttle6.msg_count.Response_Data::4 78438
|
||||
system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3 78937
|
||||
system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4 5647536
|
||||
system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3 631496
|
||||
system.ruby.network.routers9.throttle7.link_utilization 5.115302
|
||||
system.ruby.network.routers9.throttle7.msg_count.Response_Data::4 78512
|
||||
system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3 78988
|
||||
system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4 5652864
|
||||
system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3 631904
|
||||
system.ruby.network.routers9.throttle8.link_utilization 40.660151
|
||||
system.ruby.network.routers9.throttle8.msg_count.Control::2 628472
|
||||
system.ruby.network.routers9.throttle8.msg_count.Data::2 624002
|
||||
system.ruby.network.routers9.throttle8.msg_bytes.Control::2 5027776
|
||||
system.ruby.network.routers9.throttle8.msg_bytes.Data::2 44928144
|
||||
system.ruby.delayVCHist.vnet_1::bucket_size 4 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::max_bucket 39 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::samples 628456 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::mean 0.270507 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::stdev 1.327302 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1 | 602976 95.95% 95.95% | 18460 2.94% 98.88% | 5975 0.95% 99.83% | 853 0.14% 99.97% | 168 0.03% 100.00% | 23 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::total 628456 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_2::bucket_size 32 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::max_bucket 319 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::samples 632339 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::mean 4.240058 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::stdev 10.251834 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2 | 614994 97.26% 97.26% | 11474 1.81% 99.07% | 5225 0.83% 99.90% | 542 0.09% 99.98% | 89 0.01% 100.00% | 15 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::total 632339 # delay histogram for vnet_2
|
||||
system.ruby.LD.latency_hist_seqr::bucket_size 512
|
||||
system.ruby.LD.latency_hist_seqr::max_bucket 5119
|
||||
system.ruby.LD.latency_hist_seqr::samples 404420
|
||||
system.ruby.LD.latency_hist_seqr::mean 1563.542728
|
||||
system.ruby.LD.latency_hist_seqr::gmean 1541.515221
|
||||
system.ruby.LD.latency_hist_seqr::stdev 262.248075
|
||||
system.ruby.LD.latency_hist_seqr | 49 0.01% 0.01% | 3881 0.96% 0.97% | 192068 47.49% 48.46% | 191307 47.30% 95.77% | 16988 4.20% 99.97% | 127 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist_seqr::total 404420
|
||||
system.ruby.LD.miss_latency_hist_seqr::bucket_size 512
|
||||
system.ruby.LD.miss_latency_hist_seqr::max_bucket 5119
|
||||
system.ruby.LD.miss_latency_hist_seqr::samples 404420
|
||||
system.ruby.LD.miss_latency_hist_seqr::mean 1563.542728
|
||||
system.ruby.LD.miss_latency_hist_seqr::gmean 1541.515221
|
||||
system.ruby.LD.miss_latency_hist_seqr::stdev 262.248075
|
||||
system.ruby.LD.miss_latency_hist_seqr | 49 0.01% 0.01% | 3881 0.96% 0.97% | 192068 47.49% 48.46% | 191307 47.30% 95.77% | 16988 4.20% 99.97% | 127 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist_seqr::total 404420
|
||||
system.ruby.ST.latency_hist_seqr::bucket_size 512
|
||||
system.ruby.ST.latency_hist_seqr::max_bucket 5119
|
||||
system.ruby.ST.latency_hist_seqr::samples 224036
|
||||
system.ruby.ST.latency_hist_seqr::mean 1564.295926
|
||||
system.ruby.ST.latency_hist_seqr::gmean 1542.292779
|
||||
system.ruby.ST.latency_hist_seqr::stdev 262.297007
|
||||
system.ruby.ST.latency_hist_seqr | 28 0.01% 0.01% | 2223 0.99% 1.00% | 105994 47.31% 48.32% | 106129 47.37% 95.69% | 9598 4.28% 99.97% | 64 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist_seqr::total 224036
|
||||
system.ruby.ST.miss_latency_hist_seqr::bucket_size 512
|
||||
system.ruby.ST.miss_latency_hist_seqr::max_bucket 5119
|
||||
system.ruby.ST.miss_latency_hist_seqr::samples 224036
|
||||
system.ruby.ST.miss_latency_hist_seqr::mean 1564.295926
|
||||
system.ruby.ST.miss_latency_hist_seqr::gmean 1542.292779
|
||||
system.ruby.ST.miss_latency_hist_seqr::stdev 262.297007
|
||||
system.ruby.ST.miss_latency_hist_seqr | 28 0.01% 0.01% | 2223 0.99% 1.00% | 105994 47.31% 48.32% | 106129 47.37% 95.69% | 9598 4.28% 99.97% | 64 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist_seqr::total 224036
|
||||
system.ruby.L1Cache.miss_mach_latency_hist_seqr::bucket_size 512
|
||||
system.ruby.L1Cache.miss_mach_latency_hist_seqr::max_bucket 5119
|
||||
system.ruby.L1Cache.miss_mach_latency_hist_seqr::samples 8337
|
||||
system.ruby.L1Cache.miss_mach_latency_hist_seqr::mean 1457.519731
|
||||
system.ruby.L1Cache.miss_mach_latency_hist_seqr::gmean 1434.160972
|
||||
system.ruby.L1Cache.miss_mach_latency_hist_seqr::stdev 261.316891
|
||||
system.ruby.L1Cache.miss_mach_latency_hist_seqr | 1 0.01% 0.01% | 260 3.12% 3.13% | 5041 60.47% 63.60% | 2865 34.36% 97.96% | 168 2.02% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.L1Cache.miss_mach_latency_hist_seqr::total 8337
|
||||
system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 512
|
||||
system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 5119
|
||||
system.ruby.Directory.miss_mach_latency_hist_seqr::samples 620119
|
||||
system.ruby.Directory.miss_mach_latency_hist_seqr::mean 1565.240236
|
||||
system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 1543.293101
|
||||
system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 261.984881
|
||||
system.ruby.Directory.miss_mach_latency_hist_seqr | 76 0.01% 0.01% | 5844 0.94% 0.95% | 293021 47.25% 48.21% | 294571 47.50% 95.71% | 26418 4.26% 99.97% | 189 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist_seqr::total 620119
|
||||
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
|
||||
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
|
||||
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 3
|
||||
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 3
|
||||
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1
|
||||
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9
|
||||
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 3
|
||||
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 3
|
||||
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1
|
||||
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9
|
||||
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 3
|
||||
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 3
|
||||
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 16
|
||||
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 159
|
||||
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 3
|
||||
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 80
|
||||
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 79.895697
|
||||
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev 5
|
||||
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 3
|
||||
system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 256
|
||||
system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 2559
|
||||
system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::samples 5455
|
||||
system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::mean 1456.778185
|
||||
system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::gmean 1433.055554
|
||||
system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::stdev 263.122030
|
||||
system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 1 0.02% 0.02% | 6 0.11% 0.13% | 171 3.13% 3.26% | 1270 23.28% 26.54% | 2035 37.31% 63.85% | 1383 25.35% 89.20% | 473 8.67% 97.87% | 103 1.89% 99.76% | 13 0.24% 100.00%
|
||||
system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::total 5455
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 512
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 5119
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 398965
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 1565.002506
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 1543.053698
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 261.935038
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 48 0.01% 0.01% | 3704 0.93% 0.94% | 188763 47.31% 48.25% | 189451 47.49% 95.74% | 16872 4.23% 99.97% | 127 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 398965
|
||||
system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 512
|
||||
system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 5119
|
||||
system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::samples 2882
|
||||
system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::mean 1458.923317
|
||||
system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::gmean 1436.255624
|
||||
system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::stdev 257.905109
|
||||
system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 83 2.88% 2.88% | 1736 60.24% 63.12% | 1009 35.01% 98.13% | 52 1.80% 99.93% | 2 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::total 2882
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 512
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 5119
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 221154
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 1565.669104
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 1543.725080
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 262.074821
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 28 0.01% 0.01% | 2140 0.97% 0.98% | 104258 47.14% 48.12% | 105120 47.53% 95.66% | 9546 4.32% 99.97% | 62 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 221154
|
||||
system.ruby.Directory_Controller.GETX 695129 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUTX 620103 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUTX_NotOwner 3899 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Data 620120 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Ack 620103 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.GETX 620135 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.GETX 8337 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.PUTX 620103 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.PUTX_NotOwner 3899 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IM.GETX 66370 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IM.Memory_Data 620120 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MI.GETX 287 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MI.Memory_Ack 620103 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Load | 50377 12.46% 12.46% | 50576 12.51% 24.96% | 50610 12.51% 37.48% | 50632 12.52% 49.99% | 50644 12.52% 62.52% | 50559 12.50% 75.02% | 50404 12.46% 87.48% | 50629 12.52% 100.00%
|
||||
system.ruby.L1Cache_Controller.Load::total 404431
|
||||
system.ruby.L1Cache_Controller.Store | 28149 12.56% 12.56% | 27898 12.45% 25.02% | 28234 12.60% 37.62% | 27941 12.47% 50.09% | 27931 12.47% 62.56% | 27970 12.48% 75.04% | 28036 12.51% 87.55% | 27886 12.45% 100.00%
|
||||
system.ruby.L1Cache_Controller.Store::total 224045
|
||||
system.ruby.L1Cache_Controller.Data | 78523 12.49% 12.49% | 78471 12.49% 24.98% | 78843 12.55% 37.53% | 78570 12.50% 50.03% | 78574 12.50% 62.53% | 78525 12.49% 75.03% | 78438 12.48% 87.51% | 78512 12.49% 100.00%
|
||||
system.ruby.L1Cache_Controller.Data::total 628456
|
||||
system.ruby.L1Cache_Controller.Fwd_GETX | 1008 12.09% 12.09% | 1013 12.15% 24.24% | 1042 12.50% 36.74% | 1075 12.89% 49.63% | 1013 12.15% 61.78% | 1071 12.85% 74.63% | 1078 12.93% 87.56% | 1037 12.44% 100.00%
|
||||
system.ruby.L1Cache_Controller.Fwd_GETX::total 8337
|
||||
system.ruby.L1Cache_Controller.Replacement | 78522 12.49% 12.49% | 78470 12.49% 24.98% | 78840 12.55% 37.53% | 78569 12.50% 50.03% | 78571 12.50% 62.53% | 78525 12.50% 75.03% | 78436 12.48% 87.51% | 78511 12.49% 100.00%
|
||||
system.ruby.L1Cache_Controller.Replacement::total 628444
|
||||
system.ruby.L1Cache_Controller.Writeback_Ack | 77514 12.50% 12.50% | 77457 12.49% 24.99% | 77798 12.55% 37.54% | 77494 12.50% 50.03% | 77558 12.51% 62.54% | 77450 12.49% 75.03% | 77358 12.48% 87.51% | 77474 12.49% 100.00%
|
||||
system.ruby.L1Cache_Controller.Writeback_Ack::total 620103
|
||||
system.ruby.L1Cache_Controller.Writeback_Nack | 467 11.98% 11.98% | 476 12.21% 24.19% | 489 12.54% 36.73% | 521 13.36% 50.09% | 465 11.93% 62.02% | 503 12.90% 74.92% | 501 12.85% 87.77% | 477 12.23% 100.00%
|
||||
system.ruby.L1Cache_Controller.Writeback_Nack::total 3899
|
||||
system.ruby.L1Cache_Controller.I.Load | 50377 12.46% 12.46% | 50576 12.51% 24.96% | 50610 12.51% 37.48% | 50632 12.52% 49.99% | 50644 12.52% 62.52% | 50559 12.50% 75.02% | 50404 12.46% 87.48% | 50629 12.52% 100.00%
|
||||
system.ruby.L1Cache_Controller.I.Load::total 404431
|
||||
system.ruby.L1Cache_Controller.I.Store | 28149 12.56% 12.56% | 27898 12.45% 25.02% | 28234 12.60% 37.62% | 27941 12.47% 50.09% | 27931 12.47% 62.56% | 27970 12.48% 75.04% | 28036 12.51% 87.55% | 27886 12.45% 100.00%
|
||||
system.ruby.L1Cache_Controller.I.Store::total 224045
|
||||
system.ruby.L1Cache_Controller.I.Replacement | 541 12.19% 12.19% | 537 12.10% 24.29% | 553 12.46% 36.75% | 554 12.48% 49.23% | 548 12.35% 61.58% | 568 12.80% 74.38% | 577 13.00% 87.38% | 560 12.62% 100.00%
|
||||
system.ruby.L1Cache_Controller.I.Replacement::total 4438
|
||||
system.ruby.L1Cache_Controller.II.Writeback_Nack | 467 11.98% 11.98% | 476 12.21% 24.19% | 489 12.54% 36.73% | 521 13.36% 50.09% | 465 11.93% 62.02% | 503 12.90% 74.92% | 501 12.85% 87.77% | 477 12.23% 100.00%
|
||||
system.ruby.L1Cache_Controller.II.Writeback_Nack::total 3899
|
||||
system.ruby.L1Cache_Controller.M.Fwd_GETX | 541 12.19% 12.19% | 537 12.10% 24.29% | 553 12.46% 36.75% | 554 12.48% 49.23% | 548 12.35% 61.58% | 568 12.80% 74.38% | 577 13.00% 87.38% | 560 12.62% 100.00%
|
||||
system.ruby.L1Cache_Controller.M.Fwd_GETX::total 4438
|
||||
system.ruby.L1Cache_Controller.M.Replacement | 77981 12.50% 12.50% | 77933 12.49% 24.99% | 78287 12.55% 37.53% | 78015 12.50% 50.03% | 78023 12.50% 62.54% | 77957 12.49% 75.03% | 77859 12.48% 87.51% | 77951 12.49% 100.00%
|
||||
system.ruby.L1Cache_Controller.M.Replacement::total 624006
|
||||
system.ruby.L1Cache_Controller.MI.Fwd_GETX | 467 11.98% 11.98% | 476 12.21% 24.19% | 489 12.54% 36.73% | 521 13.36% 50.09% | 465 11.93% 62.02% | 503 12.90% 74.92% | 501 12.85% 87.77% | 477 12.23% 100.00%
|
||||
system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 3899
|
||||
system.ruby.L1Cache_Controller.MI.Writeback_Ack | 77514 12.50% 12.50% | 77457 12.49% 24.99% | 77798 12.55% 37.54% | 77494 12.50% 50.03% | 77558 12.51% 62.54% | 77450 12.49% 75.03% | 77358 12.48% 87.51% | 77474 12.49% 100.00%
|
||||
system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 620103
|
||||
system.ruby.L1Cache_Controller.IS.Data | 50375 12.46% 12.46% | 50575 12.51% 24.96% | 50609 12.51% 37.48% | 50632 12.52% 50.00% | 50643 12.52% 62.52% | 50556 12.50% 75.02% | 50402 12.46% 87.48% | 50628 12.52% 100.00%
|
||||
system.ruby.L1Cache_Controller.IS.Data::total 404420
|
||||
system.ruby.L1Cache_Controller.IM.Data | 28148 12.56% 12.56% | 27896 12.45% 25.02% | 28234 12.60% 37.62% | 27938 12.47% 50.09% | 27931 12.47% 62.56% | 27969 12.48% 75.04% | 28036 12.51% 87.55% | 27884 12.45% 100.00%
|
||||
system.ruby.L1Cache_Controller.IM.Data::total 224036
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -1,742 +0,0 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[1]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu0]
|
||||
type=MemTest
|
||||
children=l1c
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
interval=1
|
||||
max_loads=100000
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_uncacheable=10
|
||||
power_model=Null
|
||||
progress_check=5000000
|
||||
progress_interval=10000
|
||||
size=65536
|
||||
suppress_func_warnings=false
|
||||
system=system
|
||||
port=system.cpu0.l1c.cpu_side
|
||||
|
||||
[system.cpu0.l1c]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.l1c.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu0.port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu0.l1c.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu1]
|
||||
type=MemTest
|
||||
children=l1c
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
interval=1
|
||||
max_loads=100000
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_uncacheable=10
|
||||
power_model=Null
|
||||
progress_check=5000000
|
||||
progress_interval=10000
|
||||
size=65536
|
||||
suppress_func_warnings=false
|
||||
system=system
|
||||
port=system.cpu1.l1c.cpu_side
|
||||
|
||||
[system.cpu1.l1c]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu1.l1c.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu1.port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu1.l1c.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu2]
|
||||
type=MemTest
|
||||
children=l1c
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
interval=1
|
||||
max_loads=100000
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_uncacheable=10
|
||||
power_model=Null
|
||||
progress_check=5000000
|
||||
progress_interval=10000
|
||||
size=65536
|
||||
suppress_func_warnings=false
|
||||
system=system
|
||||
port=system.cpu2.l1c.cpu_side
|
||||
|
||||
[system.cpu2.l1c]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu2.l1c.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu2.port
|
||||
mem_side=system.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu2.l1c.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu3]
|
||||
type=MemTest
|
||||
children=l1c
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
interval=1
|
||||
max_loads=100000
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_uncacheable=10
|
||||
power_model=Null
|
||||
progress_check=5000000
|
||||
progress_interval=10000
|
||||
size=65536
|
||||
suppress_func_warnings=false
|
||||
system=system
|
||||
port=system.cpu3.l1c.cpu_side
|
||||
|
||||
[system.cpu3.l1c]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu3.l1c.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu3.port
|
||||
mem_side=system.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu3.l1c.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu4]
|
||||
type=MemTest
|
||||
children=l1c
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
interval=1
|
||||
max_loads=100000
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_uncacheable=10
|
||||
power_model=Null
|
||||
progress_check=5000000
|
||||
progress_interval=10000
|
||||
size=65536
|
||||
suppress_func_warnings=false
|
||||
system=system
|
||||
port=system.cpu4.l1c.cpu_side
|
||||
|
||||
[system.cpu4.l1c]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu4.l1c.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu4.port
|
||||
mem_side=system.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu4.l1c.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu5]
|
||||
type=MemTest
|
||||
children=l1c
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
interval=1
|
||||
max_loads=100000
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_uncacheable=10
|
||||
power_model=Null
|
||||
progress_check=5000000
|
||||
progress_interval=10000
|
||||
size=65536
|
||||
suppress_func_warnings=false
|
||||
system=system
|
||||
port=system.cpu5.l1c.cpu_side
|
||||
|
||||
[system.cpu5.l1c]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu5.l1c.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu5.port
|
||||
mem_side=system.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu5.l1c.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu6]
|
||||
type=MemTest
|
||||
children=l1c
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
interval=1
|
||||
max_loads=100000
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_uncacheable=10
|
||||
power_model=Null
|
||||
progress_check=5000000
|
||||
progress_interval=10000
|
||||
size=65536
|
||||
suppress_func_warnings=false
|
||||
system=system
|
||||
port=system.cpu6.l1c.cpu_side
|
||||
|
||||
[system.cpu6.l1c]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu6.l1c.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu6.port
|
||||
mem_side=system.toL2Bus.slave[6]
|
||||
|
||||
[system.cpu6.l1c.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu7]
|
||||
type=MemTest
|
||||
children=l1c
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
interval=1
|
||||
max_loads=100000
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_uncacheable=10
|
||||
power_model=Null
|
||||
progress_check=5000000
|
||||
progress_interval=10000
|
||||
size=65536
|
||||
suppress_func_warnings=false
|
||||
system=system
|
||||
port=system.cpu7.l1c.cpu_side
|
||||
|
||||
[system.cpu7.l1c]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu7.l1c.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu7.port
|
||||
mem_side=system.toL2Bus.slave[7]
|
||||
|
||||
[system.cpu7.l1c.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.l2c]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=65536
|
||||
system=system
|
||||
tags=system.l2c.tags
|
||||
tgts_per_mshr=12
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[0]
|
||||
|
||||
[system.l2c.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=65536
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.l2c.mem_side system.system_port
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=0:134217727
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.toL2Bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
|
||||
|
||||
[system.toL2Bus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
@ -1,73 +0,0 @@
|
|||
system.cpu3: completed 10000 read, 5503 write accesses @55915500
|
||||
system.cpu4: completed 10000 read, 5302 write accesses @55980000
|
||||
system.cpu7: completed 10000 read, 5500 write accesses @56129000
|
||||
system.cpu2: completed 10000 read, 5342 write accesses @56146500
|
||||
system.cpu6: completed 10000 read, 5358 write accesses @56494500
|
||||
system.cpu0: completed 10000 read, 5493 write accesses @56861500
|
||||
system.cpu1: completed 10000 read, 5676 write accesses @57033500
|
||||
system.cpu5: completed 10000 read, 5528 write accesses @57497500
|
||||
system.cpu4: completed 20000 read, 10871 write accesses @105086000
|
||||
system.cpu7: completed 20000 read, 11018 write accesses @105227000
|
||||
system.cpu6: completed 20000 read, 10904 write accesses @105245500
|
||||
system.cpu0: completed 20000 read, 10841 write accesses @105416500
|
||||
system.cpu3: completed 20000 read, 11147 write accesses @105878500
|
||||
system.cpu2: completed 20000 read, 10930 write accesses @106485500
|
||||
system.cpu5: completed 20000 read, 10954 write accesses @106687000
|
||||
system.cpu1: completed 20000 read, 11324 write accesses @107095000
|
||||
system.cpu4: completed 30000 read, 16387 write accesses @154433500
|
||||
system.cpu6: completed 30000 read, 16529 write accesses @154891500
|
||||
system.cpu2: completed 30000 read, 16387 write accesses @154906000
|
||||
system.cpu3: completed 30000 read, 16756 write accesses @155604500
|
||||
system.cpu7: completed 30000 read, 16642 write accesses @155734000
|
||||
system.cpu5: completed 30000 read, 16445 write accesses @156039500
|
||||
system.cpu0: completed 30000 read, 16469 write accesses @156104500
|
||||
system.cpu1: completed 30000 read, 16825 write accesses @156708500
|
||||
system.cpu6: completed 40000 read, 21980 write accesses @203895500
|
||||
system.cpu4: completed 40000 read, 22029 write accesses @204285000
|
||||
system.cpu3: completed 40000 read, 22257 write accesses @204704000
|
||||
system.cpu7: completed 40000 read, 22193 write accesses @205001500
|
||||
system.cpu2: completed 40000 read, 22047 write accesses @205470000
|
||||
system.cpu5: completed 40000 read, 22004 write accesses @206055000
|
||||
system.cpu0: completed 40000 read, 21987 write accesses @206174000
|
||||
system.cpu1: completed 40000 read, 22532 write accesses @206732500
|
||||
system.cpu4: completed 50000 read, 27591 write accesses @253615500
|
||||
system.cpu6: completed 50000 read, 27369 write accesses @253616500
|
||||
system.cpu2: completed 50000 read, 27561 write accesses @254261500
|
||||
system.cpu7: completed 50000 read, 27945 write accesses @254398000
|
||||
system.cpu5: completed 50000 read, 27346 write accesses @254644500
|
||||
system.cpu3: completed 50000 read, 27794 write accesses @254687000
|
||||
system.cpu0: completed 50000 read, 27491 write accesses @255540000
|
||||
system.cpu1: completed 50000 read, 28147 write accesses @256393500
|
||||
system.cpu4: completed 60000 read, 33155 write accesses @302912000
|
||||
system.cpu6: completed 60000 read, 33024 write accesses @303044500
|
||||
system.cpu5: completed 60000 read, 32819 write accesses @303948500
|
||||
system.cpu7: completed 60000 read, 33412 write accesses @304003500
|
||||
system.cpu2: completed 60000 read, 33183 write accesses @305097000
|
||||
system.cpu3: completed 60000 read, 33603 write accesses @305311500
|
||||
system.cpu1: completed 60000 read, 33393 write accesses @305569000
|
||||
system.cpu0: completed 60000 read, 33038 write accesses @305621500
|
||||
system.cpu4: completed 70000 read, 38636 write accesses @352443000
|
||||
system.cpu5: completed 70000 read, 38516 write accesses @353701000
|
||||
system.cpu6: completed 70000 read, 38725 write accesses @353942000
|
||||
system.cpu7: completed 70000 read, 39072 write accesses @354424000
|
||||
system.cpu2: completed 70000 read, 38818 write accesses @354701000
|
||||
system.cpu1: completed 70000 read, 38717 write accesses @354858500
|
||||
system.cpu3: completed 70000 read, 39274 write accesses @355379500
|
||||
system.cpu0: completed 70000 read, 38744 write accesses @355617500
|
||||
system.cpu4: completed 80000 read, 44404 write accesses @402767500
|
||||
system.cpu2: completed 80000 read, 44188 write accesses @403291500
|
||||
system.cpu5: completed 80000 read, 44099 write accesses @403371500
|
||||
system.cpu7: completed 80000 read, 44629 write accesses @403854500
|
||||
system.cpu6: completed 80000 read, 44307 write accesses @404062000
|
||||
system.cpu0: completed 80000 read, 44206 write accesses @404147000
|
||||
system.cpu1: completed 80000 read, 44256 write accesses @404649000
|
||||
system.cpu3: completed 80000 read, 44966 write accesses @406154000
|
||||
system.cpu4: completed 90000 read, 49951 write accesses @452283500
|
||||
system.cpu5: completed 90000 read, 49582 write accesses @452363500
|
||||
system.cpu2: completed 90000 read, 49727 write accesses @452365500
|
||||
system.cpu6: completed 90000 read, 49789 write accesses @453642000
|
||||
system.cpu0: completed 90000 read, 49883 write accesses @453665500
|
||||
system.cpu7: completed 90000 read, 50370 write accesses @454276500
|
||||
system.cpu1: completed 90000 read, 49817 write accesses @454621500
|
||||
system.cpu3: completed 90000 read, 50461 write accesses @455559000
|
||||
system.cpu5: completed 100000 read, 55110 write accesses @501584000
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
Redirecting stdout to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter/simout
|
||||
Redirecting stderr to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 21 2016 14:24:31
|
||||
gem5 started Jul 21 2016 14:24:50
|
||||
gem5 executing on e108600-lin, pid 18184
|
||||
command line: /work/curdun01/gem5-external.hg/build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.memtest/null/none/memtest-filter
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 501584000 because maximum number of loads reached
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,734 +0,0 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[1]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu0]
|
||||
type=MemTest
|
||||
children=l1c
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
interval=1
|
||||
max_loads=100000
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_uncacheable=10
|
||||
power_model=Null
|
||||
progress_check=5000000
|
||||
progress_interval=10000
|
||||
size=65536
|
||||
suppress_func_warnings=false
|
||||
system=system
|
||||
port=system.cpu0.l1c.cpu_side
|
||||
|
||||
[system.cpu0.l1c]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu0.l1c.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu0.port
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu0.l1c.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu1]
|
||||
type=MemTest
|
||||
children=l1c
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
interval=1
|
||||
max_loads=100000
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_uncacheable=10
|
||||
power_model=Null
|
||||
progress_check=5000000
|
||||
progress_interval=10000
|
||||
size=65536
|
||||
suppress_func_warnings=false
|
||||
system=system
|
||||
port=system.cpu1.l1c.cpu_side
|
||||
|
||||
[system.cpu1.l1c]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu1.l1c.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu1.port
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu1.l1c.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu2]
|
||||
type=MemTest
|
||||
children=l1c
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
interval=1
|
||||
max_loads=100000
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_uncacheable=10
|
||||
power_model=Null
|
||||
progress_check=5000000
|
||||
progress_interval=10000
|
||||
size=65536
|
||||
suppress_func_warnings=false
|
||||
system=system
|
||||
port=system.cpu2.l1c.cpu_side
|
||||
|
||||
[system.cpu2.l1c]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu2.l1c.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu2.port
|
||||
mem_side=system.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu2.l1c.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu3]
|
||||
type=MemTest
|
||||
children=l1c
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
interval=1
|
||||
max_loads=100000
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_uncacheable=10
|
||||
power_model=Null
|
||||
progress_check=5000000
|
||||
progress_interval=10000
|
||||
size=65536
|
||||
suppress_func_warnings=false
|
||||
system=system
|
||||
port=system.cpu3.l1c.cpu_side
|
||||
|
||||
[system.cpu3.l1c]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu3.l1c.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu3.port
|
||||
mem_side=system.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu3.l1c.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu4]
|
||||
type=MemTest
|
||||
children=l1c
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
interval=1
|
||||
max_loads=100000
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_uncacheable=10
|
||||
power_model=Null
|
||||
progress_check=5000000
|
||||
progress_interval=10000
|
||||
size=65536
|
||||
suppress_func_warnings=false
|
||||
system=system
|
||||
port=system.cpu4.l1c.cpu_side
|
||||
|
||||
[system.cpu4.l1c]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu4.l1c.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu4.port
|
||||
mem_side=system.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu4.l1c.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu5]
|
||||
type=MemTest
|
||||
children=l1c
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
interval=1
|
||||
max_loads=100000
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_uncacheable=10
|
||||
power_model=Null
|
||||
progress_check=5000000
|
||||
progress_interval=10000
|
||||
size=65536
|
||||
suppress_func_warnings=false
|
||||
system=system
|
||||
port=system.cpu5.l1c.cpu_side
|
||||
|
||||
[system.cpu5.l1c]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu5.l1c.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu5.port
|
||||
mem_side=system.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu5.l1c.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu6]
|
||||
type=MemTest
|
||||
children=l1c
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
interval=1
|
||||
max_loads=100000
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_uncacheable=10
|
||||
power_model=Null
|
||||
progress_check=5000000
|
||||
progress_interval=10000
|
||||
size=65536
|
||||
suppress_func_warnings=false
|
||||
system=system
|
||||
port=system.cpu6.l1c.cpu_side
|
||||
|
||||
[system.cpu6.l1c]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu6.l1c.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu6.port
|
||||
mem_side=system.toL2Bus.slave[6]
|
||||
|
||||
[system.cpu6.l1c.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu7]
|
||||
type=MemTest
|
||||
children=l1c
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
interval=1
|
||||
max_loads=100000
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
percent_functional=50
|
||||
percent_reads=65
|
||||
percent_uncacheable=10
|
||||
power_model=Null
|
||||
progress_check=5000000
|
||||
progress_interval=10000
|
||||
size=65536
|
||||
suppress_func_warnings=false
|
||||
system=system
|
||||
port=system.cpu7.l1c.cpu_side
|
||||
|
||||
[system.cpu7.l1c]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tags=system.cpu7.l1c.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu7.port
|
||||
mem_side=system.toL2Bus.slave[7]
|
||||
|
||||
[system.cpu7.l1c.tags]
|
||||
type=LRU
|
||||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.l2c]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=65536
|
||||
system=system
|
||||
tags=system.l2c.tags
|
||||
tgts_per_mshr=12
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[0]
|
||||
|
||||
[system.l2c.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=65536
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.l2c.mem_side system.system_port
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=0:134217727
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.toL2Bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
|
||||
|
||||
[system.toL2Bus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=0
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
|
|
@ -1,73 +0,0 @@
|
|||
system.cpu2: completed 10000 read, 5501 write accesses @55798000
|
||||
system.cpu1: completed 10000 read, 5520 write accesses @55942500
|
||||
system.cpu4: completed 10000 read, 5672 write accesses @55948000
|
||||
system.cpu0: completed 10000 read, 5544 write accesses @56022500
|
||||
system.cpu6: completed 10000 read, 5523 write accesses @56194500
|
||||
system.cpu5: completed 10000 read, 5576 write accesses @56196500
|
||||
system.cpu3: completed 10000 read, 5638 write accesses @56648500
|
||||
system.cpu7: completed 10000 read, 5609 write accesses @56820000
|
||||
system.cpu6: completed 20000 read, 11092 write accesses @104740000
|
||||
system.cpu4: completed 20000 read, 11217 write accesses @105227500
|
||||
system.cpu0: completed 20000 read, 11130 write accesses @105598500
|
||||
system.cpu5: completed 20000 read, 11119 write accesses @105604000
|
||||
system.cpu2: completed 20000 read, 11021 write accesses @105822000
|
||||
system.cpu7: completed 20000 read, 11085 write accesses @105988500
|
||||
system.cpu3: completed 20000 read, 11232 write accesses @106234000
|
||||
system.cpu1: completed 20000 read, 11093 write accesses @106248000
|
||||
system.cpu6: completed 30000 read, 16618 write accesses @154364000
|
||||
system.cpu4: completed 30000 read, 16727 write accesses @154528000
|
||||
system.cpu5: completed 30000 read, 16661 write accesses @154991500
|
||||
system.cpu0: completed 30000 read, 16578 write accesses @155150000
|
||||
system.cpu7: completed 30000 read, 16597 write accesses @155572000
|
||||
system.cpu3: completed 30000 read, 16777 write accesses @155692000
|
||||
system.cpu2: completed 30000 read, 16783 write accesses @155741500
|
||||
system.cpu1: completed 30000 read, 16605 write accesses @155757500
|
||||
system.cpu4: completed 40000 read, 22227 write accesses @203532500
|
||||
system.cpu0: completed 40000 read, 22094 write accesses @203735500
|
||||
system.cpu2: completed 40000 read, 22329 write accesses @204034500
|
||||
system.cpu6: completed 40000 read, 22323 write accesses @204341500
|
||||
system.cpu5: completed 40000 read, 22093 write accesses @204530500
|
||||
system.cpu3: completed 40000 read, 22449 write accesses @204979500
|
||||
system.cpu7: completed 40000 read, 22085 write accesses @205200000
|
||||
system.cpu1: completed 40000 read, 22157 write accesses @205324500
|
||||
system.cpu2: completed 50000 read, 27810 write accesses @252814500
|
||||
system.cpu0: completed 50000 read, 27524 write accesses @252975000
|
||||
system.cpu4: completed 50000 read, 27619 write accesses @253195000
|
||||
system.cpu6: completed 50000 read, 27815 write accesses @253668000
|
||||
system.cpu5: completed 50000 read, 27749 write accesses @254286500
|
||||
system.cpu3: completed 50000 read, 28015 write accesses @254662000
|
||||
system.cpu1: completed 50000 read, 27700 write accesses @255277000
|
||||
system.cpu7: completed 50000 read, 27537 write accesses @255788500
|
||||
system.cpu2: completed 60000 read, 33479 write accesses @302616500
|
||||
system.cpu4: completed 60000 read, 33151 write accesses @302639500
|
||||
system.cpu0: completed 60000 read, 33158 write accesses @302949000
|
||||
system.cpu5: completed 60000 read, 33293 write accesses @303327000
|
||||
system.cpu6: completed 60000 read, 33367 write accesses @303498500
|
||||
system.cpu3: completed 60000 read, 33551 write accesses @304167000
|
||||
system.cpu1: completed 60000 read, 33190 write accesses @304842500
|
||||
system.cpu7: completed 60000 read, 33105 write accesses @305455501
|
||||
system.cpu4: completed 70000 read, 38677 write accesses @351659000
|
||||
system.cpu0: completed 70000 read, 38797 write accesses @352214500
|
||||
system.cpu2: completed 70000 read, 39135 write accesses @352355500
|
||||
system.cpu6: completed 70000 read, 38839 write accesses @353200500
|
||||
system.cpu5: completed 70000 read, 38774 write accesses @353284000
|
||||
system.cpu3: completed 70000 read, 38980 write accesses @353497000
|
||||
system.cpu1: completed 70000 read, 38895 write accesses @355264000
|
||||
system.cpu7: completed 70000 read, 38703 write accesses @355598500
|
||||
system.cpu2: completed 80000 read, 44512 write accesses @400360000
|
||||
system.cpu4: completed 80000 read, 44241 write accesses @401405500
|
||||
system.cpu0: completed 80000 read, 44424 write accesses @401492500
|
||||
system.cpu6: completed 80000 read, 44426 write accesses @402695000
|
||||
system.cpu5: completed 80000 read, 44250 write accesses @402938000
|
||||
system.cpu3: completed 80000 read, 44495 write accesses @403103500
|
||||
system.cpu1: completed 80000 read, 44343 write accesses @403920500
|
||||
system.cpu7: completed 80000 read, 44194 write accesses @404626000
|
||||
system.cpu0: completed 90000 read, 49874 write accesses @450153000
|
||||
system.cpu2: completed 90000 read, 50018 write accesses @450453000
|
||||
system.cpu4: completed 90000 read, 49959 write accesses @452038500
|
||||
system.cpu3: completed 90000 read, 50050 write accesses @452249000
|
||||
system.cpu5: completed 90000 read, 49902 write accesses @452294500
|
||||
system.cpu6: completed 90000 read, 50125 write accesses @453074500
|
||||
system.cpu1: completed 90000 read, 49995 write accesses @453105500
|
||||
system.cpu7: completed 90000 read, 49805 write accesses @454516500
|
||||
system.cpu2: completed 100000 read, 55556 write accesses @500337000
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
Redirecting stdout to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest/simout
|
||||
Redirecting stderr to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 21 2016 14:24:31
|
||||
gem5 started Jul 21 2016 14:24:50
|
||||
gem5 executing on e108600-lin, pid 18186
|
||||
command line: /work/curdun01/gem5-external.hg/build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.memtest/null/none/memtest
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 500337000 because maximum number of loads reached
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
Loading…
Reference in a new issue