Commit graph

87 commits

Author SHA1 Message Date
Ali Saidi 28a2236ec1 O3: Update stats for new ordering fix. 2011-09-13 12:58:09 -04:00
Ali Saidi 999cd8aef5 StoreSet: Update stats for store-set clearing 2011-08-19 15:08:08 -05:00
Ali Saidi f125ef22b9 O3: Update stats for LSQ changes. 2011-08-19 15:08:06 -05:00
Gabe Black a1aaeac2f9 Stats: Update the stats after the uninitialized branch predictor variable fix. 2011-08-07 09:22:18 -07:00
Ali Saidi 3ebfe2eb01 O3: Update stats for fetch and bp changes. 2011-07-10 12:56:09 -05:00
Korey Sewell b5736ba4ef alpha:o3:simple: update simout/err files
A few prior changesets have changed the gem5 output in a way that wont cause
errors but may be confusing for someone trying to debug the regressions. Ones that I caught
were:
- no more "warn: <hash address"
- typo in the ALPHA Prefetch unimplemented warning

Additionaly, the last updated stats changes rearrange the ordering of the stats output even though
they are still correct stats (gem5 is smart enough to detect this). All the regressions pass
w/the same stats even though it looks like they are being changed.
2011-06-20 18:57:14 -04:00
Korey Sewell 55dce6419d inorder: update SE regressions 2011-06-19 21:43:42 -04:00
Korey Sewell 1aa4869ff0 sparc: update long regressions 2011-06-12 21:35:03 -04:00
Ali Saidi 5d5b0f49cc Stats: Update stats for minor O3 changes below. 2011-05-23 10:59:13 -05:00
Ali Saidi 44e599a1a4 ARM: Fix up stats for previous changes to condition codes 2011-05-13 17:29:27 -05:00
Ali Saidi fea2c26402 ARM: Update ARM_FS stats for mp changes 2011-05-04 20:38:28 -05:00
Ali Saidi 307f089e7f O3/ARM: Update stats for recent changes. 2011-05-04 20:38:27 -05:00
Nathan Binkert a7e27f9a82 tests: updates for stat name change 2011-04-22 10:18:51 -07:00
Nathan Binkert 8c1563096c tests: update stats for name changes 2011-04-19 18:45:23 -07:00
Ali Saidi d50d0152d0 ARM: Fix stats for ARM_SE checkpoint restore fix.
Register reads/writes done in startup() count against the stats while they
don't count if done in initState().
2011-04-12 16:09:20 -04:00
Ali Saidi b20e92e1ca ARM: Update stats for previous changes. 2011-04-04 11:42:31 -05:00
Ali Saidi 1114be4b78 O3: Update stats for memory order violation checking patch. 2011-04-04 11:42:25 -05:00
Ali Saidi 63eb337b3b ARM: Update stats for the previous changes and add ARM_FS/O3 regression. 2011-03-17 19:20:22 -05:00
Ali Saidi 73603c2b17 ARM: Update regression tests for preceeding changes. 2011-02-23 15:10:50 -06:00
Korey Sewell ab9c20cc78 inorder: regr-update: reduce dynamic mem. use to speedup sims
previous changesets took a closer look at memory mgmt in the inorder model and sought to avoid
dynamic memory mgmt (for access to pipeline resources) as much as possible. For the regressions
that were run, the sims are about 2x speedup from changeset 7726 which is the last change
since the recent commits in Feb. (note: these regressions now are 4-issue CPUs instead of just 1-issue)
2011-02-18 14:31:37 -05:00
Korey Sewell 2971b8401a inorder:regress: host-inst-rate improved ~58%
there are still only a few inorder benchmark but for the lengthier benchmarks (twolf and vortext)
the latest changes to how instruction scheduling (how instructions figure out what they want to
do on each pipeline stage in the inorder model) were able to improve performance by a nice
amount... The latest results for the inorder model process about 100k insts/second
(note: 58% is over the last time run on 64-bit pool machines at UM)
2011-02-12 10:14:52 -05:00
Gabe Black 0851580aad Stats: Re update stats. 2011-02-07 19:23:13 -08:00
Korey Sewell a48fe2729a imported patch regression_updates 2011-02-04 00:09:22 -05:00
Ali Saidi f7885b8f26 ARM/O3: Add regressions for ARM w/ O3 CPU. 2011-01-18 16:30:06 -06:00
Ali Saidi 9b67f3723e Stats: Update stats for previous set of patches. 2011-01-18 16:30:06 -06:00
Ali Saidi 371110fb0a Regressions: Update regressions for SIMD opclass changes 2010-11-15 14:04:05 -06:00
Ali Saidi 06c5283930 ARM: Update SE stats for TLB stats additions 2010-11-08 13:59:35 -06:00
Ali Saidi b4b6a2338a ARM/Alpha/Cpu: Stats change for prefetchs to be more like normal loads. 2010-11-08 13:58:24 -06:00
Steve Reinhardt 13a15c55a4 stats: update stats for previous cset
Coherence protocol change basically got rid
of UpgradeReqs in L2 caches, other minor
related cache stat changes.
2010-09-21 23:07:35 -07:00
Steve Reinhardt 9e45ada171 stats: update stats for preceding coherence changes
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
2010-09-09 14:40:19 -04:00
Ali Saidi e6d3fe8a0c ARM: Update regression tests for ldr/str microcode changes. 2010-08-25 19:10:42 -05:00
Steve Reinhardt 0f8b5afd7a tests: update reference config.ini files for previous cset
Rename 'responder_set' to 'use_default_range'.
2010-08-17 05:06:22 -07:00
Ali Saidi 1b73376b0b ARM: Add regression tests 2010-07-27 01:03:44 -04:00
Korey Sewell f2eba81f50 inorder: update regressions from RAS fix 2010-06-25 17:42:55 -04:00
Korey Sewell 0135cdab8d inorder: update regressions 2010-06-24 15:34:21 -04:00
Korey Sewell e17c41c176 inorder: update regressions 2010-06-23 18:21:44 -04:00
m5test 744b59d6de tests: Update O3 ref outputs to reflect Lisa's dist format change. 2010-06-06 18:39:10 -04:00
Ali Saidi e63c73b45d BPRED: Update regressions for tournament predictor fix. 2010-05-13 23:45:59 -04:00
Korey Sewell c90ee27283 inorder: update regressions for fwd-ing patch 2010-04-11 00:21:49 -04:00
Korey Sewell 941399728f inorder: update twolf/vortex regressions 2010-03-27 02:21:22 -04:00
Korey Sewell ef0fb9bee4 inorder: update vortex regression 2010-03-22 23:39:23 -04:00
Lisa Hsu ee20a7c0bd stats: update stats for the changes I pushed re: shared cache occupancy 2010-02-25 10:08:41 -08:00
Korey Sewell a3c635f777 inorder: vortex alpha regression 2010-01-31 18:31:20 -05:00
Nathan Binkert 9a8cb7db7e python: Move more code into m5.util allow SCons to use that code.
Get rid of misc.py and just stick misc things in __init__.py
Move utility functions out of SCons files and into m5.util
Move utility type stuff from m5/__init__.py to m5/util/__init__.py
Remove buildEnv from m5 and allow access only from m5.defines
Rename AddToPath to addToPath while we're moving it to m5.util
Rename read_command to readCommand while we're moving it
Rename compare_versions to compareVersions while we're moving it.

--HG--
rename : src/python/m5/convert.py => src/python/m5/util/convert.py
rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
2009-09-22 15:24:16 -07:00
Nathan Binkert e3e509b31a tests: stats outputs now include CDFs, update tests that use those so they're easier to diff 2009-07-06 15:49:48 -07:00
Gabe Black 5ae983f8da inorder: Fix up some reference stats. 2009-07-04 21:46:23 -07:00
Korey Sewell b5959124e1 inorder-regress: add vortex ALPHA_SE 2009-05-12 15:01:17 -04:00
Nathan Binkert 567cab6859 stats: update reference outputs now that compatibility is gone
Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 10:25:17 -07:00
Steve Reinhardt 7b40c36fbd Update stats for new single bad-address responder.
Mostly just config.ini updates, though the different response
latency for bad addresses caused very minor timing changes
in the O3 Linux boot tests.
2009-04-22 01:55:52 -04:00
Steve Reinhardt 48d4ca522a Update stats after elimination of Unallocated state.
Somehow ending threads with halt() instead of deallocate()
reduces the squash count on o3 by 1 (and a few other
similarly trivial changes).
2009-04-15 13:13:58 -07:00