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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt

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ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
sim_seconds 2.827616 # Number of seconds simulated
sim_ticks 2827616186000 # Number of ticks simulated
final_tick 2827616186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
host_inst_rate 97479 # Simulator instruction rate (inst/s)
host_op_rate 118241 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2435971946 # Simulator tick rate (ticks/s)
host_mem_usage 621864 # Number of bytes of host memory used
host_seconds 1160.78 # Real time elapsed on the host
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
sim_insts 113151083 # Number of instructions simulated
sim_ops 137250963 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bytes_read::cpu.inst 1325344 # Number of bytes read from this memory
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.bytes_read::cpu.data 9769960 # Number of bytes read from this memory
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.bytes_read::total 11098056 # Number of bytes read from this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bytes_inst_read::cpu.inst 1325344 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1325344 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8387584 # Number of bytes written to this memory
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bytes_written::total 8405108 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.num_reads::cpu.inst 22954 # Number of read requests responded to by this memory
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.num_reads::cpu.data 153176 # Number of read requests responded to by this memory
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.num_reads::total 176173 # Number of read requests responded to by this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.num_writes::writebacks 131056 # Number of write requests responded to by this memory
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.num_writes::total 135437 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 475 # Total read bandwidth from this memory (bytes/s)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bw_read::cpu.inst 468714 # Total read bandwidth from this memory (bytes/s)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.bw_read::cpu.data 3455193 # Total read bandwidth from this memory (bytes/s)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.bw_read::total 3924881 # Total read bandwidth from this memory (bytes/s)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bw_inst_read::cpu.inst 468714 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 468714 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2966309 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 6197 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2972507 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2966309 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 475 # Total bandwidth to/from this memory (bytes/s)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bw_total::cpu.inst 468714 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.bw_total::cpu.data 3461391 # Total bandwidth to/from this memory (bytes/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.bw_total::total 6897387 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 176174 # Number of read requests accepted
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.writeReqs 171661 # Number of write requests accepted
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.readBursts 176174 # Number of DRAM read bursts, including those serviced by the write queue
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.writeBursts 171661 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 11266304 # Total number of bytes read from DRAM
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.bytesReadWrQ 8832 # Total number of bytes read from write queue
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bytesWritten 9457344 # Total number of bytes written to DRAM
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.bytesReadSys 11098120 # Total read bytes from the system interface side
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bytesWrittenSys 10723444 # Total written bytes from the system interface side
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.servicedByWrQ 138 # Number of DRAM read bursts serviced by the write queue
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.mergedWrBursts 23861 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 4579 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 11334 # Per bank write bursts
system.physmem.perBankRdBursts::1 10890 # Per bank write bursts
system.physmem.perBankRdBursts::2 10732 # Per bank write bursts
system.physmem.perBankRdBursts::3 10393 # Per bank write bursts
system.physmem.perBankRdBursts::4 14045 # Per bank write bursts
system.physmem.perBankRdBursts::5 11531 # Per bank write bursts
system.physmem.perBankRdBursts::6 11498 # Per bank write bursts
system.physmem.perBankRdBursts::7 11674 # Per bank write bursts
system.physmem.perBankRdBursts::8 10645 # Per bank write bursts
system.physmem.perBankRdBursts::9 10993 # Per bank write bursts
system.physmem.perBankRdBursts::10 10307 # Per bank write bursts
system.physmem.perBankRdBursts::11 9597 # Per bank write bursts
system.physmem.perBankRdBursts::12 9956 # Per bank write bursts
system.physmem.perBankRdBursts::13 10908 # Per bank write bursts
system.physmem.perBankRdBursts::14 10689 # Per bank write bursts
system.physmem.perBankRdBursts::15 10844 # Per bank write bursts
system.physmem.perBankWrBursts::0 9257 # Per bank write bursts
system.physmem.perBankWrBursts::1 9346 # Per bank write bursts
system.physmem.perBankWrBursts::2 9336 # Per bank write bursts
system.physmem.perBankWrBursts::3 8962 # Per bank write bursts
system.physmem.perBankWrBursts::4 9705 # Per bank write bursts
system.physmem.perBankWrBursts::5 9746 # Per bank write bursts
system.physmem.perBankWrBursts::6 9125 # Per bank write bursts
system.physmem.perBankWrBursts::7 9630 # Per bank write bursts
system.physmem.perBankWrBursts::8 9307 # Per bank write bursts
system.physmem.perBankWrBursts::9 9634 # Per bank write bursts
system.physmem.perBankWrBursts::10 8942 # Per bank write bursts
system.physmem.perBankWrBursts::11 8449 # Per bank write bursts
system.physmem.perBankWrBursts::12 8881 # Per bank write bursts
system.physmem.perBankWrBursts::13 9361 # Per bank write bursts
system.physmem.perBankWrBursts::14 9018 # Per bank write bursts
system.physmem.perBankWrBursts::15 9072 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.numWrRetry 58 # Number of times write queue was full causing retry
system.physmem.totGap 2827615975000 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.readPktSize::2 542 # Read request sizes (log2)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.readPktSize::3 14 # Read request sizes (log2)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.readPktSize::4 2994 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.readPktSize::6 172624 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.writePktSize::6 167280 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 154910 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 18105 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 2183 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 821 # What read queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.wrQLenPdf::15 1641 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 1756 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5177 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6016 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6189 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6349 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6399 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6912 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 8194 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 6687 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7233 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 8649 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7333 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7316 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 9234 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7906 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7485 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 7118 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1141 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 899 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 1255 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 2319 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 2443 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 2021 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 1971 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 2359 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1895 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 2077 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1665 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1811 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 1476 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 1370 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 1404 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 1002 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 739 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 403 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 312 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 216 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 192 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 196 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 152 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 154 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 155 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 90 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 104 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 97 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 77 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 87 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 66219 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 312.955255 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 183.034234 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 334.173316 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 24625 37.19% 37.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 15873 23.97% 61.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6865 10.37% 71.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3626 5.48% 77.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2732 4.13% 81.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1677 2.53% 83.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1136 1.72% 85.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1168 1.76% 87.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 8517 12.86% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 66219 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6252 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 28.154671 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 564.033809 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 6251 99.98% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 6252 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6252 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 23.635797 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.335011 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 41.227878 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-31 5914 94.59% 94.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-47 86 1.38% 95.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-63 17 0.27% 96.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-79 16 0.26% 96.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-95 17 0.27% 96.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-111 30 0.48% 97.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-127 32 0.51% 97.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-143 14 0.22% 97.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-159 17 0.27% 98.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-175 6 0.10% 98.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-191 22 0.35% 98.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-207 18 0.29% 98.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-223 7 0.11% 99.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-255 1 0.02% 99.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-271 1 0.02% 99.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-287 6 0.10% 99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-303 4 0.06% 99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::304-319 4 0.06% 99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-335 3 0.05% 99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-351 5 0.08% 99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-367 16 0.26% 99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::368-383 2 0.03% 99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-399 3 0.05% 99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::400-415 1 0.02% 99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::448-463 1 0.02% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::480-495 3 0.05% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::496-511 1 0.02% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-527 1 0.02% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::528-543 1 0.02% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::704-719 1 0.02% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::752-767 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6252 # Writes before turning the bus around for reads
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.totQLat 2104913750 # Total ticks spent queuing
system.physmem.totMemAccLat 5405588750 # Total ticks spent from burst creation until serviced by the DRAM
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.totBusLat 880180000 # Total ticks spent in databus transfers
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.avgQLat 11957.29 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.avgMemAccLat 30707.29 # Average memory access latency per DRAM burst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.avgRdBW 3.98 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.34 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.92 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 3.79 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.busUtil 0.06 # Data bus utilization in percentage
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.avgWrQLen 25.89 # Average write queue length when enqueuing
system.physmem.readRowHits 145058 # Number of row buffer hits during reads
system.physmem.writeRowHits 112529 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.avgGap 8129187.62 # Average gap between requests
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 260517600 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 142147500 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 718356600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 486693360 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem_0.actBackEnergy 81488169855 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1625088668250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1892870659965 # Total energy per rank (pJ)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_0.averagePower 669.422846 # Core power per rank (mW)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem_0.memoryStateTime::IDLE 2703351122494 # Time in different power states
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_0.memoryStateTime::REF 94420300000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem_0.memoryStateTime::ACT 29844456256 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_1.actEnergy 240098040 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 131005875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 654716400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 470862720 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem_1.actBackEnergy 80123990850 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1626285316500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1892592097185 # Total energy per rank (pJ)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_1.averagePower 669.324331 # Core power per rank (mW)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem_1.memoryStateTime::IDLE 2705354976994 # Time in different power states
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_1.memoryStateTime::REF 94420300000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem_1.memoryStateTime::ACT 27840895506 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.branchPred.lookups 46937284 # Number of BP lookups
system.cpu.branchPred.condPredicted 24041936 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1233234 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 29553356 # Number of BTB lookups
system.cpu.branchPred.BTBHits 21362007 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.branchPred.BTBHitPct 72.282847 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 11754741 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 33891 # Number of incorrect RAS predictions.
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dtb.walker.walks 72371 # Table walker walks requested
system.cpu.dtb.walker.walksShort 72371 # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29709 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22637 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore 20025 # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples 52346 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean 408.397967 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev 2384.163324 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-4095 50769 96.99% 96.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::4096-8191 522 1.00% 97.98% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::8192-12287 392 0.75% 98.73% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::12288-16383 322 0.62% 99.35% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::16384-20479 112 0.21% 99.56% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::20480-24575 191 0.36% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::24576-28671 14 0.03% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::28672-32767 8 0.02% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::32768-36863 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::36864-40959 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::40960-45055 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkWaitTime::45056-49151 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::61440-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total 52346 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples 17999 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 11613.492583 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 9112.637070 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 7625.312992 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-16383 13355 74.20% 74.20% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::16384-32767 4455 24.75% 98.95% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::32768-49151 181 1.01% 99.96% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::49152-65535 5 0.03% 99.98% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::81920-98303 2 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total 17999 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 117490693224 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean 0.629020 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev 0.491115 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0-1 117435257724 99.95% 99.95% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::2-3 37744500 0.03% 99.98% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::4-5 7698500 0.01% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::6-7 6179000 0.01% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::8-9 1033000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::10-11 848500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::12-13 1404000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::14-15 520500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::16-17 7500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 117490693224 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 6498 81.61% 81.61% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M 1464 18.39% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 7962 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72371 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72371 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7962 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7962 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 80333 # Table walker requests started/completed, data/inst
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.dtb.read_hits 25461869 # DTB read hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dtb.read_misses 62291 # DTB read misses
system.cpu.dtb.write_hits 19915387 # DTB write hits
system.cpu.dtb.write_misses 10080 # DTB write misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 348 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 2290 # Number of TLB faults due to prefetch
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dtb.perms_faults 1335 # Number of TLB faults due to permissions restrictions
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.dtb.read_accesses 25524160 # DTB read accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dtb.write_accesses 19925467 # DTB write accesses
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.dtb.hits 45377256 # DTB hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dtb.misses 72371 # DTB misses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.dtb.accesses 45449627 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.itb.walker.walks 11974 # Table walker walks requested
system.cpu.itb.walker.walksShort 11974 # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1 3948 # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksShortTerminationLevel::Level2 7776 # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksSquashedBefore 250 # Table walks squashed before starting
system.cpu.itb.walker.walkWaitTime::samples 11724 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::mean 570.794951 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::stdev 2803.545728 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0-8191 11373 97.01% 97.01% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::8192-16383 269 2.29% 99.30% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::16384-24575 71 0.61% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::24576-32767 7 0.06% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::40960-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkWaitTime::49152-57343 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.itb.walker.walkWaitTime::73728-81919 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 11724 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples 3579 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 12176.865046 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 9546.126127 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 7774.383636 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-8191 1294 36.16% 36.16% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::8192-16383 1330 37.16% 73.32% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-24575 901 25.17% 98.49% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::24576-32767 22 0.61% 99.11% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::32768-40959 25 0.70% 99.80% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::40960-49151 5 0.14% 99.94% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::81920-90111 2 0.06% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total 3579 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 23001352712 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::mean 0.973391 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::stdev 0.161136 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 612637000 2.66% 2.66% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::1 22388223712 97.33% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::2 416000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::3 45500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::4 30500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 23001352712 # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K 3007 90.33% 90.33% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M 322 9.67% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 3329 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11974 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 11974 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3329 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3329 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 15303 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 66270436 # ITB inst hits
system.cpu.itb.inst_misses 11974 # ITB inst misses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.itb.perms_faults 2189 # Number of TLB faults due to permissions restrictions
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.itb.inst_accesses 66282410 # ITB inst accesses
system.cpu.itb.hits 66270436 # DTB hits
system.cpu.itb.misses 11974 # DTB misses
system.cpu.itb.accesses 66282410 # DTB accesses
system.cpu.numCycles 263104506 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.fetch.icacheStallCycles 104871759 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 184678718 # Number of instructions fetch has processed
system.cpu.fetch.Branches 46937284 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 33116748 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 147875517 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 6159108 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 184684 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 7836 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 337023 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 520063 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 109 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 66270632 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1094853 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 5249 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 256876545 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.877001 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.234757 # Number of instructions fetched each cycle (Total)
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.fetch.rateDist::0 157598366 61.35% 61.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 29238251 11.38% 72.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 14077167 5.48% 78.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 55962761 21.79% 100.00% # Number of instructions fetched each cycle (Total)
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.fetch.rateDist::total 256876545 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.178398 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.701922 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 78017085 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 107782223 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 64633482 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3841952 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 2601803 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3422699 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 486058 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 157446500 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 3690202 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 2601803 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 83861883 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 10277178 # Number of cycles rename is blocking
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.rename.serializeStallCycles 74822964 # count of cycles rename stalled for serializing inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.rename.RunCycles 62634848 # Number of cycles rename is running
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.rename.UnblockCycles 22677869 # Number of cycles rename is unblocking
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.rename.RenamedInsts 146804130 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 949467 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 441862 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 64017 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 17858 # Number of times rename has blocked due to LQ full
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.rename.SQFullEvents 19908152 # Number of times rename has blocked due to SQ full
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.rename.RenamedOperands 150492299 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 678751292 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 164435882 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 10966 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 141814735 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 8677561 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2844686 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2648369 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 13872312 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 26410080 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 21300681 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1687720 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2166938 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 143540852 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2119167 # Number of non-speculative instructions added to the IQ
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.iq.iqInstsIssued 143328298 # Number of instructions issued
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.iqSquashedInstsIssued 272168 # Number of squashed instructions issued
stats: update for previous changeset Very small differences in IQ-specific O3 stats.
2015-04-23 05:22:29 +02:00
system.cpu.iq.iqSquashedInstsExamined 8409052 # Number of squashed instructions iterated over during squash; mainly for profiling
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.iqSquashedOperandsExamined 14689564 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 125312 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 256876545 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.557966 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.879925 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.iq.issued_per_cycle::0 168573864 65.62% 65.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 45206232 17.60% 83.22% # Number of insts issued each cycle
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.issued_per_cycle::2 31980064 12.45% 95.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 10303635 4.01% 99.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 812717 0.32% 100.00% # Number of insts issued each cycle
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.issued_per_cycle::total 256876545 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.fu_full::IntAlu 7356620 32.59% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 33 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.59% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 5633879 24.95% 57.54% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 9585743 42.46% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.FU_type_0::IntAlu 96002656 66.98% 66.98% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 114517 0.08% 67.06% # Type of FU issued
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.FU_type_0::SimdFloatMisc 8586 0.01% 67.07% # Type of FU issued
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.iq.FU_type_0::MemRead 26193106 18.27% 85.34% # Type of FU issued
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.FU_type_0::MemWrite 21007096 14.66% 100.00% # Type of FU issued
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.iq.FU_type_0::total 143328298 # Type of FU issued
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.rate 0.544758 # Inst issue rate
system.cpu.iq.fu_busy_cnt 22576275 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.157514 # FU busy rate (busy events/executed inst)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.iq.int_inst_queue_reads 566346237 # Number of integer instruction queue reads
stats: update for previous changeset Very small differences in IQ-specific O3 stats.
2015-04-23 05:22:29 +02:00
system.cpu.iq.int_inst_queue_writes 154074171 # Number of integer instruction queue writes
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.int_inst_queue_wakeup_accesses 140211060 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 35347 # Number of floating instruction queue reads
stats: update for previous changeset Very small differences in IQ-specific O3 stats.
2015-04-23 05:22:29 +02:00
system.cpu.iq.fp_inst_queue_writes 13216 # Number of floating instruction queue writes
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.iq.int_alu_accesses 165879208 # Number of integer alu accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.fp_alu_accesses 23028 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 323617 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 1493976 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 505 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 18357 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 705133 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 87833 # Number of loads that were rescheduled
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.lsq.thread0.cacheBlocked 6849 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.iewSquashCycles 2601803 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 997477 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 311742 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 145861072 # Number of instructions dispatched to IQ
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.iewDispLoadInsts 26410080 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 21300681 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1095001 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 17866 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 276819 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 18357 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 317506 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 471434 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 788940 # Number of branch mispredicts detected at execute
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.iew.iewExecutedInsts 142382517 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 25789725 # Number of load instructions executed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.iewExecSquashedInsts 873528 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.exec_nop 201053 # number of nop insts executed
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.iew.exec_refs 46667574 # number of memory reference insts executed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.exec_branches 26530134 # Number of branches executed
system.cpu.iew.exec_stores 20877849 # Number of stores executed
system.cpu.iew.exec_rate 0.541163 # Inst execution rate
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.iew.wb_sent 141996041 # cumulative count of insts sent to commit
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.wb_count 140222490 # cumulative count of insts written-back
system.cpu.iew.wb_producers 63271750 # num instructions producing a value
system.cpu.iew.wb_consumers 95823649 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.wb_rate 0.532954 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.660294 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.commitSquashedInsts 7612502 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1993855 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 755483 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 253938585 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.541099 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.141491 # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.committed_per_cycle::0 180469459 71.07% 71.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 43296577 17.05% 88.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 15470824 6.09% 94.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 4378580 1.72% 95.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 6397908 2.52% 98.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1648304 0.65% 99.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 799189 0.31% 99.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 418335 0.16% 99.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 1059409 0.42% 100.00% # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.committed_per_cycle::total 253938585 # Number of insts commited each cycle
system.cpu.commit.committedInsts 113305988 # Number of instructions committed
system.cpu.commit.committedOps 137405868 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.refs 45511652 # Number of memory references committed
system.cpu.commit.loads 24916104 # Number of loads committed
system.cpu.commit.membars 814017 # Number of memory barriers committed
system.cpu.commit.branches 26045610 # Number of branches committed
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.int_insts 120229462 # Number of committed integer instructions.
system.cpu.commit.function_calls 4892502 # Number of function calls committed.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.op_class_0::IntAlu 91772138 66.79% 66.79% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 113493 0.08% 66.87% # Class of committed instruction
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.op_class_0::SimdFloatMisc 8585 0.01% 66.88% # Class of committed instruction
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.op_class_0::MemRead 24916104 18.13% 85.01% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 20595548 14.99% 100.00% # Class of committed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.op_class_0::total 137405868 # Class of committed instruction
system.cpu.commit.bw_lim_events 1059409 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 375672050 # The number of ROB reads
system.cpu.rob.rob_writes 292972268 # The number of ROB writes
system.cpu.timesIdled 891577 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 6227961 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 5392127867 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 113151083 # Number of Instructions Simulated
system.cpu.committedOps 137250963 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 2.325250 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.325250 # CPI: Total CPI of All Threads
system.cpu.ipc 0.430061 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.430061 # IPC: Total IPC of All Threads
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.int_regfile_reads 155826636 # number of integer regfile reads
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.int_regfile_writes 88633021 # number of integer regfile writes
system.cpu.fp_regfile_reads 9606 # number of floating regfile reads
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.fp_regfile_writes 2716 # number of floating regfile writes
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.cc_regfile_reads 502981878 # number of cc regfile reads
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.cc_regfile_writes 53178096 # number of cc regfile writes
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.misc_regfile_reads 446088160 # number of misc regfile reads
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.misc_regfile_writes 1519760 # number of misc regfile writes
system.cpu.dcache.tags.replacements 839617 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.954240 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 40126369 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 840129 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 47.762152 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 270754250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.954240 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999911 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999911 # Average percentage of cache occupancy
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.tag_accesses 179354797 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 179354797 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 23316087 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23316087 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 15561026 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 15561026 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 345829 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 345829 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 441066 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 441066 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 459481 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 459481 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 38877113 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 38877113 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 39222942 # number of overall hits
system.cpu.dcache.overall_hits::total 39222942 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 705718 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 705718 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 3595150 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 3595150 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 177438 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 177438 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 26862 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 26862 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 4300868 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 4300868 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4478306 # number of overall misses
system.cpu.dcache.overall_misses::total 4478306 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10273111663 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 10273111663 # number of ReadReq miss cycles
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502808344 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 149502808344 # number of WriteReq miss cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 365521996 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 365521996 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 209000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 209000 # number of StoreCondReq miss cycles
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.dcache.demand_miss_latency::cpu.data 159775920007 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 159775920007 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 159775920007 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 159775920007 # number of overall miss cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.ReadReq_accesses::cpu.data 24021805 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 24021805 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19156176 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19156176 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 523267 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 523267 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 467928 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 467928 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 459486 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 459486 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 43177981 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 43177981 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 43701248 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 43701248 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029378 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.029378 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.187676 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.187676 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339096 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.339096 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057406 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057406 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.099608 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.099608 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.102475 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.102475 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14556.964202 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14556.964202 # average ReadReq miss latency
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.581546 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.581546 # average WriteReq miss latency
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13607.400640 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13607.400640 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 41800 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 41800 # average StoreCondReq miss latency
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.691645 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 37149.691645 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.758511 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 35677.758511 # average overall miss latency
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 582483 # number of cycles access was blocked
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.blocked::no_mshrs 7397 # number of cycles access was blocked
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 78.745843 # average number of cycles each access was blocked
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.writebacks::writebacks 696320 # number of writebacks
system.cpu.dcache.writebacks::total 696320 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291077 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 291077 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3294875 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3294875 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18482 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 18482 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3585952 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3585952 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3585952 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3585952 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414641 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 414641 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300275 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 300275 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119609 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 119609 # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8380 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 8380 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 714916 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 714916 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 834525 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 834525 # number of overall MSHR misses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5660697158 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5660697158 # number of ReadReq MSHR miss cycles
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13235281165 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235281165 # number of WriteReq MSHR miss cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562991253 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562991253 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 123125251 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 123125251 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895978323 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 18895978323 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458969576 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 20458969576 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831942750 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831942750 # number of ReadReq MSHR uncacheable cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4511868951 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4511868951 # number of WriteReq MSHR uncacheable cycles
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10343811701 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 10343811701 # number of overall MSHR uncacheable cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017261 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017261 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015675 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015675 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228581 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228581 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017909 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017909 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016557 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.016557 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019096 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.019096 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13652.043956 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13652.043956 # average ReadReq mshr miss latency
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.199784 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.199784 # average WriteReq mshr miss latency
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13067.505397 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13067.505397 # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14692.750716 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14692.750716 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 40300 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 40300 # average StoreCondReq mshr miss latency
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.046896 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.046896 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.706032 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.706032 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187359.615446 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187359.615446 # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163568.334941 # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163568.334941 # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176181.834767 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176181.834767 # average overall mshr uncacheable latency
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.replacements 1892540 # number of replacements
system.cpu.icache.tags.tagsinuse 511.345997 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 64285030 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1893052 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 33.958407 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 13579028250 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.345997 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.998723 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.998723 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.tag_accesses 68160699 # Number of tag accesses
system.cpu.icache.tags.data_accesses 68160699 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 64285030 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 64285030 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 64285030 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 64285030 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 64285030 # number of overall hits
system.cpu.icache.overall_hits::total 64285030 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1982600 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1982600 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1982600 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1982600 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1982600 # number of overall misses
system.cpu.icache.overall_misses::total 1982600 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 26922947970 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 26922947970 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 26922947970 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 26922947970 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 26922947970 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 26922947970 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 66267630 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 66267630 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 66267630 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 66267630 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 66267630 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 66267630 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029918 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.029918 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.029918 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.029918 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.029918 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.029918 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13579.616650 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13579.616650 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13579.616650 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13579.616650 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13579.616650 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13579.616650 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 2392 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.blocked::no_mshrs 125 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 19.136000 # average number of cycles each access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 89529 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 89529 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 89529 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 89529 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 89529 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 89529 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1893071 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1893071 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1893071 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1893071 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1893071 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1893071 # number of overall MSHR misses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3002 # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total 3002 # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3002 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total 3002 # number of overall MSHR uncacheable misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23219754000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 23219754000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23219754000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 23219754000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23219754000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 23219754000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 225366000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 225366000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 225366000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 225366000 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028567 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.028567 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.028567 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12265.654062 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12265.654062 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75071.952032 # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75071.952032 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75071.952032 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75071.952032 # average overall mshr uncacheable latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.tags.replacements 103160 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65071.102218 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3020124 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 168359 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 17.938596 # Average number of references to valid blocks.
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 49253.315053 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 11.936082 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.797931 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 10086.820532 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 5716.232619 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.751546 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000182 # Average percentage of cache occupancy
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000043 # Average percentage of cache occupancy
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.153913 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.087223 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.992906 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65183 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2920 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6837 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55246 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994614 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 28477722 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 28477722 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 56030 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12587 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 1873051 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 528182 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2469850 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 696320 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 696320 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 36 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 36 # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 157101 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 157101 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 56030 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 12587 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 1873051 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 685283 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2626951 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 56030 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 12587 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 1873051 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 685283 # number of overall hits
system.cpu.l2cache.overall_hits::total 2626951 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 21 # number of ReadReq misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 19985 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 14326 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 34339 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2720 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2720 # number of UpgradeReq misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 140540 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 140540 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 21 # number of demand (read+write) misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.demand_misses::cpu.inst 19985 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 154866 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 174879 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 21 # number of overall misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.overall_misses::cpu.inst 19985 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 154866 # number of overall misses
system.cpu.l2cache.overall_misses::total 174879 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1759750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 789750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1637862750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1227493750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 2867906000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 966469 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 966469 # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 165000 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 165000 # number of SCUpgradeReq miss cycles
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11197753141 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 11197753141 # number of ReadExReq miss cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1759750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 789750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 1637862750 # number of demand (read+write) miss cycles
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.demand_miss_latency::cpu.data 12425246891 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 14065659141 # number of demand (read+write) miss cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1759750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 789750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 1637862750 # number of overall miss cycles
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.overall_miss_latency::cpu.data 12425246891 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 14065659141 # number of overall miss cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 56051 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12594 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1893036 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 542508 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2504189 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 696320 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 696320 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 297641 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 297641 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 56051 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 12594 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 1893036 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 840149 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2801830 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 56051 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 12594 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1893036 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 840149 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2801830 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000375 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000556 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010557 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026407 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.013713 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986938 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986938 # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.472180 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.472180 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000375 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000556 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010557 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.184332 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.062416 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000375 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000556 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010557 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.184332 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.062416 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 83797.619048 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 112821.428571 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81954.603453 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85682.936619 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 83517.458284 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 355.319485 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 355.319485 # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82500 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82500 # average SCUpgradeReq miss latency
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79676.626875 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79676.626875 # average ReadExReq miss latency
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80232.245238 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 80430.807250 # average overall miss latency
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80232.245238 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 80430.807250 # average overall miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.writebacks::writebacks 94866 # number of writebacks
system.cpu.l2cache.writebacks::total 94866 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 22 # number of ReadReq MSHR hits
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 112 # number of ReadReq MSHR hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_mshr_hits::total 134 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.demand_mshr_hits::cpu.data 112 # number of demand (read+write) MSHR hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.demand_mshr_hits::total 134 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.overall_mshr_hits::cpu.data 112 # number of overall MSHR hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.overall_mshr_hits::total 134 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 21 # number of ReadReq MSHR misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 19963 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14214 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 34205 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2720 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2720 # number of UpgradeReq MSHR misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 140540 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 140540 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 21 # number of demand (read+write) MSHR misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 19963 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 154754 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 174745 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 21 # number of overall MSHR misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 19963 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 154754 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 174745 # number of overall MSHR misses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3002 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34129 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3002 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61713 # number of overall MSHR uncacheable misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1495250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 701750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1386544250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1041614500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2430355750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 48397220 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48397220 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9440469859 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9440469859 # number of ReadExReq MSHR miss cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1495250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 701750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1386544250 # number of demand (read+write) MSHR miss cycles
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10482084359 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 11870825609 # number of demand (read+write) MSHR miss cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1495250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 701750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1386544250 # number of overall MSHR miss cycles
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10482084359 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 11870825609 # number of overall MSHR miss cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 181832000 # number of ReadReq MSHR uncacheable cycles
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5395669750 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5577501750 # number of ReadReq MSHR uncacheable cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151610000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151610000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 181832000 # number of overall MSHR uncacheable cycles
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547279750 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729111750 # number of overall MSHR uncacheable cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026201 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013659 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986938 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986938 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.472180 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.472180 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.184198 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.062368 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.184198 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.062368 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 100250 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69455.705555 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73280.885043 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71052.645812 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17793.095588 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17793.095588 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.832354 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.832354 # average ReadExReq mshr miss latency
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.850879 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.276225 # average overall mshr miss latency
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.850879 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.276225 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60570.286476 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173343.712854 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163424.118785 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150507.903132 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150507.903132 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60570.286476 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162614.837935 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157650.928492 # average overall mshr uncacheable latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.trans_dist::ReadReq 2564424 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2564404 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 696320 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36268 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 297641 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 297641 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3792109 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499777 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32094 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 131034 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.pkt_count::total 6455014 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121202208 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530845 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50376 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224204 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.pkt_size::total 220007633 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.snoops 62589 # Total snoops (count)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.snoop_fanout::samples 3624998 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1.036134 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.186622 # Request fanout histogram
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.snoop_fanout::1 3494014 96.39% 96.39% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 130984 3.61% 100.00% # Request fanout histogram
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 3624998 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 2504368734 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.snoopLayer0.occupancy 322500 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 2847443747 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 1338896897 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.respLayer2.occupancy 19507738 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.respLayer3.occupancy 75011458 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.trans_dist::ReadReq 30182 # Transaction distribution
system.iobus.trans_dist::ReadResp 30182 # Transaction distribution
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
system.iobus.trans_dist::WriteResp 22790 # Transaction distribution
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72914 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72914 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 178392 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321096 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321096 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.reqLayer27.occupancy 198816983 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.respLayer3.occupancy 36845510 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.tags.replacements 36423 # number of replacements
system.iocache.tags.tagsinuse 1.000480 # Cycle average of tags in use
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks.
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.tags.warmup_cycle 252520633000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 1.000480 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.062530 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.062530 # Average percentage of cache occupancy
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.tags.tag_accesses 328113 # Number of tag accesses
system.iocache.tags.data_accesses 328113 # Number of data accesses
system.iocache.ReadReq_misses::realview.ide 233 # number of ReadReq misses
system.iocache.ReadReq_misses::total 233 # number of ReadReq misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.demand_misses::realview.ide 233 # number of demand (read+write) misses
system.iocache.demand_misses::total 233 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 233 # number of overall misses
system.iocache.overall_misses::total 233 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 28780877 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 28780877 # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6657450596 # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total 6657450596 # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ide 28780877 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 28780877 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 28780877 # number of overall miss cycles
system.iocache.overall_miss_latency::total 28780877 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 233 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 233 # number of ReadReq accesses(hits+misses)
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.demand_accesses::realview.ide 233 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 233 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 233 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 233 # number of overall (read+write) accesses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 123523.077253 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 123523.077253 # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183785.628202 # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 183785.628202 # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 123523.077253 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 123523.077253 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 123523.077253 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 123523.077253 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 22928 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.blocked::no_mshrs 3494 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 6.562106 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.iocache.cache_copies 0 # number of cache copies performed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.ReadReq_mshr_misses::realview.ide 233 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 233 # number of ReadReq MSHR misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.demand_mshr_misses::realview.ide 233 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 233 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 233 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 233 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 16449877 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 16449877 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4773782616 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4773782616 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 16449877 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 16449877 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 16449877 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 16449877 # number of overall MSHR miss cycles
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70600.330472 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70600.330472 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131785.076634 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131785.076634 # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.membus.trans_dist::ReadReq 68567 # Transaction distribution
system.membus.trans_dist::ReadResp 68566 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.trans_dist::WriteReq 27584 # Transaction distribution
system.membus.trans_dist::WriteResp 27584 # Transaction distribution
system.membus.trans_dist::Writeback 131056 # Transaction distribution
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.trans_dist::UpgradeReq 4579 # Transaction distribution
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.trans_dist::UpgradeResp 4581 # Transaction distribution
system.membus.trans_dist::ReadExReq 138681 # Transaction distribution
system.membus.trans_dist::ReadExResp 138681 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465382 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572946 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108886 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 108886 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.membus.pkt_count::total 681832 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186044 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349437 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.membus.pkt_size::total 21984893 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.snoops 497 # Total snoops (count)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.membus.snoop_fanout::samples 406751 # Request fanout histogram
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.membus.snoop_fanout::1 406751 100.00% 100.00% # Request fanout histogram
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.membus.snoop_fanout::total 406751 # Request fanout histogram
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.reqLayer0.occupancy 83856500 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.reqLayer2.occupancy 1725500 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.membus.reqLayer5.occupancy 1057992643 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.membus.respLayer2.occupancy 1020413671 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 37506490 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink