2012-08-28 20:30:25 +02:00
---------- Begin Simulation Statistics ----------
2016-07-21 18:19:18 +02:00
sim_seconds 2.832894 # Number of seconds simulated
sim_ticks 2832894126500 # Number of ticks simulated
final_tick 2832894126500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2012-08-28 20:30:25 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-08-02 12:34:32 +02:00
host_inst_rate 74117 # Simulator instruction rate (inst/s)
host_op_rate 89897 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1856270381 # Simulator tick rate (ticks/s)
host_mem_usage 579324 # Number of bytes of host memory used
host_seconds 1526.12 # Real time elapsed on the host
2016-07-21 18:19:18 +02:00
sim_insts 113111333 # Number of instructions simulated
sim_ops 137193850 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-07-21 18:19:18 +02:00
system.physmem.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1321536 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9400296 # Number of bytes read from this memory
2014-11-12 15:05:25 +01:00
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
2016-07-21 18:19:18 +02:00
system.physmem.bytes_read::total 10724584 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1321536 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1321536 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8031104 # Number of bytes written to this memory
2014-10-30 05:18:29 +01:00
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
2016-07-21 18:19:18 +02:00
system.physmem.bytes_written::total 8048628 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 22896 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 147400 # Number of read requests responded to by this memory
2014-11-12 15:05:25 +01:00
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
2016-07-21 18:19:18 +02:00
system.physmem.num_reads::total 170339 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 125486 # Number of write requests responded to by this memory
2014-10-30 05:18:29 +01:00
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
2016-07-21 18:19:18 +02:00
system.physmem.num_writes::total 129867 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 474 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 466497 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3318266 # Total read bandwidth from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s)
2016-07-21 18:19:18 +02:00
system.physmem.bw_read::total 3785734 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 466497 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 466497 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2834947 # Write bandwidth from this memory (bytes/s)
2015-11-06 09:26:50 +01:00
system.physmem.bw_write::cpu.data 6186 # Write bandwidth from this memory (bytes/s)
2016-07-21 18:19:18 +02:00
system.physmem.bw_write::total 2841133 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2834947 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 474 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 466497 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3324452 # Total bandwidth to/from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s)
2016-07-21 18:19:18 +02:00
system.physmem.bw_total::total 6626867 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 170340 # Number of read requests accepted
system.physmem.writeReqs 129867 # Number of write requests accepted
system.physmem.readBursts 170340 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 129867 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 10892352 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue
system.physmem.bytesWritten 8061056 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 10724648 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 8048628 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue
2015-09-25 13:27:03 +02:00
system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-07-21 18:19:18 +02:00
system.physmem.perBankRdBursts::0 11036 # Per bank write bursts
system.physmem.perBankRdBursts::1 10507 # Per bank write bursts
system.physmem.perBankRdBursts::2 10862 # Per bank write bursts
system.physmem.perBankRdBursts::3 11068 # Per bank write bursts
system.physmem.perBankRdBursts::4 13101 # Per bank write bursts
system.physmem.perBankRdBursts::5 10327 # Per bank write bursts
system.physmem.perBankRdBursts::6 10639 # Per bank write bursts
system.physmem.perBankRdBursts::7 10985 # Per bank write bursts
system.physmem.perBankRdBursts::8 10460 # Per bank write bursts
system.physmem.perBankRdBursts::9 10167 # Per bank write bursts
system.physmem.perBankRdBursts::10 10435 # Per bank write bursts
system.physmem.perBankRdBursts::11 9511 # Per bank write bursts
system.physmem.perBankRdBursts::12 9930 # Per bank write bursts
system.physmem.perBankRdBursts::13 10756 # Per bank write bursts
system.physmem.perBankRdBursts::14 10401 # Per bank write bursts
system.physmem.perBankRdBursts::15 10008 # Per bank write bursts
system.physmem.perBankWrBursts::0 8291 # Per bank write bursts
system.physmem.perBankWrBursts::1 7865 # Per bank write bursts
system.physmem.perBankWrBursts::2 8399 # Per bank write bursts
system.physmem.perBankWrBursts::3 8558 # Per bank write bursts
system.physmem.perBankWrBursts::4 7751 # Per bank write bursts
system.physmem.perBankWrBursts::5 7713 # Per bank write bursts
system.physmem.perBankWrBursts::6 7781 # Per bank write bursts
system.physmem.perBankWrBursts::7 8111 # Per bank write bursts
system.physmem.perBankWrBursts::8 7871 # Per bank write bursts
system.physmem.perBankWrBursts::9 7662 # Per bank write bursts
system.physmem.perBankWrBursts::10 7844 # Per bank write bursts
system.physmem.perBankWrBursts::11 7196 # Per bank write bursts
system.physmem.perBankWrBursts::12 7582 # Per bank write bursts
system.physmem.perBankWrBursts::13 8119 # Per bank write bursts
system.physmem.perBankWrBursts::14 7846 # Per bank write bursts
system.physmem.perBankWrBursts::15 7365 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2016-07-21 18:19:18 +02:00
system.physmem.numWrRetry 17 # Number of times write queue was full causing retry
system.physmem.totGap 2832893894500 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
2015-05-05 09:22:39 +02:00
system.physmem.readPktSize::2 542 # Read request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.readPktSize::3 14 # Read request sizes (log2)
2015-09-25 13:27:03 +02:00
system.physmem.readPktSize::4 2996 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-07-21 18:19:18 +02:00
system.physmem.readPktSize::6 166788 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2016-07-21 18:19:18 +02:00
system.physmem.writePktSize::6 125486 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 150867 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 16439 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 2150 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 721 # What read queue length does an incoming req see
2016-04-09 18:13:40 +02:00
system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
2014-10-30 05:18:29 +01:00
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
2013-05-30 18:54:18 +02:00
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2016-07-21 18:19:18 +02:00
system.physmem.wrQLenPdf::15 1883 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2891 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 6675 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6069 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 7147 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6554 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6489 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6585 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 7283 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 7048 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7591 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 8460 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7511 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7926 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 8975 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7507 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7129 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 7208 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1140 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 304 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 257 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 207 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 209 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 194 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 202 # What write queue length does an incoming req see
2016-04-21 10:48:24 +02:00
system.physmem.wrQLenPdf::40 174 # What write queue length does an incoming req see
2016-07-21 18:19:18 +02:00
system.physmem.wrQLenPdf::41 169 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 125 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 132 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 146 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 130 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 137 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 108 # What write queue length does an incoming req see
2016-04-21 10:48:24 +02:00
system.physmem.wrQLenPdf::49 125 # What write queue length does an incoming req see
2016-07-21 18:19:18 +02:00
system.physmem.wrQLenPdf::50 113 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 138 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 125 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 79 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 117 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 55 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 104 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 81 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 48 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 79 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 69 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 35 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 56 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 62108 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 305.167515 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 180.813202 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 324.494619 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 23016 37.06% 37.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 15104 24.32% 61.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6524 10.50% 71.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3665 5.90% 77.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2528 4.07% 81.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1637 2.64% 84.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1479 2.38% 86.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1102 1.77% 88.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7053 11.36% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 62108 # Bytes accessed per row activation
2016-04-21 10:48:24 +02:00
system.physmem.rdPerTurnAround::samples 6142 # Reads before turning the bus around for writes
2016-07-21 18:19:18 +02:00
system.physmem.rdPerTurnAround::mean 27.706936 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 569.623530 # Reads before turning the bus around for writes
2016-04-21 10:48:24 +02:00
system.physmem.rdPerTurnAround::0-2047 6141 99.98% 99.98% # Reads before turning the bus around for writes
2015-09-25 13:27:03 +02:00
system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
2016-04-21 10:48:24 +02:00
system.physmem.rdPerTurnAround::total 6142 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6142 # Writes before turning the bus around for reads
2016-07-21 18:19:18 +02:00
system.physmem.wrPerTurnAround::mean 20.507001 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.506831 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 14.607971 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 5435 88.49% 88.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 129 2.10% 90.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 31 0.50% 91.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 49 0.80% 91.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 32 0.52% 92.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 17 0.28% 92.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 48 0.78% 93.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 14 0.23% 93.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 140 2.28% 95.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 11 0.18% 96.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 8 0.13% 96.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 8 0.13% 96.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 65 1.06% 97.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 1 0.02% 97.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 21 0.34% 97.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 93 1.51% 99.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 3 0.05% 99.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 1 0.02% 99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 1 0.02% 99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 1 0.02% 99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 2 0.03% 99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 3 0.05% 99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.02% 99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 11 0.18% 99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 1 0.02% 99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 1 0.02% 99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 2 0.03% 99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 7 0.11% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 1 0.02% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 1 0.02% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 1 0.02% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 2 0.03% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-211 1 0.02% 100.00% # Writes before turning the bus around for reads
2016-04-21 10:48:24 +02:00
system.physmem.wrPerTurnAround::total 6142 # Writes before turning the bus around for reads
2016-07-21 18:19:18 +02:00
system.physmem.totQLat 2108320500 # Total ticks spent queuing
system.physmem.totMemAccLat 5299439250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 850965000 # Total ticks spent in databus transfers
system.physmem.avgQLat 12387.82 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-07-21 18:19:18 +02:00
system.physmem.avgMemAccLat 31137.82 # Average memory access latency per DRAM burst
2015-09-25 13:27:03 +02:00
system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s
2016-07-21 18:19:18 +02:00
system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.79 # Average system read bandwidth in MiByte/s
2016-04-09 18:13:40 +02:00
system.physmem.avgWrBWSys 2.84 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-07-03 16:15:03 +02:00
system.physmem.busUtil 0.05 # Data bus utilization in percentage
2014-10-30 05:18:29 +01:00
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
2015-07-03 16:15:03 +02:00
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
2016-04-09 18:13:40 +02:00
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
2016-07-21 18:19:18 +02:00
system.physmem.avgWrQLen 25.42 # Average write queue length when enqueuing
system.physmem.readRowHits 139937 # Number of row buffer hits during reads
system.physmem.writeRowHits 94101 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.22 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes
system.physmem.avgGap 9436468.49 # Average gap between requests
system.physmem.pageHitRate 79.02 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 243454680 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 132837375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 690495000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 417759120 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 185030401920 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 83647548450 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1626357251250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1896519747795 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.465335 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2705450093000 # Time in different power states
system.physmem_0.memoryStateTime::REF 94596320000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-07-21 18:19:18 +02:00
system.physmem_0.memoryStateTime::ACT 32840757000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-07-21 18:19:18 +02:00
system.physmem_1.actEnergy 226081800 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 123358125 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 637002600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 398422800 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 185030401920 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 82216233135 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1627612791000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1896244291380 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.368099 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2707556632500 # Time in different power states
system.physmem_1.memoryStateTime::REF 94596320000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-07-21 18:19:18 +02:00
system.physmem_1.memoryStateTime::ACT 30741160500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-07-21 18:19:18 +02:00
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
2016-04-09 18:13:40 +02:00
system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 112 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 40 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 40 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 40 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s)
2016-07-21 18:19:18 +02:00
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
2012-08-28 20:30:25 +02:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
2014-10-30 05:18:29 +01:00
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
2016-07-21 18:19:18 +02:00
system.cpu.branchPred.lookups 46812529 # Number of BP lookups
system.cpu.branchPred.condPredicted 23980713 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1174980 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 29461889 # Number of BTB lookups
system.cpu.branchPred.BTBHits 13525990 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-07-21 18:19:18 +02:00
system.cpu.branchPred.BTBHitPct 45.910125 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 11726513 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 34925 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 7916092 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 7770128 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 145964 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 60126 # Number of mispredicted indirect branches.
2014-11-12 15:05:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2016-07-21 18:19:18 +02:00
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-07-21 18:19:18 +02:00
system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.cpu.checker.dtb.walker.walks 9712 # Table walker walks requested
system.cpu.checker.dtb.walker.walksShort 9712 # Table walker walks initiated with short descriptors
system.cpu.checker.dtb.walker.walkWaitTime::samples 9712 # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walkWaitTime::0 9712 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walkWaitTime::total 9712 # Table walker wait (enqueue to first request) latency
2015-09-25 13:27:03 +02:00
system.cpu.checker.dtb.walker.walksPending::samples 375751000 # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::0 375751000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::total 375751000 # Table walker pending requests distribution
2016-07-21 18:19:18 +02:00
system.cpu.checker.dtb.walker.walkPageSizes::4K 6218 82.38% 82.38% # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkPageSizes::1M 1330 17.62% 100.00% # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkPageSizes::total 7548 # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9712 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-07-21 18:19:18 +02:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9712 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7548 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-07-21 18:19:18 +02:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7548 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin::total 17260 # Table walker requests started/completed, data/inst
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
2016-07-21 18:19:18 +02:00
system.cpu.checker.dtb.read_hits 24578721 # DTB read hits
system.cpu.checker.dtb.read_misses 8315 # DTB read misses
system.cpu.checker.dtb.write_hits 19634427 # DTB write hits
system.cpu.checker.dtb.write_misses 1397 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-06-21 17:42:04 +02:00
system.cpu.checker.dtb.flush_entries 4219 # Number of entries that have been flushed from TLB
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
2016-07-21 18:19:18 +02:00
system.cpu.checker.dtb.prefetch_faults 1636 # Number of TLB faults due to prefetch
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2014-10-30 05:18:29 +01:00
system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
2016-07-21 18:19:18 +02:00
system.cpu.checker.dtb.read_accesses 24587036 # DTB read accesses
system.cpu.checker.dtb.write_accesses 19635824 # DTB write accesses
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
2016-07-21 18:19:18 +02:00
system.cpu.checker.dtb.hits 44213148 # DTB hits
system.cpu.checker.dtb.misses 9712 # DTB misses
system.cpu.checker.dtb.accesses 44222860 # DTB accesses
system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-07-21 18:19:18 +02:00
system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
2015-09-25 13:27:03 +02:00
system.cpu.checker.itb.walker.walks 4825 # Table walker walks requested
system.cpu.checker.itb.walker.walksShort 4825 # Table walker walks initiated with short descriptors
system.cpu.checker.itb.walker.walkWaitTime::samples 4825 # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walkWaitTime::0 4825 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walkWaitTime::total 4825 # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walksPending::samples 375090000 # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::0 375090000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::total 375090000 # Table walker pending requests distribution
system.cpu.checker.itb.walker.walkPageSizes::4K 2798 88.26% 88.26% # Table walker page sizes translated
system.cpu.checker.itb.walker.walkPageSizes::1M 372 11.74% 100.00% # Table walker page sizes translated
system.cpu.checker.itb.walker.walkPageSizes::total 3170 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 4825 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 4825 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 3170 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 3170 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin::total 7995 # Table walker requests started/completed, data/inst
2016-07-21 18:19:18 +02:00
system.cpu.checker.itb.inst_hits 115810053 # ITB inst hits
2015-09-25 13:27:03 +02:00
system.cpu.checker.itb.inst_misses 4825 # ITB inst misses
2012-08-28 20:30:25 +02:00
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.write_hits 0 # DTB write hits
system.cpu.checker.itb.write_misses 0 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu.checker.itb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.checker.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-06-21 17:42:04 +02:00
system.cpu.checker.itb.flush_entries 2912 # Number of entries that have been flushed from TLB
2012-08-28 20:30:25 +02:00
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
2016-07-21 18:19:18 +02:00
system.cpu.checker.itb.inst_accesses 115814878 # ITB inst accesses
system.cpu.checker.itb.hits 115810053 # DTB hits
2015-09-25 13:27:03 +02:00
system.cpu.checker.itb.misses 4825 # DTB misses
2016-07-21 18:19:18 +02:00
system.cpu.checker.itb.accesses 115814878 # DTB accesses
system.cpu.checker.pwrStateResidencyTicks::ON 2832894126500 # Cumulative time (in ticks) in various power states
system.cpu.checker.numCycles 139044613 # number of cpu cycles simulated
2012-08-28 20:30:25 +02:00
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-07-21 18:19:18 +02:00
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-07-21 18:19:18 +02:00
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 72186 # Table walker walks requested
system.cpu.dtb.walker.walksShort 72186 # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29334 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23181 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore 19671 # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples 52515 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean 467.713986 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev 2821.743931 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-8191 51203 97.50% 97.50% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::8192-16383 905 1.72% 99.22% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::16384-24575 322 0.61% 99.84% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::24576-32767 40 0.08% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::32768-40959 18 0.03% 99.95% # Table walker wait (enqueue to first request) latency
2016-04-21 10:48:24 +02:00
system.cpu.dtb.walker.walkWaitTime::40960-49151 21 0.04% 99.99% # Table walker wait (enqueue to first request) latency
2016-04-09 18:13:40 +02:00
system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::57344-65535 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::90112-98303 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
2016-07-21 18:19:18 +02:00
system.cpu.dtb.walker.walkWaitTime::total 52515 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples 17658 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 12583.333333 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 10066.135653 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 8522.119991 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-32767 17438 98.75% 98.75% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::32768-65535 214 1.21% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-163839 4 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-360447 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total 17658 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 131358619316 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean 0.629965 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev 0.490082 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0-1 131298865316 99.95% 99.95% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::2-3 40695500 0.03% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::4-5 8747000 0.01% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::6-7 6751500 0.01% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::8-9 1053500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::10-11 584000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::12-13 1412000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::14-15 501000 0.00% 100.00% # Table walker pending requests distribution
2016-04-09 18:13:40 +02:00
system.cpu.dtb.walker.walksPending::16-17 9500 0.00% 100.00% # Table walker pending requests distribution
2016-07-21 18:19:18 +02:00
system.cpu.dtb.walker.walksPending::total 131358619316 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 6349 82.25% 82.25% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M 1370 17.75% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 7719 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72186 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-07-21 18:19:18 +02:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72186 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7719 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-07-21 18:19:18 +02:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7719 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 79905 # Table walker requests started/completed, data/inst
2012-08-28 20:30:25 +02:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
2016-07-21 18:19:18 +02:00
system.cpu.dtb.read_hits 25413003 # DTB read hits
system.cpu.dtb.read_misses 62542 # DTB read misses
system.cpu.dtb.write_hits 19866296 # DTB write hits
system.cpu.dtb.write_misses 9644 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-06-21 17:42:04 +02:00
system.cpu.dtb.flush_entries 4253 # Number of entries that have been flushed from TLB
2016-07-21 18:19:18 +02:00
system.cpu.dtb.align_faults 366 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 2075 # Number of TLB faults due to prefetch
2012-08-28 20:30:25 +02:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-07-21 18:19:18 +02:00
system.cpu.dtb.perms_faults 1321 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 25475545 # DTB read accesses
system.cpu.dtb.write_accesses 19875940 # DTB write accesses
2012-08-28 20:30:25 +02:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
2016-07-21 18:19:18 +02:00
system.cpu.dtb.hits 45279299 # DTB hits
system.cpu.dtb.misses 72186 # DTB misses
system.cpu.dtb.accesses 45351485 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-07-21 18:19:18 +02:00
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
2016-04-21 10:48:24 +02:00
system.cpu.itb.walker.walks 12817 # Table walker walks requested
system.cpu.itb.walker.walksShort 12817 # Table walker walks initiated with short descriptors
2016-07-21 18:19:18 +02:00
system.cpu.itb.walker.walksShortTerminationLevel::Level1 3407 # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksShortTerminationLevel::Level2 7692 # Level at which table walker walks with short descriptors terminate
2016-04-21 10:48:24 +02:00
system.cpu.itb.walker.walksSquashedBefore 1718 # Table walks squashed before starting
system.cpu.itb.walker.walkWaitTime::samples 11099 # Table walker wait (enqueue to first request) latency
2016-07-21 18:19:18 +02:00
system.cpu.itb.walker.walkWaitTime::mean 742.229030 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::stdev 3116.397220 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0-4095 10521 94.79% 94.79% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::4096-8191 119 1.07% 95.86% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::8192-12287 227 2.05% 97.91% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::12288-16383 123 1.11% 99.02% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::16384-20479 47 0.42% 99.44% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::20480-24575 47 0.42% 99.86% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.89% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::28672-32767 6 0.05% 99.95% # Table walker wait (enqueue to first request) latency
2016-04-21 10:48:24 +02:00
system.cpu.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency
2016-04-09 18:13:40 +02:00
system.cpu.itb.walker.walkWaitTime::36864-40959 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::40960-45055 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::53248-57343 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
2015-11-06 09:26:50 +01:00
system.cpu.itb.walker.walkWaitTime::57344-61439 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
2016-04-21 10:48:24 +02:00
system.cpu.itb.walker.walkWaitTime::total 11099 # Table walker wait (enqueue to first request) latency
2016-07-21 18:19:18 +02:00
system.cpu.itb.walker.walkCompletionTime::samples 5040 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 12026.488095 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 9684.197840 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 7608.176186 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-16383 4071 80.77% 80.77% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-32767 955 18.95% 99.72% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::32768-49151 11 0.22% 99.94% # Table walker service (enqueue to completion) latency
2016-04-09 18:13:40 +02:00
system.cpu.itb.walker.walkCompletionTime::49152-65535 1 0.02% 99.96% # Table walker service (enqueue to completion) latency
2016-03-16 21:03:49 +01:00
system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.04% 100.00% # Table walker service (enqueue to completion) latency
2016-07-21 18:19:18 +02:00
system.cpu.itb.walker.walkCompletionTime::total 5040 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 23984374916 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::mean 0.642154 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::stdev 0.479545 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 8584682500 35.79% 35.79% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::1 15397812416 64.20% 99.99% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::2 1792000 0.01% 100.00% # Table walker pending requests distribution
2016-04-09 18:13:40 +02:00
system.cpu.itb.walker.walksPending::3 88000 0.00% 100.00% # Table walker pending requests distribution
2016-07-21 18:19:18 +02:00
system.cpu.itb.walker.walksPending::total 23984374916 # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K 2987 89.92% 89.92% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M 335 10.08% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 3322 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-04-21 10:48:24 +02:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12817 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 12817 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-07-21 18:19:18 +02:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3322 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3322 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 16139 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 65982481 # ITB inst hits
2016-04-21 10:48:24 +02:00
system.cpu.itb.inst_misses 12817 # ITB inst misses
2012-08-28 20:30:25 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu.itb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-07-21 18:19:18 +02:00
system.cpu.itb.flush_entries 3021 # Number of entries that have been flushed from TLB
2012-08-28 20:30:25 +02:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-07-21 18:19:18 +02:00
system.cpu.itb.perms_faults 2147 # Number of TLB faults due to permissions restrictions
2012-08-28 20:30:25 +02:00
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
2016-07-21 18:19:18 +02:00
system.cpu.itb.inst_accesses 65995298 # ITB inst accesses
system.cpu.itb.hits 65982481 # DTB hits
2016-04-21 10:48:24 +02:00
system.cpu.itb.misses 12817 # DTB misses
2016-07-21 18:19:18 +02:00
system.cpu.itb.accesses 65995298 # DTB accesses
2016-06-06 18:16:44 +02:00
system.cpu.numPwrStateTransitions 6074 # Number of power state transitions
system.cpu.pwrStateClkGateDist::samples 3037 # Distribution of time spent in the clock gated state
2016-07-21 18:19:18 +02:00
system.cpu.pwrStateClkGateDist::mean 886948130.312150 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::stdev 17421700028.084686 # Distribution of time spent in the clock gated state
2016-06-06 18:16:44 +02:00
system.cpu.pwrStateClkGateDist::underflows 2966 97.66% 97.66% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1000-5e+10 65 2.14% 99.80% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.07% 99.90% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state
2016-07-21 18:19:18 +02:00
system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::max_value 499972891000 # Distribution of time spent in the clock gated state
2016-06-06 18:16:44 +02:00
system.cpu.pwrStateClkGateDist::total 3037 # Distribution of time spent in the clock gated state
2016-07-21 18:19:18 +02:00
system.cpu.pwrStateResidencyTicks::ON 139232654742 # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::CLK_GATED 2693661471758 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 278465363 # number of cpu cycles simulated
2012-08-28 20:30:25 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-07-21 18:19:18 +02:00
system.cpu.fetch.icacheStallCycles 104979858 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 184015649 # Number of instructions fetch has processed
system.cpu.fetch.Branches 46812529 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 33022631 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 161497089 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 6057652 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 189263 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 8972 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 337056 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 558097 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 172 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 65981271 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1027864 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 6246 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 270599333 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.829251 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.216918 # Number of instructions fetched each cycle (Total)
2012-08-28 20:30:25 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-07-21 18:19:18 +02:00
system.cpu.fetch.rateDist::0 171686790 63.45% 63.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 29154260 10.77% 74.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 14034299 5.19% 79.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 55723984 20.59% 100.00% # Number of instructions fetched each cycle (Total)
2012-08-28 20:30:25 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
2014-09-03 13:42:59 +02:00
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2016-07-21 18:19:18 +02:00
system.cpu.fetch.rateDist::total 270599333 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.168109 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.660821 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 77964907 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 121895477 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 64303176 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3866825 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 2568948 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3406986 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 467982 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 156982730 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 3511045 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 2568948 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 83721940 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 11815597 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 76560081 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 62413108 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 33519659 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 146432544 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 918349 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 465966 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 65322 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 18586 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 30762818 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 150226924 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 676971311 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 163962292 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 10893 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 141750491 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 8476427 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2839737 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2644396 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 13885386 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 26339908 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 21214343 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1703941 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2126584 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 143224778 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2118002 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 143047064 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 260478 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 8148926 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 14278560 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 121950 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 270599333 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.528631 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.865147 # Number of insts issued each cycle
2012-08-28 20:30:25 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-07-21 18:19:18 +02:00
system.cpu.iq.issued_per_cycle::0 182394036 67.40% 67.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 45259787 16.73% 84.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 31866202 11.78% 95.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 10262392 3.79% 99.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 816883 0.30% 100.00% # Number of insts issued each cycle
2015-11-06 09:26:50 +01:00
system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle
2014-09-03 13:42:59 +02:00
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
2012-08-28 20:30:25 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2014-09-03 13:42:59 +02:00
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2016-07-21 18:19:18 +02:00
system.cpu.iq.issued_per_cycle::total 270599333 # Number of insts issued each cycle
2012-08-28 20:30:25 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-07-21 18:19:18 +02:00
system.cpu.iq.fu_full::IntAlu 7342152 32.76% 32.76% # attempts to use FU when none available
2016-04-21 10:48:24 +02:00
system.cpu.iq.fu_full::IntMult 32 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available
2016-07-21 18:19:18 +02:00
system.cpu.iq.fu_full::MemRead 5622313 25.09% 57.86% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 9444091 42.14% 100.00% # attempts to use FU when none available
2012-08-28 20:30:25 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2014-10-30 05:18:29 +01:00
system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued
2016-07-21 18:19:18 +02:00
system.cpu.iq.FU_type_0::IntAlu 95850690 67.01% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 114288 0.08% 67.09% # Type of FU issued
2016-04-09 18:13:40 +02:00
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued
2016-07-21 18:19:18 +02:00
system.cpu.iq.FU_type_0::SimdFloatMisc 8577 0.01% 67.09% # Type of FU issued
2016-04-09 18:13:40 +02:00
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.09% # Type of FU issued
2016-07-21 18:19:18 +02:00
system.cpu.iq.FU_type_0::MemRead 26130891 18.27% 85.36% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 20940281 14.64% 100.00% # Type of FU issued
2012-08-28 20:30:25 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-07-21 18:19:18 +02:00
system.cpu.iq.FU_type_0::total 143047064 # Type of FU issued
system.cpu.iq.rate 0.513698 # Inst issue rate
system.cpu.iq.fu_busy_cnt 22408588 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.156652 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 579326888 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 153497201 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 139997351 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 35639 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 13116 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 11369 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 165429916 # Number of integer alu accesses
2016-04-21 10:48:24 +02:00
system.cpu.iq.fp_alu_accesses 23399 # Number of floating point alu accesses
2016-07-21 18:19:18 +02:00
system.cpu.iew.lsq.thread0.forwLoads 323958 # Number of loads that had data forwarded from stores
2012-08-28 20:30:25 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-07-21 18:19:18 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 1433781 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 712 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 18665 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 622043 # Number of stores squashed
2012-08-28 20:30:25 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-07-21 18:19:18 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 88844 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 6344 # Number of times an access to memory failed due to the cache being blocked
2012-08-28 20:30:25 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-07-21 18:19:18 +02:00
system.cpu.iew.iewSquashCycles 2568948 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1241907 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 544667 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 145523405 # Number of instructions dispatched to IQ
2014-09-03 13:42:59 +02:00
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2016-07-21 18:19:18 +02:00
system.cpu.iew.iewDispLoadInsts 26339908 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 21214343 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1094304 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 17849 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 508298 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 18665 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 277238 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 471000 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 748238 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 142148555 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 25736254 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 826428 # Number of squashed instructions skipped in execute
2012-08-28 20:30:25 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
2016-07-21 18:19:18 +02:00
system.cpu.iew.exec_nop 180625 # number of nop insts executed
system.cpu.iew.exec_refs 46564673 # number of memory reference insts executed
system.cpu.iew.exec_branches 26492434 # Number of branches executed
system.cpu.iew.exec_stores 20828419 # Number of stores executed
system.cpu.iew.exec_rate 0.510471 # Inst execution rate
system.cpu.iew.wb_sent 141779361 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 140008720 # cumulative count of insts written-back
system.cpu.iew.wb_producers 63240555 # num instructions producing a value
system.cpu.iew.wb_consumers 95712709 # num instructions consuming a value
system.cpu.iew.wb_rate 0.502787 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.660733 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 7366290 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1996052 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 715102 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 267708008 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.513054 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.118068 # Number of insts commited each cycle
2012-08-28 20:30:25 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-07-21 18:19:18 +02:00
system.cpu.commit.committed_per_cycle::0 194252968 72.56% 72.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 43305040 16.18% 88.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 15457612 5.77% 94.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 4371808 1.63% 96.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 6428406 2.40% 98.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1610065 0.60% 99.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 797962 0.30% 99.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 411830 0.15% 99.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 1072317 0.40% 100.00% # Number of insts commited each cycle
2012-08-28 20:30:25 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-07-21 18:19:18 +02:00
system.cpu.commit.committed_per_cycle::total 267708008 # Number of insts commited each cycle
system.cpu.commit.committedInsts 113266238 # Number of instructions committed
system.cpu.commit.committedOps 137348755 # Number of ops (including micro ops) committed
2012-08-28 20:30:25 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2016-07-21 18:19:18 +02:00
system.cpu.commit.refs 45498427 # Number of memory references committed
system.cpu.commit.loads 24906127 # Number of loads committed
system.cpu.commit.membars 814995 # Number of memory barriers committed
system.cpu.commit.branches 26026646 # Number of branches committed
2015-09-25 13:27:03 +02:00
system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions.
2016-07-21 18:19:18 +02:00
system.cpu.commit.int_insts 120175202 # Number of committed integer instructions.
system.cpu.commit.function_calls 4885014 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2016-07-21 18:19:18 +02:00
system.cpu.commit.op_class_0::IntAlu 91728959 66.79% 66.79% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 112792 0.08% 66.87% # Class of committed instruction
2014-10-30 05:18:29 +01:00
system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction
2016-07-21 18:19:18 +02:00
system.cpu.commit.op_class_0::SimdFloatMisc 8577 0.01% 66.87% # Class of committed instruction
2015-09-25 13:27:03 +02:00
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction
2016-07-21 18:19:18 +02:00
system.cpu.commit.op_class_0::MemRead 24906127 18.13% 85.01% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 20592300 14.99% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-07-21 18:19:18 +02:00
system.cpu.commit.op_class_0::total 137348755 # Class of committed instruction
system.cpu.commit.bw_lim_events 1072317 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 389160423 # The number of ROB reads
system.cpu.rob.rob_writes 292308325 # The number of ROB writes
system.cpu.timesIdled 890756 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7866030 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 5387322891 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 113111333 # Number of Instructions Simulated
system.cpu.committedOps 137193850 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 2.461870 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.461870 # CPI: Total CPI of All Threads
system.cpu.ipc 0.406195 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.406195 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 155535200 # number of integer regfile reads
system.cpu.int_regfile_writes 88495254 # number of integer regfile writes
system.cpu.fp_regfile_reads 9528 # number of floating regfile reads
2014-10-30 05:18:29 +01:00
system.cpu.fp_regfile_writes 2716 # number of floating regfile writes
2016-07-21 18:19:18 +02:00
system.cpu.cc_regfile_reads 502191760 # number of cc regfile reads
system.cpu.cc_regfile_writes 53133619 # number of cc regfile writes
2016-08-02 12:34:32 +02:00
system.cpu.misc_regfile_reads 461629806 # number of misc regfile reads
2016-07-21 18:19:18 +02:00
system.cpu.misc_regfile_writes 1521804 # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 838109 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.925913 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 40060330 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 838621 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 47.769290 # Average number of references to valid blocks.
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit.
2016-07-21 18:19:18 +02:00
system.cpu.dcache.tags.occ_blocks::cpu.data 511.925913 # Average occupied blocks per requestor
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-07-21 18:19:18 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 358 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id
2014-11-12 15:05:25 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-07-21 18:19:18 +02:00
system.cpu.dcache.tags.tag_accesses 179138470 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 179138470 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 23266826 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23266826 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 15542812 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 15542812 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 345885 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 345885 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 441505 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 441505 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 460387 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 460387 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 38809638 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 38809638 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 39155523 # number of overall hits
system.cpu.dcache.overall_hits::total 39155523 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 704207 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 704207 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 3608607 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 3608607 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 177503 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 177503 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 27219 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 27219 # number of LoadLockedReq misses
2016-04-09 18:13:40 +02:00
system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses
2016-07-21 18:19:18 +02:00
system.cpu.dcache.demand_misses::cpu.data 4312814 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 4312814 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4490317 # number of overall misses
system.cpu.dcache.overall_misses::total 4490317 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11705123500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11705123500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 232670418192 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 232670418192 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376308000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 376308000 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 275000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 275000 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 244375541692 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 244375541692 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 244375541692 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 244375541692 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 23971033 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 23971033 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19151419 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19151419 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 523388 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 523388 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468724 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 468724 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460392 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 460392 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 43122452 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 43122452 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 43645840 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 43645840 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029377 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.029377 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188425 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.188425 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339142 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.339142 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.058070 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.058070 # miss rate for LoadLockedReq accesses
2016-04-09 18:13:40 +02:00
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses
2016-07-21 18:19:18 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.100013 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.100013 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.102881 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.102881 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16621.708532 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16621.708532 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64476.519109 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 64476.519109 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13825.195635 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13825.195635 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 55000 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 55000 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56662.666577 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 56662.666577 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54422.781664 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 54422.781664 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 867732 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-07-21 18:19:18 +02:00
system.cpu.dcache.blocked::no_mshrs 6871 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
2016-07-21 18:19:18 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 126.289041 # average number of cycles each access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-07-21 18:19:18 +02:00
system.cpu.dcache.writebacks::writebacks 696134 # number of writebacks
system.cpu.dcache.writebacks::total 696134 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 290642 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 290642 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3308599 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3308599 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18782 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 18782 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3599241 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3599241 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3599241 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3599241 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 413565 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 413565 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300008 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 300008 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119442 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 119442 # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8437 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 8437 # number of LoadLockedReq MSHR misses
2016-04-09 18:13:40 +02:00
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses
2016-07-21 18:19:18 +02:00
system.cpu.dcache.demand_mshr_misses::cpu.data 713573 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 713573 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 833015 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 833015 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 31129 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses
2016-07-21 18:19:18 +02:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6383877500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6383877500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19987260971 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 19987260971 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1693165000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1693165000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 126972500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 126972500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 270000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 270000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26371138471 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 26371138471 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28064303471 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 28064303471 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6276254500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6276254500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6276254500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 6276254500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017253 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017253 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015665 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015665 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228209 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228209 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018000 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018000 # mshr miss rate for LoadLockedReq accesses
2016-04-09 18:13:40 +02:00
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses
2016-07-21 18:19:18 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016548 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.016548 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019086 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.019086 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15436.213171 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15436.213171 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66622.426639 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66622.426639 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14175.624990 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14175.624990 # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15049.484414 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15049.484414 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54000 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54000 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36956.469024 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 36956.469024 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33690.033758 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 33690.033758 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201620.819814 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201620.819814 # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106895.365671 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106895.365671 # average overall mshr uncacheable latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 1886431 # number of replacements
system.cpu.icache.tags.tagsinuse 511.154202 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 64000082 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1886943 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 33.917337 # Average number of references to valid blocks.
2016-04-09 18:13:40 +02:00
system.cpu.icache.tags.warmup_cycle 16319051500 # Cycle when the warmup percentage was hit.
2016-07-21 18:19:18 +02:00
system.cpu.icache.tags.occ_blocks::cpu.inst 511.154202 # Average occupied blocks per requestor
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.occ_percent::cpu.inst 0.998348 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.998348 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-07-21 18:19:18 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
2014-11-12 15:05:25 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-07-21 18:19:18 +02:00
system.cpu.icache.tags.tag_accesses 67865267 # Number of tag accesses
system.cpu.icache.tags.data_accesses 67865267 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 64000082 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 64000082 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 64000082 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 64000082 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 64000082 # number of overall hits
system.cpu.icache.overall_hits::total 64000082 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1978185 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1978185 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1978185 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1978185 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1978185 # number of overall misses
system.cpu.icache.overall_misses::total 1978185 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 28158737492 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 28158737492 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 28158737492 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 28158737492 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 28158737492 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 28158737492 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 65978267 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 65978267 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 65978267 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 65978267 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 65978267 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 65978267 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029982 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.029982 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.029982 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.029982 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.029982 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.029982 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14234.633006 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14234.633006 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14234.633006 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14234.633006 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14234.633006 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14234.633006 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 5390 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-07-21 18:19:18 +02:00
system.cpu.icache.blocked::no_mshrs 176 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2016-07-21 18:19:18 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 30.625000 # average number of cycles each access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-07-21 18:19:18 +02:00
system.cpu.icache.writebacks::writebacks 1886431 # number of writebacks
system.cpu.icache.writebacks::total 1886431 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91184 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 91184 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 91184 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 91184 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 91184 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 91184 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1887001 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1887001 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1887001 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1887001 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1887001 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1887001 # number of overall MSHR misses
2016-04-09 18:13:40 +02:00
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3003 # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3003 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses
2016-07-21 18:19:18 +02:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25189687497 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 25189687497 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25189687497 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 25189687497 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25189687497 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 25189687497 # number of overall MSHR miss cycles
2016-04-09 18:13:40 +02:00
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 377605500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 377605500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 377605500 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 377605500 # number of overall MSHR uncacheable cycles
2016-07-21 18:19:18 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028600 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028600 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028600 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.028600 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028600 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.028600 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13349.058902 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13349.058902 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13349.058902 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13349.058902 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13349.058902 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13349.058902 # average overall mshr miss latency
2016-04-09 18:13:40 +02:00
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125742.757243 # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125742.757243 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125742.757243 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125742.757243 # average overall mshr uncacheable latency
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 97066 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65034.676246 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 5004762 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 162374 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 30.822435 # Average number of references to valid blocks.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.tags.occ_blocks::writebacks 49586.658386 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 11.610418 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.677884 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 10386.588269 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 5047.141288 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.756632 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000177 # Average percentage of cache occupancy
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000041 # Average percentage of cache occupancy
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.158487 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.077013 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.992350 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 15 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65293 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2842 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6720 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55568 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000229 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996292 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 44286849 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 44286849 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 57782 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12059 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 69841 # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks 696134 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 696134 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1848502 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1848502 # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 60 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 60 # number of UpgradeReq hits
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 161598 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 161598 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1866971 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1866971 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 527952 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 527952 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 57782 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 12059 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 1866971 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 689550 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2626362 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 57782 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 12059 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 1866971 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 689550 # number of overall hits
system.cpu.l2cache.overall_hits::total 2626362 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 21 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 28 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2746 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2746 # number of UpgradeReq misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 135739 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 135739 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19929 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 19929 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 13357 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 13357 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 21 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 19929 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 149096 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 169053 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 21 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 19929 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 149096 # number of overall misses
system.cpu.l2cache.overall_misses::total 169053 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2978500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 929000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 3907500 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 2730500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 2730500 # number of UpgradeReq miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162000 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 17623320500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 17623320500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2639049500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 2639049500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1797637500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1797637500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2978500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 929000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 2639049500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 19420958000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 22063915000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2978500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 929000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 2639049500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 19420958000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 22063915000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 57803 # number of ReadReq accesses(hits+misses)
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12066 # number of ReadReq accesses(hits+misses)
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.ReadReq_accesses::total 69869 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks 696134 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 696134 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 1848502 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1848502 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2806 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2806 # number of UpgradeReq accesses(hits+misses)
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses)
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 297337 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 297337 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1886900 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 1886900 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 541309 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 541309 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 57803 # number of demand (read+write) accesses
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.demand_accesses::cpu.itb.walker 12066 # number of demand (read+write) accesses
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.demand_accesses::cpu.inst 1886900 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 838646 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2795415 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 57803 # number of overall (read+write) accesses
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.overall_accesses::cpu.itb.walker 12066 # number of overall (read+write) accesses
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.overall_accesses::cpu.inst 1886900 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 838646 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2795415 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000363 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000580 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.000401 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.978617 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.978617 # miss rate for UpgradeReq accesses
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.600000 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.600000 # miss rate for SCUpgradeReq accesses
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.456516 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.456516 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010562 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010562 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024675 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024675 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000363 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000580 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010562 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.177782 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.060475 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000363 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000580 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010562 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.177782 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.060475 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 141833.333333 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 132714.285714 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 139553.571429 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 994.355426 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 994.355426 # average UpgradeReq miss latency
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 54000 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 54000 # average SCUpgradeReq miss latency
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 129832.402626 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 129832.402626 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132422.575142 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132422.575142 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134583.926031 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134583.926031 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 141833.333333 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 132714.285714 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132422.575142 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 130258.075334 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 130514.779389 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 141833.333333 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 132714.285714 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132422.575142 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130258.075334 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 130514.779389 # average overall miss latency
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.writebacks::writebacks 89296 # number of writebacks
system.cpu.l2cache.writebacks::total 89296 # number of writebacks
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 26 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 26 # number of ReadCleanReq MSHR hits
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 112 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 112 # number of ReadSharedReq MSHR hits
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.inst 26 # number of demand (read+write) MSHR hits
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.data 112 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 138 # number of demand (read+write) MSHR hits
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.inst 26 # number of overall MSHR hits
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.data 112 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 138 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 21 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 28 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2746 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2746 # number of UpgradeReq MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 135739 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 135739 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19903 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19903 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 13245 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 13245 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 21 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 19903 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 148984 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 168915 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 21 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 19903 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 148984 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 168915 # number of overall MSHR misses
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3003 # number of ReadReq MSHR uncacheable
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34132 # number of ReadReq MSHR uncacheable
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3003 # number of overall MSHR uncacheable misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61717 # number of overall MSHR uncacheable misses
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2768500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 859000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3627500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 186762000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 186762000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 210500 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 210500 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16265930500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16265930500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2437107003 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2437107003 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1651792000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1651792000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2768500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 859000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2437107003 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17917722500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 20358457003 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2768500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 859000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2437107003 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17917722500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 20358457003 # number of overall MSHR miss cycles
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340067500 # number of ReadReq MSHR uncacheable cycles
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5887129500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6227197000 # number of ReadReq MSHR uncacheable cycles
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340067500 # number of overall MSHR uncacheable cycles
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5887129500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6227197000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000363 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000580 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000401 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.978617 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.978617 # mshr miss rate for UpgradeReq accesses
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for SCUpgradeReq accesses
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.456516 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.456516 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010548 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010548 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024468 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024468 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000363 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000580 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010548 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177648 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.060426 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000363 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000580 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010548 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177648 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.060426 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 131833.333333 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122714.285714 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 129553.571429 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68012.381646 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68012.381646 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70166.666667 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70166.666667 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119832.402626 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119832.402626 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122449.228910 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122449.228910 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124710.607777 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124710.607777 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 131833.333333 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122714.285714 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122449.228910 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120266.085620 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120524.861635 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 131833.333333 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122714.285714 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122449.228910 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120266.085620 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120524.861635 # average overall mshr miss latency
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113242.590743 # average ReadReq mshr uncacheable latency
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189120.418260 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182444.538849 # average ReadReq mshr uncacheable latency
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113242.590743 # average overall mshr uncacheable latency
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100267.900330 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 100899.217396 # average overall mshr uncacheable latency
system.cpu.toL2Bus.snoop_filter.tot_requests 5483160 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2757544 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 45002 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 381 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 381 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq 128619 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2557060 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.trans_dist::WritebackDirty 821637 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1886431 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 149968 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2806 # Transaction distribution
2016-04-09 18:13:40 +02:00
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.trans_dist::UpgradeResp 2811 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 297337 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 297337 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887001 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 541532 # Transaction distribution
2016-04-09 18:13:40 +02:00
system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5666337 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2638583 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30857 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 133499 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 8469276 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241541168 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98417449 # Cumulative packet size per connected master and slave (bytes)
2016-04-21 10:48:24 +02:00
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 48264 # Cumulative packet size per connected master and slave (bytes)
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 231212 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 340238093 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 194794 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 8145576 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 3054607 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.024758 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.155386 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.snoop_fanout::0 2978982 97.52% 97.52% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 75625 2.48% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.snoop_fanout::total 3054607 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 5400960498 # Layer occupancy (ticks)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.cpu.toL2Bus.snoopLayer0.occupancy 258877 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 2834452098 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 1304519551 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.respLayer2.occupancy 18799483 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.respLayer3.occupancy 75755880 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
2016-04-09 18:13:40 +02:00
system.iobus.trans_dist::ReadReq 30172 # Transaction distribution
system.iobus.trans_dist::ReadResp 30172 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
2016-04-09 18:13:40 +02:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72894 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72894 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 178372 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
2016-04-09 18:13:40 +02:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321016 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321016 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480141 # Cumulative packet size per connected master and slave (bytes)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer0.occupancy 43088500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer2.occupancy 326000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer3.occupancy 28000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer7.occupancy 92500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer8.occupancy 651500 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2016-03-16 21:03:49 +01:00
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer23.occupancy 6158500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer24.occupancy 33063500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer25.occupancy 187149991 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
2016-04-09 18:13:40 +02:00
system.iocache.tags.replacements 36413 # number of replacements
2016-07-21 18:19:18 +02:00
system.iocache.tags.tagsinuse 1.005857 # Cycle average of tags in use
2016-04-09 18:13:40 +02:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36429 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2016-07-21 18:19:18 +02:00
system.iocache.tags.warmup_cycle 256506730000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 1.005857 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.062866 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.062866 # Average percentage of cache occupancy
2014-10-30 05:18:29 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2016-04-09 18:13:40 +02:00
system.iocache.tags.tag_accesses 328023 # Number of tag accesses
system.iocache.tags.data_accesses 328023 # Number of data accesses
2016-07-21 18:19:18 +02:00
system.iocache.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
2016-04-09 18:13:40 +02:00
system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses
system.iocache.ReadReq_misses::total 223 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2016-04-21 10:48:24 +02:00
system.iocache.demand_misses::realview.ide 36447 # number of demand (read+write) misses
system.iocache.demand_misses::total 36447 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 36447 # number of overall misses
system.iocache.overall_misses::total 36447 # number of overall misses
2016-07-21 18:19:18 +02:00
system.iocache.ReadReq_miss_latency::realview.ide 28156877 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 28156877 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 4551348114 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4551348114 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 4579504991 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 4579504991 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 4579504991 # number of overall miss cycles
system.iocache.overall_miss_latency::total 4579504991 # number of overall miss cycles
2016-04-09 18:13:40 +02:00
system.iocache.ReadReq_accesses::realview.ide 223 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 223 # number of ReadReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2016-04-21 10:48:24 +02:00
system.iocache.demand_accesses::realview.ide 36447 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 36447 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 36447 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 36447 # number of overall (read+write) accesses
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2016-04-09 18:13:40 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2016-07-21 18:19:18 +02:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 126264.022422 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 126264.022422 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125644.548200 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125644.548200 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 125648.338437 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 125648.338437 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 125648.338437 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 125648.338437 # average overall miss latency
2016-04-21 10:48:24 +02:00
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2012-08-28 20:30:25 +02:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-04-21 10:48:24 +02:00
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
2012-08-28 20:30:25 +02:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2016-04-21 10:48:24 +02:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2012-08-28 20:30:25 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-04-09 18:13:40 +02:00
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide 223 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2016-04-21 10:48:24 +02:00
system.iocache.demand_mshr_misses::realview.ide 36447 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 36447 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 36447 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 36447 # number of overall MSHR misses
2016-07-21 18:19:18 +02:00
system.iocache.ReadReq_mshr_miss_latency::realview.ide 17006877 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 17006877 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2738747578 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2738747578 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 2755754455 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 2755754455 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 2755754455 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 2755754455 # number of overall MSHR miss cycles
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2016-04-09 18:13:40 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2016-07-21 18:19:18 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76264.022422 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 76264.022422 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75605.884993 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75605.884993 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 75609.911790 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 75609.911790 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75609.911790 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75609.911790 # average overall mshr miss latency
system.membus.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
2016-04-09 18:13:40 +02:00
system.membus.trans_dist::ReadReq 34132 # Transaction distribution
2016-07-21 18:19:18 +02:00
system.membus.trans_dist::ReadResp 67530 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::WriteReq 27585 # Transaction distribution
system.membus.trans_dist::WriteResp 27585 # Transaction distribution
2016-07-21 18:19:18 +02:00
system.membus.trans_dist::WritebackDirty 125486 # Transaction distribution
system.membus.trans_dist::CleanEvict 7993 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4611 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
2016-07-21 18:19:18 +02:00
system.membus.trans_dist::ReadExReq 133874 # Transaction distribution
system.membus.trans_dist::ReadExResp 133874 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 33399 # Transaction distribution
2016-04-09 18:13:40 +02:00
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
2016-04-09 18:13:40 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes)
2016-07-21 18:19:18 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 451368 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558936 # Packet count per connected master and slave (bytes)
2016-04-09 18:13:40 +02:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72875 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72875 # Packet count per connected master and slave (bytes)
2016-07-21 18:19:18 +02:00
system.membus.pkt_count::total 631811 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
2016-04-09 18:13:40 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes)
2016-07-21 18:19:18 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16456092 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16619481 # Cumulative packet size per connected master and slave (bytes)
2016-04-09 18:13:40 +02:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
2016-07-21 18:19:18 +02:00
system.membus.pkt_size::total 18936601 # Cumulative packet size per connected master and slave (bytes)
2016-04-09 18:13:40 +02:00
system.membus.snoops 487 # Total snoops (count)
2016-07-21 18:19:18 +02:00
system.membus.snoopTraffic 31040 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 403324 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2016-07-21 18:19:18 +02:00
system.membus.snoop_fanout::1 403324 100.00% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2016-07-21 18:19:18 +02:00
system.membus.snoop_fanout::total 403324 # Request fanout histogram
system.membus.reqLayer0.occupancy 83656500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.membus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.membus.reqLayer2.occupancy 1736499 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.membus.reqLayer5.occupancy 876921354 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.membus.respLayer2.occupancy 979994750 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.membus.respLayer3.occupancy 1182123 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2016-07-21 18:19:18 +02:00
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
2014-11-12 15:05:25 +01:00
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2016-07-21 18:19:18 +02:00
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2016-07-21 18:19:18 +02:00
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states
2012-08-28 20:30:25 +02:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
2015-09-25 13:27:03 +02:00
system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed
2012-08-28 20:30:25 +02:00
---------- End Simulation Statistics ----------
