2009-04-18 16:42:29 +02:00
---------- Begin Simulation Statistics ----------
2015-07-03 16:15:03 +02:00
sim_seconds 0.000022 # Number of seconds simulated
2015-11-06 09:26:50 +01:00
sim_ticks 22454000 # Number of ticks simulated
final_tick 22454000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-06-21 00:57:14 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
2015-11-06 09:26:50 +01:00
host_inst_rate 82798 # Simulator instruction rate (inst/s)
host_op_rate 82780 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 372464129 # Simulator tick rate (ticks/s)
host_mem_usage 294232 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
2014-10-20 23:48:19 +02:00
sim_insts 4986 # Number of instructions simulated
sim_ops 4986 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2015-09-15 15:14:09 +02:00
system.physmem.bytes_read::cpu.inst 20992 # Number of bytes read from this memory
2014-10-20 23:48:19 +02:00
system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory
2015-09-15 15:14:09 +02:00
system.physmem.bytes_read::total 30016 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 20992 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 20992 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 328 # Number of read requests responded to by this memory
2014-10-20 23:48:19 +02:00
system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
2015-09-15 15:14:09 +02:00
system.physmem.num_reads::total 469 # Number of read requests responded to by this memory
2015-11-06 09:26:50 +01:00
system.physmem.bw_read::cpu.inst 934889107 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 401888305 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1336777412 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 934889107 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 934889107 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 934889107 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 401888305 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1336777412 # Total bandwidth to/from this memory (bytes/s)
2015-09-15 15:14:09 +02:00
system.physmem.readReqs 469 # Number of read requests accepted
2013-11-01 16:56:34 +01:00
system.physmem.writeReqs 0 # Number of write requests accepted
2015-09-15 15:14:09 +02:00
system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue
2013-11-01 16:56:34 +01:00
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
2015-09-15 15:14:09 +02:00
system.physmem.bytesReadDRAM 30016 # Total number of bytes read from DRAM
2013-11-01 16:56:34 +01:00
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
2015-09-15 15:14:09 +02:00
system.physmem.bytesReadSys 30016 # Total read bytes from the system interface side
2013-11-01 16:56:34 +01:00
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2014-10-20 23:48:19 +02:00
system.physmem.perBankRdBursts::0 29 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::1 0 # Per bank write bursts
system.physmem.perBankRdBursts::2 1 # Per bank write bursts
system.physmem.perBankRdBursts::3 0 # Per bank write bursts
system.physmem.perBankRdBursts::4 7 # Per bank write bursts
system.physmem.perBankRdBursts::5 3 # Per bank write bursts
system.physmem.perBankRdBursts::6 13 # Per bank write bursts
2014-10-20 23:48:19 +02:00
system.physmem.perBankRdBursts::7 53 # Per bank write bursts
system.physmem.perBankRdBursts::8 59 # Per bank write bursts
system.physmem.perBankRdBursts::9 76 # Per bank write bursts
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::10 43 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::11 20 # Per bank write bursts
system.physmem.perBankRdBursts::12 51 # Per bank write bursts
system.physmem.perBankRdBursts::13 29 # Per bank write bursts
2015-09-15 15:14:09 +02:00
system.physmem.perBankRdBursts::14 78 # Per bank write bursts
2014-06-22 23:33:09 +02:00
system.physmem.perBankRdBursts::15 7 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
2015-11-06 09:26:50 +01:00
system.physmem.totGap 22367000 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2015-09-15 15:14:09 +02:00
system.physmem.readPktSize::6 469 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
2015-09-15 15:14:09 +02:00
system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see
2015-03-02 11:04:20 +01:00
system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see
2015-09-15 15:14:09 +02:00
system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
2015-09-15 15:14:09 +02:00
system.physmem.bytesPerActivate::samples 104 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 262.153846 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 180.926322 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 251.694944 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 29 27.88% 27.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 32 30.77% 58.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 20 19.23% 77.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 9 8.65% 86.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 4 3.85% 90.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 2 1.92% 92.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1 0.96% 93.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1 0.96% 94.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 6 5.77% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 104 # Bytes accessed per row activation
system.physmem.totQLat 4505500 # Total ticks spent queuing
system.physmem.totMemAccLat 13299250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers
system.physmem.avgQLat 9606.61 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2015-09-15 15:14:09 +02:00
system.physmem.avgMemAccLat 28356.61 # Average memory access latency per DRAM burst
2015-11-06 09:26:50 +01:00
system.physmem.avgRdBW 1336.78 # Average DRAM read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
2015-11-06 09:26:50 +01:00
system.physmem.avgRdBWSys 1336.78 # Average system read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-09-15 15:14:09 +02:00
system.physmem.busUtil 10.44 # Data bus utilization in percentage
system.physmem.busUtilRead 10.44 # Data bus utilization in percentage for reads
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
2015-09-15 15:14:09 +02:00
system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing
2013-11-01 16:56:34 +01:00
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
2015-09-15 15:14:09 +02:00
system.physmem.readRowHits 355 # Number of row buffer hits during reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
2015-09-15 15:14:09 +02:00
system.physmem.readRowHitRate 75.69 # Row buffer hit rate for reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
2015-11-06 09:26:50 +01:00
system.physmem.avgGap 47690.83 # Average gap between requests
2015-09-15 15:14:09 +02:00
system.physmem.pageHitRate 75.69 # Row buffer hit rate, read and write combined
2015-03-02 11:04:20 +01:00
system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ)
2015-09-15 15:14:09 +02:00
system.physmem_0.readEnergy 530400 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
2015-09-15 15:14:09 +02:00
system.physmem_0.actBackEnergy 9542655 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1130250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 12419070 # Total energy per rank (pJ)
system.physmem_0.averagePower 784.279760 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 1840500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-09-15 15:14:09 +02:00
system.physmem_0.memoryStateTime::ACT 13487750 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-09-15 15:14:09 +02:00
system.physmem_1.actEnergy 514080 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 280500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 2168400 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
2015-09-15 15:14:09 +02:00
system.physmem_1.actBackEnergy 10730250 # Energy for active background per rank (pJ)
2015-07-03 16:15:03 +02:00
system.physmem_1.preBackEnergy 87000 # Energy for precharge background per rank (pJ)
2015-09-15 15:14:09 +02:00
system.physmem_1.totalEnergy 14797350 # Total energy per rank (pJ)
system.physmem_1.averagePower 934.618664 # Core power per rank (mW)
2015-07-03 16:15:03 +02:00
system.physmem_1.memoryStateTime::IDLE 103500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-09-15 15:14:09 +02:00
system.physmem_1.memoryStateTime::ACT 15222750 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-09-15 15:14:09 +02:00
system.cpu.branchPred.lookups 2031 # Number of BP lookups
system.cpu.branchPred.condPredicted 1362 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 402 # Number of conditional branches incorrect
2015-07-03 16:15:03 +02:00
system.cpu.branchPred.BTBLookups 1641 # Number of BTB lookups
2015-09-15 15:14:09 +02:00
system.cpu.branchPred.BTBHits 605 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2015-09-15 15:14:09 +02:00
system.cpu.branchPred.BTBHitPct 36.867764 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 242 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 66 # Number of incorrect RAS predictions.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2009-04-18 16:42:29 +02:00
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
2011-06-21 00:57:14 +02:00
system.cpu.dtb.read_accesses 0 # DTB read accesses
2009-04-18 16:42:29 +02:00
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
2011-06-21 00:57:14 +02:00
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
2014-10-20 23:48:19 +02:00
system.cpu.workload.num_syscalls 7 # Number of system calls
2015-11-06 09:26:50 +01:00
system.cpu.numCycles 44909 # number of cpu cycles simulated
2011-06-21 00:57:14 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-09-15 15:14:09 +02:00
system.cpu.fetch.icacheStallCycles 8843 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 12328 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2031 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 847 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 4817 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 822 # Number of cycles fetch has spent squashing
system.cpu.fetch.PendingTrapStallCycles 190 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 1979 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 255 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 14261 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.864456 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.133927 # Number of instructions fetched each cycle (Total)
2009-07-07 00:49:48 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2015-09-15 15:14:09 +02:00
system.cpu.fetch.rateDist::0 10999 77.13% 77.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1480 10.38% 87.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 118 0.83% 88.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 169 1.19% 89.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 282 1.98% 91.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 102 0.72% 92.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 134 0.94% 93.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 153 1.07% 94.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 824 5.78% 100.00% # Number of instructions fetched each cycle (Total)
2009-07-07 00:49:48 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2015-09-15 15:14:09 +02:00
system.cpu.fetch.rateDist::total 14261 # Number of instructions fetched each cycle (Total)
2015-11-06 09:26:50 +01:00
system.cpu.fetch.branchRate 0.045225 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.274511 # Number of inst fetches per cycle
2015-09-15 15:14:09 +02:00
system.cpu.decode.IdleCycles 8380 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 2677 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2707 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 371 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 41 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 11351 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 162 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 371 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 8518 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 542 # Number of cycles rename is blocking
2015-07-03 16:15:03 +02:00
system.cpu.rename.serializeStallCycles 996 # count of cycles rename stalled for serializing inst
2015-09-15 15:14:09 +02:00
system.cpu.rename.RunCycles 2675 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 1159 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 10918 # Number of instructions processed by rename
2014-09-03 13:42:59 +02:00
system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
2015-09-15 15:14:09 +02:00
system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 179 # Number of times rename has blocked due to LQ full
2015-07-03 16:15:03 +02:00
system.cpu.rename.SQFullEvents 954 # Number of times rename has blocked due to SQ full
2015-09-15 15:14:09 +02:00
system.cpu.rename.RenamedOperands 6512 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 12905 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 12683 # Number of integer rename lookups
2013-10-16 16:44:12 +02:00
system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups
2014-10-20 23:48:19 +02:00
system.cpu.rename.CommittedMaps 3282 # Number of HB maps that are committed
2015-09-15 15:14:09 +02:00
system.cpu.rename.UndoneMaps 3230 # Number of HB maps that are undone due to squashing
2015-07-03 16:15:03 +02:00
system.cpu.rename.serializingInsts 14 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed
2015-09-15 15:14:09 +02:00
system.cpu.rename.skidInsts 314 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2295 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1159 # Number of stores inserted to the mem dependence unit.
2011-06-21 00:57:14 +02:00
system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
2014-10-20 23:48:19 +02:00
system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
2015-09-15 15:14:09 +02:00
system.cpu.iq.iqInstsAdded 8632 # Number of instructions added to the IQ (excludes non-spec)
2014-10-20 23:48:19 +02:00
system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ
2015-09-15 15:14:09 +02:00
system.cpu.iq.iqInstsIssued 7937 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 3656 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1608 # Number of squashed operands that are examined and possibly removed from graph
2013-05-30 18:54:18 +02:00
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
2015-09-15 15:14:09 +02:00
system.cpu.iq.issued_per_cycle::samples 14261 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.556553 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.276985 # Number of insts issued each cycle
2011-06-21 00:57:14 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2015-09-15 15:14:09 +02:00
system.cpu.iq.issued_per_cycle::0 10981 77.00% 77.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1321 9.26% 86.26% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 733 5.14% 91.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 439 3.08% 94.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 350 2.45% 96.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 277 1.94% 98.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 91 0.64% 99.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 50 0.35% 99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Number of insts issued each cycle
2011-06-21 00:57:14 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2015-09-15 15:14:09 +02:00
system.cpu.iq.issued_per_cycle::total 14261 # Number of insts issued each cycle
2011-06-21 00:57:14 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2015-09-15 15:14:09 +02:00
system.cpu.iq.fu_full::IntAlu 6 3.41% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 112 63.64% 67.05% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 58 32.95% 100.00% # attempts to use FU when none available
2011-06-21 00:57:14 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
2015-09-15 15:14:09 +02:00
system.cpu.iq.FU_type_0::IntAlu 4719 59.46% 59.46% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 4 0.05% 59.51% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 1 0.01% 59.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2143 27.00% 86.54% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1068 13.46% 100.00% # Type of FU issued
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2015-09-15 15:14:09 +02:00
system.cpu.iq.FU_type_0::total 7937 # Type of FU issued
2015-11-06 09:26:50 +01:00
system.cpu.iq.rate 0.176735 # Inst issue rate
2015-09-15 15:14:09 +02:00
system.cpu.iq.fu_busy_cnt 176 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.022175 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 30327 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 12306 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 7277 # Number of integer instruction queue wakeup accesses
2011-06-21 00:57:14 +02:00
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
2015-09-15 15:14:09 +02:00
system.cpu.iq.int_alu_accesses 8111 # Number of integer alu accesses
2011-06-21 00:57:14 +02:00
system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
2015-09-15 15:14:09 +02:00
system.cpu.iew.lsq.thread0.forwLoads 89 # Number of loads that had data forwarded from stores
2011-06-21 00:57:14 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2015-09-15 15:14:09 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 1163 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
2014-06-22 23:33:09 +02:00
system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations
2015-09-15 15:14:09 +02:00
system.cpu.iew.lsq.thread0.squashedStores 258 # Number of stores squashed
2011-06-21 00:57:14 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
2015-09-15 15:14:09 +02:00
system.cpu.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked
2011-06-21 00:57:14 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2015-09-15 15:14:09 +02:00
system.cpu.iew.iewSquashCycles 371 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 425 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 88 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 10126 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 130 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2295 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1159 # Number of dispatched store instructions
2014-10-20 23:48:19 +02:00
system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions
2014-09-03 13:42:59 +02:00
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
2015-09-15 15:14:09 +02:00
system.cpu.iew.iewLSQFullEvents 89 # Number of times the LSQ has become full, causing a stall
2014-06-22 23:33:09 +02:00
system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
2015-07-03 16:15:03 +02:00
system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly
2015-09-15 15:14:09 +02:00
system.cpu.iew.predictedNotTakenIncorrect 321 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 419 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 7671 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 2045 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 266 # Number of squashed instructions skipped in execute
2011-06-21 00:57:14 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
2015-09-15 15:14:09 +02:00
system.cpu.iew.exec_nop 1483 # number of nop insts executed
system.cpu.iew.exec_refs 3098 # number of memory reference insts executed
system.cpu.iew.exec_branches 1353 # Number of branches executed
2015-07-03 16:15:03 +02:00
system.cpu.iew.exec_stores 1053 # Number of stores executed
2015-11-06 09:26:50 +01:00
system.cpu.iew.exec_rate 0.170812 # Inst execution rate
2015-09-15 15:14:09 +02:00
system.cpu.iew.wb_sent 7354 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 7279 # cumulative count of insts written-back
system.cpu.iew.wb_producers 2832 # num instructions producing a value
system.cpu.iew.wb_consumers 4198 # num instructions consuming a value
2015-11-06 09:26:50 +01:00
system.cpu.iew.wb_rate 0.162083 # insts written-back per cycle
2015-09-15 15:14:09 +02:00
system.cpu.iew.wb_fanout 0.674607 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 4505 # The number of squashed insts skipped by commit
2014-10-20 23:48:19 +02:00
system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards
2015-09-15 15:14:09 +02:00
system.cpu.commit.branchMispredicts 362 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 13468 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.417508 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.246465 # Number of insts commited each cycle
2011-06-21 00:57:14 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2015-09-15 15:14:09 +02:00
system.cpu.commit.committed_per_cycle::0 11324 84.08% 84.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 857 6.36% 90.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 503 3.73% 94.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 247 1.83% 96.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 153 1.14% 97.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 168 1.25% 98.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 61 0.45% 98.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 39 0.29% 99.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 116 0.86% 100.00% # Number of insts commited each cycle
2011-06-21 00:57:14 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2015-09-15 15:14:09 +02:00
system.cpu.commit.committed_per_cycle::total 13468 # Number of insts commited each cycle
2014-10-20 23:48:19 +02:00
system.cpu.commit.committedInsts 5623 # Number of instructions committed
system.cpu.commit.committedOps 5623 # Number of ops (including micro ops) committed
2011-06-21 00:57:14 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2014-10-20 23:48:19 +02:00
system.cpu.commit.refs 2033 # Number of memory references committed
system.cpu.commit.loads 1132 # Number of loads committed
2011-06-21 00:57:14 +02:00
system.cpu.commit.membars 0 # Number of memory barriers committed
2014-10-20 23:48:19 +02:00
system.cpu.commit.branches 883 # Number of branches committed
2011-06-21 00:57:14 +02:00
system.cpu.commit.fp_insts 2 # Number of committed floating point instructions.
2014-10-20 23:48:19 +02:00
system.cpu.commit.int_insts 4942 # Number of committed integer instructions.
system.cpu.commit.function_calls 85 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 637 11.33% 11.33% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 2949 52.45% 63.77% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 2 0.04% 63.81% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.81% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 2 0.04% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.84% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 1132 20.13% 83.98% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 901 16.02% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2014-10-20 23:48:19 +02:00
system.cpu.commit.op_class_0::total 5623 # Class of committed instruction
2015-09-15 15:14:09 +02:00
system.cpu.commit.bw_lim_events 116 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 23467 # The number of ROB reads
system.cpu.rob.rob_writes 21056 # The number of ROB writes
system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself
2015-11-06 09:26:50 +01:00
system.cpu.idleCycles 30648 # Total number of cycles that the CPU has spent unscheduled due to idling
2014-10-20 23:48:19 +02:00
system.cpu.committedInsts 4986 # Number of Instructions Simulated
system.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated
2015-11-06 09:26:50 +01:00
system.cpu.cpi 9.007020 # CPI: Cycles Per Instruction
system.cpu.cpi_total 9.007020 # CPI: Total CPI of All Threads
system.cpu.ipc 0.111025 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.111025 # IPC: Total IPC of All Threads
2015-09-15 15:14:09 +02:00
system.cpu.int_regfile_reads 10418 # number of integer regfile reads
system.cpu.int_regfile_writes 5064 # number of integer regfile writes
2011-06-21 00:57:14 +02:00
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
2015-09-15 15:14:09 +02:00
system.cpu.misc_regfile_reads 158 # number of misc regfile reads
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.replacements 0 # number of replacements
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.tagsinuse 90.676519 # Cycle average of tags in use
2015-09-15 15:14:09 +02:00
system.cpu.dcache.tags.total_refs 2302 # Total number of references to valid blocks.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
2015-09-15 15:14:09 +02:00
system.cpu.dcache.tags.avg_refs 16.326241 # Average number of references to valid blocks.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 90.676519 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.022138 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.022138 # Average percentage of cache occupancy
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
2015-09-15 15:14:09 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id
2015-09-15 15:14:09 +02:00
system.cpu.dcache.tags.tag_accesses 5765 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 5765 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1746 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1746 # number of ReadReq hits
2015-03-02 11:04:20 +01:00
system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits
2015-09-15 15:14:09 +02:00
system.cpu.dcache.demand_hits::cpu.data 2302 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 2302 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 2302 # number of overall hits
system.cpu.dcache.overall_hits::total 2302 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 165 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 165 # number of ReadReq misses
2015-03-02 11:04:20 +01:00
system.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 345 # number of WriteReq misses
2015-09-15 15:14:09 +02:00
system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses
system.cpu.dcache.overall_misses::total 510 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11734000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11734000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 24014999 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 24014999 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 35748999 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 35748999 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 35748999 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 35748999 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1911 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1911 # number of ReadReq accesses(hits+misses)
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
2015-09-15 15:14:09 +02:00
system.cpu.dcache.demand_accesses::cpu.data 2812 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2812 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2812 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2812 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086342 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.086342 # miss rate for ReadReq accesses
2015-03-02 11:04:20 +01:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.181366 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.181366 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.181366 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.181366 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71115.151515 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 71115.151515 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69608.692754 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 69608.692754 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 70096.076471 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 70096.076471 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 70096.076471 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 70096.076471 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 587 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-09-15 15:14:09 +02:00
system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
2015-09-15 15:14:09 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.700000 # average number of cycles each access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2015-09-15 15:14:09 +02:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits
2015-03-02 11:04:20 +01:00
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 295 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 295 # number of WriteReq MSHR hits
2015-09-15 15:14:09 +02:00
system.cpu.dcache.demand_mshr_hits::cpu.data 369 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 369 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 369 # number of overall MSHR hits
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
2015-09-15 15:14:09 +02:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7594500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7594500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4083499 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4083499 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11677999 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11677999 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11677999 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11677999 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.047619 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.047619 # mshr miss rate for ReadReq accesses
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050142 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.050142 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050142 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.050142 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83456.043956 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83456.043956 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81669.980000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81669.980000 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82822.687943 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 82822.687943 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82822.687943 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 82822.687943 # average overall mshr miss latency
2014-12-23 15:31:20 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.replacements 17 # number of replacements
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.tagsinuse 156.413207 # Cycle average of tags in use
2015-09-15 15:14:09 +02:00
system.cpu.icache.tags.total_refs 1547 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 331 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 4.673716 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 156.413207 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.076374 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.076374 # Average percentage of cache occupancy
2015-09-15 15:14:09 +02:00
system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 4289 # Number of tag accesses
system.cpu.icache.tags.data_accesses 4289 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1547 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1547 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1547 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1547 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1547 # number of overall hits
system.cpu.icache.overall_hits::total 1547 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 432 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 432 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 432 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 432 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 432 # number of overall misses
system.cpu.icache.overall_misses::total 432 # number of overall misses
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_miss_latency::cpu.inst 32422500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 32422500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 32422500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 32422500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 32422500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 32422500 # number of overall miss cycles
2015-09-15 15:14:09 +02:00
system.cpu.icache.ReadReq_accesses::cpu.inst 1979 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1979 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1979 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1979 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1979 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1979 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.218292 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.218292 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.218292 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.218292 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.218292 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.218292 # miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75052.083333 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 75052.083333 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 75052.083333 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 75052.083333 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 75052.083333 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 75052.083333 # average overall miss latency
2014-10-20 23:48:19 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2011-06-21 00:57:14 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2014-10-20 23:48:19 +02:00
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
2011-06-21 00:57:14 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2014-10-20 23:48:19 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2011-06-21 00:57:14 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.icache.writebacks::writebacks 17 # number of writebacks
system.cpu.icache.writebacks::total 17 # number of writebacks
2015-09-15 15:14:09 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 101 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 101 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 101 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 101 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 101 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 331 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 331 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 331 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 331 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 331 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 331 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25904500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 25904500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25904500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 25904500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25904500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 25904500 # number of overall MSHR miss cycles
2015-09-15 15:14:09 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.167256 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.167256 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.167256 # mshr miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78261.329305 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78261.329305 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78261.329305 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 78261.329305 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78261.329305 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 78261.329305 # average overall mshr miss latency
2011-06-21 00:57:14 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.tagsinuse 215.857139 # Cycle average of tags in use
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks.
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.tags.sampled_refs 419 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.047733 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.337319 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 57.519820 # Average occupied blocks per requestor
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004832 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001755 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.006587 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012787 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.WritebackClean_hits::writebacks 17 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 17 # number of WritebackClean hits
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
system.cpu.l2cache.overall_hits::total 3 # number of overall hits
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 328 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 328 # number of ReadCleanReq misses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 91 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 91 # number of ReadSharedReq misses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_misses::cpu.inst 328 # number of demand (read+write) misses
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 328 # number of overall misses
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.overall_misses::total 469 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4007500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 4007500 # number of ReadExReq miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25375000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 25375000 # number of ReadCleanReq miss cycles
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7455000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 7455000 # number of ReadSharedReq miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.inst 25375000 # number of demand (read+write) miss cycles
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_miss_latency::cpu.data 11462500 # number of demand (read+write) miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_miss_latency::total 36837500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 25375000 # number of overall miss cycles
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.overall_miss_latency::cpu.data 11462500 # number of overall miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_miss_latency::total 36837500 # number of overall miss cycles
system.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses)
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses)
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 331 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 331 # number of ReadCleanReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 91 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 91 # number of ReadSharedReq accesses(hits+misses)
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_accesses::cpu.inst 331 # number of demand (read+write) accesses
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_accesses::total 472 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 331 # number of overall (read+write) accesses
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.overall_accesses::total 472 # number of overall (read+write) accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.990937 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.990937 # miss rate for ReadCleanReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990937 # miss rate for demand accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_miss_rate::total 0.993644 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990937 # miss rate for overall accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80150 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80150 # average ReadExReq miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77362.804878 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77362.804878 # average ReadCleanReq miss latency
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81923.076923 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81923.076923 # average ReadSharedReq miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77362.804878 # average overall miss latency
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81294.326241 # average overall miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_avg_miss_latency::total 78544.776119 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77362.804878 # average overall miss latency
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81294.326241 # average overall miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_avg_miss_latency::total 78544.776119 # average overall miss latency
2011-06-21 00:57:14 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2011-06-21 00:57:14 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 328 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 328 # number of ReadCleanReq MSHR misses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 91 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 91 # number of ReadSharedReq MSHR misses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 328 # number of demand (read+write) MSHR misses
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 328 # number of overall MSHR misses
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3507500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3507500 # number of ReadExReq MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22095000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22095000 # number of ReadCleanReq MSHR miss cycles
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6545000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6545000 # number of ReadSharedReq MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22095000 # number of demand (read+write) MSHR miss cycles
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10052500 # number of demand (read+write) MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::total 32147500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22095000 # number of overall MSHR miss cycles
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10052500 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::total 32147500 # number of overall MSHR miss cycles
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990937 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.990937 # mshr miss rate for ReadCleanReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990937 # mshr miss rate for demand accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::total 0.993644 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990937 # mshr miss rate for overall accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70150 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70150 # average ReadExReq mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67362.804878 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67362.804878 # average ReadCleanReq mshr miss latency
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71923.076923 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71923.076923 # average ReadSharedReq mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67362.804878 # average overall mshr miss latency
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68544.776119 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67362.804878 # average overall mshr miss latency
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68544.776119 # average overall mshr miss latency
2011-06-21 00:57:14 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.trans_dist::ReadCleanReq 331 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.trans_dist::ReadSharedReq 91 # Transaction distribution
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 679 # Packet count per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes)
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.pkt_count::total 961 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22272 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.pkt_size::total 31296 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::samples 472 # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::0 472 100.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::total 472 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 261500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 496500 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
2015-09-15 15:14:09 +02:00
system.membus.trans_dist::ReadResp 419 # Transaction distribution
2014-12-23 15:31:20 +01:00
system.membus.trans_dist::ReadExReq 50 # Transaction distribution
system.membus.trans_dist::ReadExResp 50 # Transaction distribution
2015-09-15 15:14:09 +02:00
system.membus.trans_dist::ReadSharedReq 419 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 938 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 938 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30016 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
2015-09-15 15:14:09 +02:00
system.membus.snoop_fanout::samples 469 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-09-15 15:14:09 +02:00
system.membus.snoop_fanout::0 469 100.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2015-09-15 15:14:09 +02:00
system.membus.snoop_fanout::total 469 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.membus.reqLayer0.occupancy 581500 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer0.utilization 2.6 # Layer utilization (%)
2015-09-15 15:14:09 +02:00
system.membus.respLayer1.occupancy 2493500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 11.1 # Layer utilization (%)
2009-04-18 16:42:29 +02:00
---------- End Simulation Statistics ----------
