2007-02-01 00:47:23 +01:00
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---------- Begin Simulation Statistics ----------
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2014-09-03 13:42:59 +02:00
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sim_seconds 0.069652 # Number of seconds simulated
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sim_ticks 69651704000 # Number of ticks simulated
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final_tick 69651704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2007-02-01 00:47:23 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2014-12-23 15:31:20 +01:00
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host_inst_rate 253977 # Simulator instruction rate (inst/s)
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host_op_rate 253977 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 47101012 # Simulator tick rate (ticks/s)
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host_mem_usage 302288 # Number of bytes of host memory used
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host_seconds 1478.77 # Real time elapsed on the host
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2012-02-13 19:30:30 +01:00
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sim_insts 375574808 # Number of instructions simulated
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sim_ops 375574808 # Number of ops (including micro ops) simulated
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2014-01-24 22:29:33 +01:00
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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2014-09-03 13:42:59 +02:00
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system.physmem.bytes_read::cpu.inst 221568 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 255744 # Number of bytes read from this memory
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system.physmem.bytes_read::total 477312 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 221568 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 221568 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 3462 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 3996 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 7458 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 3181085 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 3671755 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 6852840 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 3181085 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 3181085 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 3181085 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 3671755 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 6852840 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 7458 # Number of read requests accepted
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2013-11-01 16:56:34 +01:00
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system.physmem.writeReqs 0 # Number of write requests accepted
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2014-09-03 13:42:59 +02:00
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system.physmem.readBursts 7458 # Number of DRAM read bursts, including those serviced by the write queue
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2013-11-01 16:56:34 +01:00
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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2014-09-03 13:42:59 +02:00
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system.physmem.bytesReadDRAM 477312 # Total number of bytes read from DRAM
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2013-11-01 16:56:34 +01:00
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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2014-09-03 13:42:59 +02:00
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system.physmem.bytesReadSys 477312 # Total read bytes from the system interface side
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2013-11-01 16:56:34 +01:00
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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2014-09-03 13:42:59 +02:00
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system.physmem.perBankRdBursts::0 528 # Per bank write bursts
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system.physmem.perBankRdBursts::1 655 # Per bank write bursts
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system.physmem.perBankRdBursts::2 455 # Per bank write bursts
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2014-06-22 23:33:09 +02:00
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system.physmem.perBankRdBursts::3 602 # Per bank write bursts
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2014-09-03 13:42:59 +02:00
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system.physmem.perBankRdBursts::4 446 # Per bank write bursts
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system.physmem.perBankRdBursts::5 454 # Per bank write bursts
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2014-06-22 23:33:09 +02:00
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system.physmem.perBankRdBursts::6 515 # Per bank write bursts
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2013-11-01 16:56:34 +01:00
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system.physmem.perBankRdBursts::7 524 # Per bank write bursts
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2014-09-03 13:42:59 +02:00
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system.physmem.perBankRdBursts::8 439 # Per bank write bursts
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system.physmem.perBankRdBursts::9 406 # Per bank write bursts
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system.physmem.perBankRdBursts::10 340 # Per bank write bursts
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system.physmem.perBankRdBursts::11 305 # Per bank write bursts
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2013-11-01 16:56:34 +01:00
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system.physmem.perBankRdBursts::12 414 # Per bank write bursts
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2014-09-03 13:42:59 +02:00
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system.physmem.perBankRdBursts::13 542 # Per bank write bursts
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system.physmem.perBankRdBursts::14 454 # Per bank write bursts
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system.physmem.perBankRdBursts::15 379 # Per bank write bursts
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2013-11-01 16:56:34 +01:00
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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2014-09-03 13:42:59 +02:00
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system.physmem.totGap 69651614500 # Total gap between requests
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2013-11-01 16:56:34 +01:00
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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2014-09-03 13:42:59 +02:00
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system.physmem.readPktSize::6 7458 # Read request sizes (log2)
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2013-11-01 16:56:34 +01:00
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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2014-12-23 15:31:20 +01:00
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system.physmem.rdQLenPdf::0 4228 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 1957 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 915 # What read queue length does an incoming req see
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2014-09-20 23:18:53 +02:00
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system.physmem.rdQLenPdf::3 293 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 63 # What read queue length does an incoming req see
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2014-05-10 00:58:50 +02:00
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system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
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2013-05-30 18:54:18 +02:00
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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2012-10-30 14:35:32 +01:00
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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2012-10-25 19:14:42 +02:00
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
2014-03-23 16:12:19 +01:00
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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2014-09-20 23:18:53 +02:00
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system.physmem.bytesPerActivate::samples 1353 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 350.509978 # Bytes accessed per row activation
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2014-12-23 15:31:20 +01:00
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system.physmem.bytesPerActivate::gmean 208.904608 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 348.764111 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 423 31.26% 31.26% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 330 24.39% 55.65% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 152 11.23% 66.89% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 83 6.13% 73.02% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 55 4.07% 77.09% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 43 3.18% 80.27% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 38 2.81% 83.07% # Bytes accessed per row activation
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2014-09-20 23:18:53 +02:00
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|
|
system.physmem.bytesPerActivate::896-1023 25 1.85% 84.92% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::1024-1151 204 15.08% 100.00% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::total 1353 # Bytes accessed per row activation
|
2014-12-23 15:31:20 +01:00
|
|
|
system.physmem.totQLat 67034750 # Total ticks spent queuing
|
|
|
|
|
system.physmem.totMemAccLat 206872250 # Total ticks spent from burst creation until serviced by the DRAM
|
2014-09-03 13:42:59 +02:00
|
|
|
system.physmem.totBusLat 37290000 # Total ticks spent in databus transfers
|
2014-12-23 15:31:20 +01:00
|
|
|
system.physmem.avgQLat 8988.30 # Average queueing delay per DRAM burst
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
2014-12-23 15:31:20 +01:00
|
|
|
system.physmem.avgMemAccLat 27738.30 # Average memory access latency per DRAM burst
|
2014-09-03 13:42:59 +02:00
|
|
|
system.physmem.avgRdBW 6.85 # Average DRAM read bandwidth in MiByte/s
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
2014-09-03 13:42:59 +02:00
|
|
|
system.physmem.avgRdBWSys 6.85 # Average system read bandwidth in MiByte/s
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
|
|
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
2013-01-31 13:49:16 +01:00
|
|
|
system.physmem.busUtil 0.05 # Data bus utilization in percentage
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads
|
|
|
|
|
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
2014-09-03 13:42:59 +02:00
|
|
|
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.readRowHits 6096 # Number of row buffer hits during reads
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.readRowHitRate 81.74 # Row buffer hit rate for reads
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
2014-09-03 13:42:59 +02:00
|
|
|
system.physmem.avgGap 9339181.35 # Average gap between requests
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.pageHitRate 81.74 # Row buffer hit rate, read and write combined
|
2014-12-23 15:31:20 +01:00
|
|
|
system.physmem_0.actEnergy 5843880 # Energy for activate commands per rank (pJ)
|
|
|
|
|
system.physmem_0.preEnergy 3188625 # Energy for precharge commands per rank (pJ)
|
|
|
|
|
system.physmem_0.readEnergy 32385600 # Energy for read commands per rank (pJ)
|
|
|
|
|
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
|
|
|
|
system.physmem_0.refreshEnergy 4549069200 # Energy for refresh commands per rank (pJ)
|
|
|
|
|
system.physmem_0.actBackEnergy 2090226195 # Energy for active background per rank (pJ)
|
|
|
|
|
system.physmem_0.preBackEnergy 39955428000 # Energy for precharge background per rank (pJ)
|
|
|
|
|
system.physmem_0.totalEnergy 46636141500 # Total energy per rank (pJ)
|
|
|
|
|
system.physmem_0.averagePower 669.595153 # Core power per rank (mW)
|
|
|
|
|
system.physmem_0.memoryStateTime::IDLE 66468117000 # Time in different power states
|
|
|
|
|
system.physmem_0.memoryStateTime::REF 2325700000 # Time in different power states
|
|
|
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
|
|
|
system.physmem_0.memoryStateTime::ACT 855864000 # Time in different power states
|
|
|
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
|
|
|
system.physmem_1.actEnergy 4362120 # Energy for activate commands per rank (pJ)
|
|
|
|
|
system.physmem_1.preEnergy 2380125 # Energy for precharge commands per rank (pJ)
|
|
|
|
|
system.physmem_1.readEnergy 25373400 # Energy for read commands per rank (pJ)
|
|
|
|
|
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
|
|
|
|
system.physmem_1.refreshEnergy 4549069200 # Energy for refresh commands per rank (pJ)
|
|
|
|
|
system.physmem_1.actBackEnergy 1978191270 # Energy for active background per rank (pJ)
|
|
|
|
|
system.physmem_1.preBackEnergy 40053704250 # Energy for precharge background per rank (pJ)
|
|
|
|
|
system.physmem_1.totalEnergy 46613080365 # Total energy per rank (pJ)
|
|
|
|
|
system.physmem_1.averagePower 669.264045 # Core power per rank (mW)
|
|
|
|
|
system.physmem_1.memoryStateTime::IDLE 66630949750 # Time in different power states
|
|
|
|
|
system.physmem_1.memoryStateTime::REF 2325700000 # Time in different power states
|
|
|
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
|
|
|
system.physmem_1.memoryStateTime::ACT 691630250 # Time in different power states
|
|
|
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
|
|
|
system.cpu.branchPred.lookups 51167471 # Number of BP lookups
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.branchPred.condPredicted 29641015 # Number of conditional branches predicted
|
|
|
|
|
system.cpu.branchPred.condIncorrect 1213095 # Number of conditional branches incorrect
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.branchPred.BTBLookups 25804996 # Number of BTB lookups
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.branchPred.BTBHits 23600999 # Number of BTB hits
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.branchPred.BTBHitPct 91.459030 # BTB Hit Percentage
|
|
|
|
|
system.cpu.branchPred.usedRAS 9351091 # Number of times the RAS was used to get a target.
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.branchPred.RASInCorrect 307 # Number of incorrect RAS predictions.
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
|
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
|
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.dtb.read_hits 103696202 # DTB read hits
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.dtb.read_misses 91462 # DTB read misses
|
|
|
|
|
system.cpu.dtb.read_acv 49407 # DTB read access violations
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.dtb.read_accesses 103787664 # DTB read accesses
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.dtb.write_hits 79414480 # DTB write hits
|
|
|
|
|
system.cpu.dtb.write_misses 1579 # DTB write misses
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dtb.write_acv 2 # DTB write access violations
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.dtb.write_accesses 79416059 # DTB write accesses
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.dtb.data_hits 183110682 # DTB hits
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.dtb.data_misses 93041 # DTB misses
|
|
|
|
|
system.cpu.dtb.data_acv 49409 # DTB access violations
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.dtb.data_accesses 183203723 # DTB accesses
|
|
|
|
|
system.cpu.itb.fetch_hits 51277820 # ITB hits
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.itb.fetch_misses 422 # ITB misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.itb.fetch_accesses 51278242 # ITB accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
|
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.workload.num_syscalls 215 # Number of system calls
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.numCycles 139303411 # number of cpu cycles simulated
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.fetch.icacheStallCycles 52063926 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.Insts 457094521 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.Branches 51167471 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.predictedBranches 32952090 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.Cycles 85692281 # Number of cycles fetch has run and was not squashing or blocked
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.fetch.SquashCycles 2532764 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb
|
|
|
|
|
system.cpu.fetch.MiscStallCycles 174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
|
|
|
system.cpu.fetch.PendingTrapStallCycles 13783 # Number of stall cycles due to pending traps
|
|
|
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.fetch.CacheLines 51277820 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 545278 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.rateDist::samples 139036576 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::mean 3.287585 # Number of instructions fetched each cycle (Total)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.fetch.rateDist::stdev 3.344928 # Number of instructions fetched each cycle (Total)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.fetch.rateDist::0 58307337 41.94% 41.94% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::1 4519216 3.25% 45.19% # Number of instructions fetched each cycle (Total)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.fetch.rateDist::2 7280822 5.24% 50.42% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::3 5545601 3.99% 54.41% # Number of instructions fetched each cycle (Total)
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.fetch.rateDist::4 11970286 8.61% 63.02% # Number of instructions fetched each cycle (Total)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.fetch.rateDist::5 8019991 5.77% 68.79% # Number of instructions fetched each cycle (Total)
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.fetch.rateDist::6 5933032 4.27% 73.06% # Number of instructions fetched each cycle (Total)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.fetch.rateDist::7 1884761 1.36% 74.41% # Number of instructions fetched each cycle (Total)
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.fetch.rateDist::8 35575530 25.59% 100.00% # Number of instructions fetched each cycle (Total)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.fetch.rateDist::total 139036576 # Number of instructions fetched each cycle (Total)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.fetch.branchRate 0.367310 # Number of branch fetches per cycle
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.fetch.rate 3.281287 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu.decode.IdleCycles 45112383 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.BlockedCycles 16348146 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.RunCycles 71787003 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.UnblockCycles 4526860 # Number of cycles decode is unblocking
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.decode.SquashCycles 1262184 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.BranchResolved 9563244 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu.decode.BranchMispred 4245 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu.decode.DecodedInsts 451283163 # Number of instructions handled by decode
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.decode.SquashedInsts 14196 # Number of squashed instructions handled by decode
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.rename.SquashCycles 1262184 # Number of cycles rename is squashing
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.rename.IdleCycles 47011024 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.BlockCycles 5663526 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.serializeStallCycles 519113 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RunCycles 74309218 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.UnblockCycles 10271511 # Number of cycles rename is unblocking
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.rename.RenamedInsts 447721649 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.ROBFullEvents 439815 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu.rename.IQFullEvents 2540100 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.LQFullEvents 2926498 # Number of times rename has blocked due to LQ full
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.rename.SQFullEvents 3600527 # Number of times rename has blocked due to SQ full
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.rename.RenamedOperands 292278306 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RenameLookups 589607782 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.int_rename_lookups 419965282 # Number of integer rename lookups
|
|
|
|
|
system.cpu.rename.fp_rename_lookups 169642499 # Number of floating rename lookups
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.rename.UndoneMaps 32745977 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.serializingInsts 37893 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.tempSerializingInsts 316 # count of temporary serializing insts renamed
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.rename.skidInsts 16173797 # count of insts added to the skid buffer
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.memDep0.insertedLoads 106306370 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 81667386 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.conflictingLoads 12470725 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 9729569 # Number of conflicting stores.
|
|
|
|
|
system.cpu.iq.iqInstsAdded 414594685 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 306 # Number of non-speculative instructions added to the IQ
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.iq.iqInstsIssued 406915918 # Number of instructions issued
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.iq.iqSquashedInstsIssued 484036 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 38878487 # Number of squashed instructions iterated over during squash; mainly for profiling
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 18208107 # Number of squashed operands that are examined and possibly removed from graph
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 91 # Number of squashed non-spec instructions that were removed
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::samples 139036576 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::mean 2.926683 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::stdev 2.221929 # Number of insts issued each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::0 23891494 17.18% 17.18% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::1 19616678 14.11% 31.29% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::2 22677483 16.31% 47.60% # Number of insts issued each cycle
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::3 18900240 13.59% 61.20% # Number of insts issued each cycle
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::4 19609416 14.10% 75.30% # Number of insts issued each cycle
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::5 14153871 10.18% 85.48% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::6 9626410 6.92% 92.40% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::7 6209797 4.47% 96.87% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::8 4351187 3.13% 100.00% # Number of insts issued each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::total 139036576 # Number of insts issued each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.iq.fu_full::IntAlu 258477 1.29% 1.29% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntMult 1 0.00% 1.29% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.29% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatAdd 145250 0.73% 2.02% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCmp 90218 0.45% 2.47% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCvt 2947 0.01% 2.49% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatMult 3497968 17.50% 19.99% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatDiv 1676632 8.39% 28.38% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.38% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.38% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.38% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.38% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.38% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.38% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.38% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 28.38% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.38% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 28.38% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.38% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.38% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.38% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.38% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.38% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.38% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.38% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.38% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.38% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.38% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.38% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemRead 9338598 46.73% 75.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemWrite 4976149 24.90% 100.00% # attempts to use FU when none available
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.iq.FU_type_0::IntAlu 153207490 37.65% 37.66% # Type of FU issued
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.iq.FU_type_0::IntMult 2128182 0.52% 38.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 37392506 9.19% 47.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 7524499 1.85% 49.22% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 2804822 0.69% 49.91% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 16757586 4.12% 54.03% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 1601657 0.39% 54.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.42% # Type of FU issued
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.iq.FU_type_0::MemRead 105367868 25.89% 80.32% # Type of FU issued
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.iq.FU_type_0::MemWrite 80097727 19.68% 100.00% # Type of FU issued
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.iq.FU_type_0::total 406915918 # Type of FU issued
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.iq.rate 2.921076 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 19986240 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.049116 # FU busy rate (busy events/executed inst)
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.iq.int_inst_queue_reads 625897049 # Number of integer instruction queue reads
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.iq.int_inst_queue_writes 265989715 # Number of integer instruction queue writes
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 237228631 # Number of integer instruction queue wakeup accesses
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.iq.fp_inst_queue_reads 347441639 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 187559752 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 163339265 # Number of floating instruction queue wakeup accesses
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.iq.int_alu_accesses 246150914 # Number of integer alu accesses
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.iq.fp_alu_accesses 180717663 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 19936358 # Number of loads that had data forwarded from stores
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 11551883 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 163597 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 76334 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 8146657 # Number of stores squashed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 381699 # Number of loads that were rescheduled
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 4488 # Number of times an access to memory failed due to the cache being blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 1262184 # Number of cycles IEW is squashing
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.iew.iewBlockCycles 4471526 # Number of cycles IEW is blocking
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.iew.iewUnblockCycles 139208 # Number of cycles IEW is unblocking
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.iew.iewDispatchedInsts 439574480 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 145285 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 106306370 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 81667386 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 306 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 6690 # Number of times the IQ has become full, causing a stall
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.iew.iewLSQFullEvents 131691 # Number of times the LSQ has become full, causing a stall
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.iew.memOrderViolationEvents 76334 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 976027 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 412585 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 1388612 # Number of branch mispredicts detected at execute
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.iew.iewExecutedInsts 403157736 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 103837102 # Number of load instructions executed
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.iew.iewExecSquashedInsts 3758182 # Number of squashed instructions skipped in execute
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.iew.exec_nop 24979489 # number of nop insts executed
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.iew.exec_refs 183253198 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 46959989 # Number of branches executed
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.iew.exec_stores 79416096 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 2.894098 # Inst execution rate
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.iew.wb_sent 401401507 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 400567896 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 198000452 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 283955606 # num instructions consuming a value
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.iew.wb_rate 2.875507 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.697294 # average fanout of values written-back
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 40912072 # The number of squashed insts skipped by commit
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.commit.branchMispredicts 1208897 # The number of times a branch was mispredicted
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::samples 133310723 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 2.990491 # Number of insts commited each cycle
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::stdev 3.213946 # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::0 48555712 36.42% 36.42% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 18055923 13.54% 49.97% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 9630862 7.22% 57.19% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 8737322 6.55% 63.75% # Number of insts commited each cycle
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::4 6426217 4.82% 68.57% # Number of insts commited each cycle
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::5 4404759 3.30% 71.87% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 4988493 3.74% 75.61% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 2616131 1.96% 77.57% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 29895304 22.43% 100.00% # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::total 133310723 # Number of insts commited each cycle
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.committedInsts 398664583 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.refs 168275216 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 94754487 # Number of loads committed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.branches 44587533 # Number of branches committed
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions.
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.int_insts 316365839 # Number of committed integer instructions.
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.function_calls 8007752 # Number of function calls committed.
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.commit.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.commit.op_class_0::IntAlu 141652545 35.53% 41.33% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 41.86% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatAdd 35620060 8.93% 50.80% # Class of committed instruction
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.commit.op_class_0::FloatCmp 7072549 1.77% 52.57% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatCvt 2735231 0.69% 53.26% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatMult 16498021 4.14% 57.40% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatDiv 1563283 0.39% 57.79% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 57.79% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 57.79% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 57.79% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 57.79% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 57.79% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 57.79% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 57.79% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 57.79% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 57.79% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 57.79% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 57.79% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 57.79% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 57.79% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 57.79% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 57.79% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 57.79% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 57.79% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 57.79% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 57.79% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.79% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.79% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::MemRead 94754487 23.77% 81.56% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::MemWrite 73520729 18.44% 100.00% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.commit.bw_lim_events 29895304 # number cycles where commit BW limit reached
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.rob.rob_reads 542989097 # The number of ROB reads
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.rob.rob_writes 884890973 # The number of ROB writes
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.timesIdled 3476 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 266835 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.committedInsts 375574808 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.cpi 0.370907 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.370907 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 2.696092 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 2.696092 # IPC: Total IPC of All Threads
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.int_regfile_reads 403240146 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 171897288 # number of integer regfile writes
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.fp_regfile_reads 157938395 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 105579710 # number of floating regfile writes
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.dcache.tags.replacements 798 # number of replacements
|
|
|
|
|
system.cpu.dcache.tags.tagsinuse 3297.113166 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.tags.total_refs 156873476 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.sampled_refs 4201 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.avg_refs 37341.936682 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 3297.113166 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.804959 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.tags.occ_percent::total 0.804959 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 3403 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.830811 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.dcache.tags.tag_accesses 313794583 # Number of tag accesses
|
|
|
|
|
system.cpu.dcache.tags.data_accesses 313794583 # Number of data accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 83372633 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 83372633 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 73500836 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 73500836 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 7 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::total 7 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::cpu.data 156873469 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 156873469 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 156873469 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 156873469 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1822 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 1822 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 19893 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 19893 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses::cpu.data 21715 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 21715 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 21715 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 21715 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 114608500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 114608500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1125293584 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 1125293584 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 1239902084 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 1239902084 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 1239902084 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 1239902084 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 83374455 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 83374455 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 156895184 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 156895184 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 156895184 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 156895184 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000138 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.000138 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000138 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.000138 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62902.579583 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 62902.579583 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56567.314332 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 56567.314332 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 57098.875616 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::total 57098.875616 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 57098.875616 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::total 57098.875616 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 46396 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 61 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 946 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.044397 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 61 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.dcache.writebacks::writebacks 674 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 674 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 824 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 824 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16690 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 16690 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 17514 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 17514 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 17514 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 17514 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 998 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 998 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3203 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 3203 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 4201 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 4201 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 4201 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 4201 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67693000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 67693000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 235962750 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 235962750 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 303655750 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 303655750 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 303655750 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 303655750 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67828.657315 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67828.657315 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73669.294411 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73669.294411 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72281.778148 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 72281.778148 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72281.778148 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 72281.778148 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.icache.tags.replacements 2164 # number of replacements
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.icache.tags.tagsinuse 1832.364532 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.tags.total_refs 51272141 # Total number of references to valid blocks.
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.icache.tags.sampled_refs 4091 # Sample count of references to valid blocks.
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.icache.tags.avg_refs 12532.911513 # Average number of references to valid blocks.
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1832.364532 # Average occupied blocks per requestor
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.894709 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.tags.occ_percent::total 0.894709 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1927 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1343 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.940918 # Percentage of cache occupancy per task id
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.icache.tags.tag_accesses 102559731 # Number of tag accesses
|
|
|
|
|
system.cpu.icache.tags.data_accesses 102559731 # Number of data accesses
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 51272141 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 51272141 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 51272141 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 51272141 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 51272141 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 51272141 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 5679 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 5679 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 5679 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 5679 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 5679 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 5679 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 341090499 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 341090499 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 341090499 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::total 341090499 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 341090499 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::total 341090499 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 51277820 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 51277820 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 51277820 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 51277820 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 51277820 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 51277820 # number of overall (read+write) accesses
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000111 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000111 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000111 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total 0.000111 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000111 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total 0.000111 # miss rate for overall accesses
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60061.718436 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 60061.718436 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 60061.718436 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total 60061.718436 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 60061.718436 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total 60061.718436 # average overall miss latency
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 528 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 58.666667 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1588 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits::total 1588 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 1588 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::total 1588 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 1588 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::total 1588 # number of overall MSHR hits
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4091 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 4091 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 4091 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 4091 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 4091 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 4091 # number of overall MSHR misses
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 250258250 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 250258250 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 250258250 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 250258250 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250258250 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 250258250 # number of overall MSHR miss cycles
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61172.879492 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61172.879492 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61172.879492 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 61172.879492 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61172.879492 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 61172.879492 # average overall mshr miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.l2cache.tags.tagsinuse 4021.632512 # Cycle average of tags in use
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.tags.total_refs 866 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.sampled_refs 4864 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.avg_refs 0.178043 # Average number of references to valid blocks.
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 371.133834 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2983.663344 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 666.835334 # Average occupied blocks per requestor
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.011326 # Average percentage of cache occupancy
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.091054 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.020350 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::total 0.122730 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4864 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 535 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4046 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148438 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.l2cache.tags.tag_accesses 79795 # Number of tag accesses
|
|
|
|
|
system.cpu.l2cache.tags.data_accesses 79795 # Number of data accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 629 # number of ReadReq hits
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 132 # number of ReadReq hits
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.ReadReq_hits::total 761 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 674 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 674 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 73 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 73 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 629 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 205 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 834 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 629 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 205 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 834 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 3462 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 866 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 4328 # number of ReadReq misses
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 3130 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 3130 # number of ReadExReq misses
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3462 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 3996 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 7458 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3462 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 3996 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 7458 # number of overall misses
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 239866750 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 65282000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 305148750 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 231929750 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 231929750 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 239866750 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 297211750 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 537078500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 239866750 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 297211750 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 537078500 # number of overall miss cycles
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 4091 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 998 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 5089 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 674 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 674 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3203 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 3203 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 4091 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 4201 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 8292 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 4091 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 4201 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 8292 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.846248 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.867735 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.850462 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.977209 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.977209 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.846248 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.951202 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::total 0.899421 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.846248 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.951202 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::total 0.899421 # miss rate for overall accesses
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69285.600809 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75383.371824 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70505.718577 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74098.961661 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74098.961661 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69285.600809 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74377.314815 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 72013.743631 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69285.600809 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74377.314815 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 72013.743631 # average overall miss latency
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3462 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 866 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 4328 # number of ReadReq MSHR misses
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3130 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 3130 # number of ReadExReq MSHR misses
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3462 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 3996 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 7458 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3462 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 3996 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 7458 # number of overall MSHR misses
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195982250 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54610500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 250592750 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 193350250 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 193350250 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195982250 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 247960750 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 443943000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195982250 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 247960750 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 443943000 # number of overall MSHR miss cycles
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867735 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.850462 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.977209 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.977209 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.951202 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.899421 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.951202 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.899421 # mshr miss rate for overall accesses
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56609.546505 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63060.623557 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57900.358133 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61773.242812 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61773.242812 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56609.546505 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62052.239740 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59525.744167 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56609.546505 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62052.239740 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59525.744167 # average overall mshr miss latency
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2014-12-23 15:31:20 +01:00
|
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 5089 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 5089 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::Writeback 674 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 3203 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 3203 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8182 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9076 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count::total 17258 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261824 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312000 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size::total 573824 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::samples 8966 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::1 8966 100.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::total 8966 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 5157000 # Layer occupancy (ticks)
|
|
|
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.cpu.toL2Bus.respLayer0.occupancy 6787250 # Layer occupancy (ticks)
|
|
|
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.cpu.toL2Bus.respLayer1.occupancy 6700250 # Layer occupancy (ticks)
|
|
|
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.membus.trans_dist::ReadReq 4328 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadResp 4328 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadExReq 3130 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadExResp 3130 # Transaction distribution
|
|
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14916 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count::total 14916 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477312 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size::total 477312 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
|
|
|
system.membus.snoop_fanout::samples 7458 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::0 7458 100.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::total 7458 # Request fanout histogram
|
|
|
|
|
system.membus.reqLayer0.occupancy 9422500 # Layer occupancy (ticks)
|
|
|
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.membus.respLayer1.occupancy 69712000 # Layer occupancy (ticks)
|
|
|
|
|
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
2007-02-01 00:47:23 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
