Create reference outputs for this regression.
--HG-- extra : convert_revision : 91e0144fef3f66d413417ad0318f43f752494e3c
This commit is contained in:
Gabe Black
parent
36a1912bf0
commit
559460e33a
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@ -0,0 +1,428 @@
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[root]
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type=Root
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||||
children=system
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||||
checkpoint=
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||||
clock=1000000000000
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||||
max_tick=0
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||||
output_file=cout
|
||||
progress_interval=0
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||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
print_data=true
|
||||
print_effaddr=true
|
||||
print_fetchseq=false
|
||||
print_iregs=false
|
||||
print_opclass=true
|
||||
print_thread=true
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||||
speculative=true
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||||
trace_system=client
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||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
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||||
dir=cpt.%012d
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||||
period=0
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||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
|
||||
ignore_events=
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mysql_db=
|
||||
mysql_host=
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mysql_password=
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mysql_user=
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project_name=test
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simulation_name=test
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simulation_sample=0
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text_compat=true
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text_file=m5stats.txt
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[system]
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type=System
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children=cpu membus physmem
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mem_mode=atomic
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physmem=system.physmem
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||||
|
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[system.cpu]
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type=DerivO3CPU
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||||
children=dcache fuPool icache l2cache toL2Bus workload
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BTBEntries=4096
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||||
BTBTagSize=16
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||||
LFSTSize=1024
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||||
LQEntries=32
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||||
RASSize=16
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||||
SQEntries=32
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||||
SSITSize=1024
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||||
activity=0
|
||||
backComSize=5
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||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
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||||
clock=1
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
decodeToFetchDelay=1
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||||
decodeToRenameDelay=1
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||||
decodeWidth=8
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||||
defer_registration=false
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||||
dispatchWidth=8
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||||
fetchToDecodeDelay=1
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||||
fetchTrapLatency=1
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fetchWidth=8
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forwardComSize=5
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fuPool=system.cpu.fuPool
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function_trace=false
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function_trace_start=0
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||||
globalCtrBits=2
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||||
globalHistoryBits=13
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||||
globalPredictorSize=8192
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||||
iewToCommitDelay=1
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||||
iewToDecodeDelay=1
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||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
instShiftAmt=2
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||||
issueToExecuteDelay=1
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||||
issueWidth=8
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||||
localCtrBits=2
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||||
localHistoryBits=11
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||||
localHistoryTableSize=2048
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||||
localPredictorSize=2048
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||||
max_insts_all_threads=0
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||||
max_insts_any_thread=0
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||||
max_loads_all_threads=0
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||||
max_loads_any_thread=0
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||||
numIQEntries=64
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||||
numPhysFloatRegs=256
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||||
numPhysIntRegs=256
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||||
numROBEntries=192
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||||
numRobs=1
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||||
numThreads=1
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||||
phase=0
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||||
predType=tournament
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||||
progress_interval=0
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||||
renameToDecodeDelay=1
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||||
renameToFetchDelay=1
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||||
renameToIEWDelay=2
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||||
renameToROBDelay=1
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||||
renameWidth=8
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squashWidth=8
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system=system
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trapLatency=13
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wbDepth=1
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wbWidth=8
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workload=system.cpu.workload
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dcache_port=system.cpu.dcache.cpu_side
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icache_port=system.cpu.icache.cpu_side
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[system.cpu.dcache]
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type=BaseCache
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adaptive_compression=false
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assoc=2
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block_size=64
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compressed_bus=false
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||||
compression_latency=0
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||||
hash_delay=1
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||||
hit_latency=1
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||||
latency=1
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||||
lifo=false
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||||
max_miss_count=0
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||||
mshrs=10
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||||
prefetch_access=false
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||||
prefetch_cache_check_push=true
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||||
prefetch_data_accesses_only=false
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prefetch_degree=1
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||||
prefetch_latency=10
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prefetch_miss=false
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||||
prefetch_past_page=false
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||||
prefetch_policy=none
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||||
prefetch_serial_squash=false
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||||
prefetch_use_cpu_id=true
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||||
prefetcher_size=100
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||||
prioritizeRequests=false
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||||
protocol=Null
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||||
repl=Null
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||||
size=262144
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||||
split=false
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||||
split_size=0
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||||
store_compressed=false
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||||
subblock_size=0
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||||
tgts_per_mshr=5
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trace_addr=0
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||||
two_queue=false
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write_buffers=8
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cpu_side=system.cpu.dcache_port
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mem_side=system.cpu.toL2Bus.port[1]
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[system.cpu.fuPool]
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type=FUPool
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children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
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FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
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[system.cpu.fuPool.FUList0]
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type=FUDesc
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children=opList0
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count=6
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opList=system.cpu.fuPool.FUList0.opList0
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[system.cpu.fuPool.FUList0.opList0]
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type=OpDesc
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issueLat=1
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opClass=IntAlu
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opLat=1
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[system.cpu.fuPool.FUList1]
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type=FUDesc
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children=opList0 opList1
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count=2
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opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
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[system.cpu.fuPool.FUList1.opList0]
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type=OpDesc
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issueLat=1
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opClass=IntMult
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opLat=3
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[system.cpu.fuPool.FUList1.opList1]
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type=OpDesc
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issueLat=19
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opClass=IntDiv
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opLat=20
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[system.cpu.fuPool.FUList2]
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type=FUDesc
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children=opList0 opList1 opList2
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count=4
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opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
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[system.cpu.fuPool.FUList2.opList0]
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type=OpDesc
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||||
issueLat=1
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||||
opClass=FloatAdd
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opLat=2
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[system.cpu.fuPool.FUList2.opList1]
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type=OpDesc
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issueLat=1
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opClass=FloatCmp
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opLat=2
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[system.cpu.fuPool.FUList2.opList2]
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type=OpDesc
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issueLat=1
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opClass=FloatCvt
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opLat=2
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[system.cpu.fuPool.FUList3]
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type=FUDesc
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children=opList0 opList1 opList2
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count=2
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opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
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[system.cpu.fuPool.FUList3.opList0]
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type=OpDesc
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||||
issueLat=1
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||||
opClass=FloatMult
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opLat=4
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||||
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[system.cpu.fuPool.FUList3.opList1]
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type=OpDesc
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||||
issueLat=12
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||||
opClass=FloatDiv
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opLat=12
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[system.cpu.fuPool.FUList3.opList2]
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type=OpDesc
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issueLat=24
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opClass=FloatSqrt
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opLat=24
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[system.cpu.fuPool.FUList4]
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type=FUDesc
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children=opList0
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count=0
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opList=system.cpu.fuPool.FUList4.opList0
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[system.cpu.fuPool.FUList4.opList0]
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type=OpDesc
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issueLat=1
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opClass=MemRead
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opLat=1
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[system.cpu.fuPool.FUList5]
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type=FUDesc
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children=opList0
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count=0
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opList=system.cpu.fuPool.FUList5.opList0
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[system.cpu.fuPool.FUList5.opList0]
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type=OpDesc
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issueLat=1
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||||
opClass=MemWrite
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opLat=1
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[system.cpu.fuPool.FUList6]
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type=FUDesc
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children=opList0 opList1
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count=4
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opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
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[system.cpu.fuPool.FUList6.opList0]
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||||
type=OpDesc
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||||
issueLat=1
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||||
opClass=MemRead
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||||
opLat=1
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||||
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||||
[system.cpu.fuPool.FUList6.opList1]
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||||
type=OpDesc
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||||
issueLat=1
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||||
opClass=MemWrite
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||||
opLat=1
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||||
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||||
[system.cpu.fuPool.FUList7]
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||||
type=FUDesc
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||||
children=opList0
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||||
count=1
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||||
opList=system.cpu.fuPool.FUList7.opList0
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||||
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||||
[system.cpu.fuPool.FUList7.opList0]
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||||
type=OpDesc
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||||
issueLat=3
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||||
opClass=IprAccess
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||||
opLat=3
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||||
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[system.cpu.icache]
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||||
type=BaseCache
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||||
adaptive_compression=false
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||||
assoc=2
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||||
block_size=64
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||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
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||||
lifo=false
|
||||
max_miss_count=0
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||||
mshrs=10
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||||
prefetch_access=false
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||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
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||||
prefetch_policy=none
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||||
prefetch_serial_squash=false
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||||
prefetch_use_cpu_id=true
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||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=131072
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
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||||
cpu_side=system.cpu.icache_port
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||||
mem_side=system.cpu.toL2Bus.port[0]
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||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
assoc=2
|
||||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=2097152
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
|
||||
cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
gid=100
|
||||
input=cin
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
ignore=
|
||||
start=0
|
||||
|
||||
|
|
@ -0,0 +1,417 @@
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[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
range=[0,134217727]
|
||||
latency=1
|
||||
zero=false
|
||||
|
||||
[system]
|
||||
type=System
|
||||
physmem=system.physmem
|
||||
mem_mode=atomic
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/o3-timing
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
gid=100
|
||||
egid=100
|
||||
pid=100
|
||||
ppid=99
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
count=6
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
issueLat=19
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
issueLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
issueLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
count=1
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
phase=0
|
||||
numThreads=1
|
||||
activity=0
|
||||
workload=system.cpu.workload
|
||||
checker=null
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
progress_interval=0
|
||||
cachePorts=200
|
||||
decodeToFetchDelay=1
|
||||
renameToFetchDelay=1
|
||||
iewToFetchDelay=1
|
||||
commitToFetchDelay=1
|
||||
fetchWidth=8
|
||||
renameToDecodeDelay=1
|
||||
iewToDecodeDelay=1
|
||||
commitToDecodeDelay=1
|
||||
fetchToDecodeDelay=1
|
||||
decodeWidth=8
|
||||
iewToRenameDelay=1
|
||||
commitToRenameDelay=1
|
||||
decodeToRenameDelay=1
|
||||
renameWidth=8
|
||||
commitToIEWDelay=1
|
||||
renameToIEWDelay=2
|
||||
issueToExecuteDelay=1
|
||||
dispatchWidth=8
|
||||
issueWidth=8
|
||||
wbWidth=8
|
||||
wbDepth=1
|
||||
fuPool=system.cpu.fuPool
|
||||
iewToCommitDelay=1
|
||||
renameToROBDelay=1
|
||||
commitWidth=8
|
||||
squashWidth=8
|
||||
trapLatency=13
|
||||
backComSize=5
|
||||
forwardComSize=5
|
||||
predType=tournament
|
||||
localPredictorSize=2048
|
||||
localCtrBits=2
|
||||
localHistoryTableSize=2048
|
||||
localHistoryBits=11
|
||||
globalPredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
choicePredictorSize=8192
|
||||
choiceCtrBits=2
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
LQEntries=32
|
||||
SQEntries=32
|
||||
LFSTSize=1024
|
||||
SSITSize=1024
|
||||
numPhysIntRegs=256
|
||||
numPhysFloatRegs=256
|
||||
numIQEntries=64
|
||||
numROBEntries=192
|
||||
smtNumFetchingThreads=1
|
||||
smtFetchPolicy=SingleThread
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
smtCommitPolicy=RoundRobin
|
||||
instShiftAmt=2
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
size=131072
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
size=262144
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
size=2097152
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
ignore=
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[random]
|
||||
seed=1
|
||||
|
||||
[exetrace]
|
||||
speculative=true
|
||||
print_cycle=true
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
print_effaddr=true
|
||||
print_data=true
|
||||
print_iregs=false
|
||||
print_fetchseq=false
|
||||
print_cpseq=false
|
||||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
@ -0,0 +1,413 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 38046005 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 46765160 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 1072 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 5897447 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 36345249 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 64275681 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 12928446 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 88491 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 183984 # Number of bytes of host memory used
|
||||
host_seconds 4244.22 # Real time elapsed on the host
|
||||
host_tick_rate 69460 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 64217134 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 49870920 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 126084683 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 92646936 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 375574675 # Number of instructions simulated
|
||||
sim_seconds 0.000295 # Number of seconds simulated
|
||||
sim_ticks 294803028 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 44587523 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 16167573 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 260352657
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 139362663 5352.84%
|
||||
1 37755491 1450.17%
|
||||
2 23927219 919.03%
|
||||
3 17243764 662.32%
|
||||
4 9550787 366.84%
|
||||
5 7718539 296.46%
|
||||
6 5199548 199.71%
|
||||
7 3427073 131.63%
|
||||
8 16167573 620.99%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
system.cpu.commit.COM:count 398664447 # Number of instructions committed
|
||||
system.cpu.commit.COM:loads 100651988 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 174183388 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 5893264 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 398664447 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 98024957 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 375574675 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 375574675 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.784939 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.784939 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 94465294 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 5573.350269 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5155.812183 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 94463621 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 9324215 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1673 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 688 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 5078475 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 985 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 73520727 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 5442.694460 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5169.706416 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 73508218 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 68082665 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000170 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 12509 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 9314 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 16517212 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 3195 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs 2708.631579 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets 3690.984252 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 40184.650478 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 19 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 2032 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 51464 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 7500080 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 167986021 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 5458.107460 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 5166.432297 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 167971839 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 77406880 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 14182 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 10002 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 21595687 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 4180 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 167986021 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 5458.107460 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 5166.432297 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 167971839 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 77406880 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 14182 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 10002 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 21595687 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 4180 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 784 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 4180 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 3190.140908 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 167971839 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 637 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 19324711 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 4274 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 11555430 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 538406721 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 137426232 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 102617017 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 16124012 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 12594 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 984698 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 64275681 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 66044385 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 172472243 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1233740 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 552850318 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 6527825 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.232481 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 66044385 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 50974451 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.999627 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 276476670
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 170048750 6150.56%
|
||||
1 11707777 423.46%
|
||||
2 11563595 418.25%
|
||||
3 7250668 262.25%
|
||||
4 16393688 592.95%
|
||||
5 9178756 331.99%
|
||||
6 6871715 248.55%
|
||||
7 4129243 149.35%
|
||||
8 39332478 1422.63%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 66044384 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 4697.455355 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3736.572860 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 66039333 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 23726847 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 5051 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 1160 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 14539005 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000059 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 3891 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets 5023.260870 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 16972.329221 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 69 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 346605 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 66044384 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 4697.455355 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 3736.572860 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 66039333 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 23726847 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 5051 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 1160 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 14539005 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000059 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 3891 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 66044384 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 4697.455355 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 3736.572860 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 66039333 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 23726847 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 5051 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 1160 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 14539005 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000059 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 3891 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 1971 # number of replacements
|
||||
system.cpu.icache.sampled_refs 3891 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1776.887115 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 66039333 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 18326359 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 51280930 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 27455299 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.521589 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 191354897 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 79285920 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 293982680 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 415403944 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.694108 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 204055700 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.502492 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 416259284 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 6316593 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 2856011 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 126084683 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 240 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 7411275 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 92646936 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 496689311 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 112068977 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 8996952 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 420683841 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 114816 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 1986 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 16124012 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 416926 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 183286 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 727659 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 9888553 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 47660 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 81366 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 183286 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 25432695 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 19115536 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 81366 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 996952 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 5319641 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.273985 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.273985 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 429680793 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
(null) 33581 0.01% # Type of FU issued
|
||||
IntAlu 167723328 39.03% # Type of FU issued
|
||||
IntMult 2137299 0.50% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 34928239 8.13% # Type of FU issued
|
||||
FloatCmp 8071357 1.88% # Type of FU issued
|
||||
FloatCvt 3141242 0.73% # Type of FU issued
|
||||
FloatMult 16626981 3.87% # Type of FU issued
|
||||
FloatDiv 1577676 0.37% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 114426564 26.63% # Type of FU issued
|
||||
MemWrite 81014526 18.85% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 9055324 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.021075 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
(null) 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 66610 0.74% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 110487 1.22% # attempts to use FU when none available
|
||||
FloatCmp 35273 0.39% # attempts to use FU when none available
|
||||
FloatCvt 2828 0.03% # attempts to use FU when none available
|
||||
FloatMult 2149754 23.74% # attempts to use FU when none available
|
||||
FloatDiv 664669 7.34% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 4545406 50.20% # attempts to use FU when none available
|
||||
MemWrite 1480297 16.35% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 276476670
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 105552217 3817.76%
|
||||
1 55104063 1993.08%
|
||||
2 43517427 1574.00%
|
||||
3 31483356 1138.73%
|
||||
4 21726208 785.82%
|
||||
5 11633875 420.79%
|
||||
6 4624667 167.27%
|
||||
7 2409257 87.14%
|
||||
8 425600 15.39%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 1.554130 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 469233772 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 429680793 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 240 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 93305351 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 1513608 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 25 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 71392848 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadReq_accesses 8070 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 4399.297838 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2193.473956 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 717 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 32348037 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.911152 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 7353 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 16128614 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.911152 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 7353 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 637 # number of WriteReqNoAck|Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.WriteReqNoAck|Writeback_hits 637 # number of WriteReqNoAck|Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.184143 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 8070 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 4399.297838 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2193.473956 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 717 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 32348037 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.911152 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 7353 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 16128614 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.911152 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 7353 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 8707 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 4399.297838 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2193.473956 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 1354 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 32348037 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.844493 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 7353 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 16128614 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.844493 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 7353 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 7353 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 6415.706550 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1354 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.numCycles 276476670 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 8743693 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 259532206 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 653030 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 142074266 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 8196045 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 109 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 687565953 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 524563034 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 338654872 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 98656303 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 16124012 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 9950983 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 79122666 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 927413 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 40317 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 23109451 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 249 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 6216 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7002
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
getting pixel output filename pixels_out.cook
|
||||
opening control file chair.control.cook
|
||||
opening camera file chair.camera
|
||||
opening surfaces file chair.surfaces
|
||||
reading data
|
||||
processing 8parts
|
||||
Grid measure is 6 by 3.0001 by 6
|
||||
cell dimension is 0.863065
|
||||
Creating grid for list of length 21
|
||||
Grid size = 7 by 4 by 7
|
||||
Total occupancy = 236
|
||||
reading control stream
|
||||
reading camera stream
|
||||
Writing to chair.cook.ppm
|
||||
calculating 15 by 15 image with 196 samples
|
||||
col 0. . .
|
||||
col 1. . .
|
||||
col 2. . .
|
||||
col 3. . .
|
||||
col 4. . .
|
||||
col 5. . .
|
||||
col 6. . .
|
||||
col 7. . .
|
||||
col 8. . .
|
||||
col 9. . .
|
||||
col 10. . .
|
||||
col 11. . .
|
||||
col 12. . .
|
||||
col 13. . .
|
||||
col 14. . .
|
||||
Writing to chair.cook.ppm
|
||||
0 8 14
|
||||
1 8 14
|
||||
2 8 14
|
||||
3 8 14
|
||||
4 8 14
|
||||
5 8 14
|
||||
6 8 14
|
||||
7 8 14
|
||||
8 8 14
|
||||
9 8 14
|
||||
10 8 14
|
||||
11 8 14
|
||||
12 8 14
|
||||
13 8 14
|
||||
14 8 14
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
Eon, Version 1.1
|
||||
OO-style eon Time= 0.000000
|
||||
Loading…
Reference in a new issue