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gem5/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt

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ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- Begin Simulation Statistics ----------
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
sim_seconds 0.523064 # Number of seconds simulated
sim_ticks 523063504500 # Number of ticks simulated
final_tick 523063504500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
host_inst_rate 149016 # Simulator instruction rate (inst/s)
host_op_rate 166238 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 50463882 # Simulator tick rate (ticks/s)
host_mem_usage 261252 # Number of bytes of host memory used
host_seconds 10365.11 # Real time elapsed on the host
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
sim_insts 1544563023 # Number of instructions simulated
sim_ops 1723073835 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.bytes_read::cpu.inst 48064 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 143764288 # Number of bytes read from this memory
system.physmem.bytes_read::total 143812352 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 48064 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 48064 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 70447616 # Number of bytes written to this memory
system.physmem.bytes_written::total 70447616 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 751 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2246317 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2247068 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1100744 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1100744 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 91889 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 274850543 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 274942432 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 91889 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 91889 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 134682721 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 134682721 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 134682721 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 91889 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 274850543 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 409625153 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 2247068 # Number of read requests accepted
system.physmem.writeReqs 1100744 # Number of write requests accepted
system.physmem.readBursts 2247068 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1100744 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 143722368 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 89984 # Total number of bytes read from write queue
system.physmem.bytesWritten 70445760 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 143812352 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 70447616 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 1406 # Number of DRAM read bursts serviced by the write queue
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.perBankRdBursts::0 139750 # Per bank write bursts
system.physmem.perBankRdBursts::1 136144 # Per bank write bursts
system.physmem.perBankRdBursts::2 133842 # Per bank write bursts
system.physmem.perBankRdBursts::3 136111 # Per bank write bursts
system.physmem.perBankRdBursts::4 134906 # Per bank write bursts
system.physmem.perBankRdBursts::5 135203 # Per bank write bursts
system.physmem.perBankRdBursts::6 136131 # Per bank write bursts
system.physmem.perBankRdBursts::7 136315 # Per bank write bursts
system.physmem.perBankRdBursts::8 143809 # Per bank write bursts
system.physmem.perBankRdBursts::9 146590 # Per bank write bursts
system.physmem.perBankRdBursts::10 144423 # Per bank write bursts
system.physmem.perBankRdBursts::11 146169 # Per bank write bursts
system.physmem.perBankRdBursts::12 145711 # Per bank write bursts
system.physmem.perBankRdBursts::13 146127 # Per bank write bursts
system.physmem.perBankRdBursts::14 142010 # Per bank write bursts
system.physmem.perBankRdBursts::15 142421 # Per bank write bursts
system.physmem.perBankWrBursts::0 69157 # Per bank write bursts
system.physmem.perBankWrBursts::1 67395 # Per bank write bursts
system.physmem.perBankWrBursts::2 65690 # Per bank write bursts
system.physmem.perBankWrBursts::3 66283 # Per bank write bursts
system.physmem.perBankWrBursts::4 66211 # Per bank write bursts
system.physmem.perBankWrBursts::5 66391 # Per bank write bursts
system.physmem.perBankWrBursts::6 67933 # Per bank write bursts
system.physmem.perBankWrBursts::7 68845 # Per bank write bursts
system.physmem.perBankWrBursts::8 70389 # Per bank write bursts
system.physmem.perBankWrBursts::9 71029 # Per bank write bursts
system.physmem.perBankWrBursts::10 70577 # Per bank write bursts
system.physmem.perBankWrBursts::11 70974 # Per bank write bursts
system.physmem.perBankWrBursts::12 70326 # Per bank write bursts
system.physmem.perBankWrBursts::13 70796 # Per bank write bursts
system.physmem.perBankWrBursts::14 69605 # Per bank write bursts
system.physmem.perBankWrBursts::15 69114 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.totGap 523063435500 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.readPktSize::6 2247068 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.writePktSize::6 1100744 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1615066 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 449330 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 137330 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 43923 # What read queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.wrQLenPdf::15 23358 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 24975 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 49534 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 60519 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 65129 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 66570 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 66892 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 67087 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 67169 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 67424 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 67533 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 67827 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 68851 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 70296 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 67618 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 68033 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 66306 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 65326 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 193 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 13 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.bytesPerActivate::samples 2025915 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 105.713545 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 82.619710 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 129.565498 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 1567130 77.35% 77.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 318929 15.74% 93.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 67085 3.31% 96.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 23530 1.16% 97.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 13977 0.69% 98.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 6837 0.34% 98.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 5148 0.25% 98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 3637 0.18% 99.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 19642 0.97% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 2025915 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 65189 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 34.403642 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 148.850371 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 65147 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 15 0.02% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 11 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095 8 0.01% 99.99% # Reads before turning the bus around for writes
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9216-10239 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # Reads before turning the bus around for writes
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.rdPerTurnAround::total 65189 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 65189 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.884981 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.844479 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 1.202215 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 39520 60.62% 60.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 1483 2.27% 62.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 18196 27.91% 90.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 4786 7.34% 98.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 898 1.38% 99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 207 0.32% 99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 54 0.08% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 11 0.02% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 9 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 1 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 2 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27 1 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28 2 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29 1 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30 3 0.00% 99.98% # Writes before turning the bus around for reads
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.wrPerTurnAround::31 10 0.02% 99.99% # Writes before turning the bus around for reads
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.wrPerTurnAround::32 3 0.00% 100.00% # Writes before turning the bus around for reads
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.wrPerTurnAround::33 1 0.00% 100.00% # Writes before turning the bus around for reads
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.wrPerTurnAround::40 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 65189 # Writes before turning the bus around for reads
system.physmem.totQLat 50228413500 # Total ticks spent queuing
system.physmem.totMemAccLat 92334576000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 11228310000 # Total ticks spent in databus transfers
system.physmem.avgQLat 22366.86 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.avgMemAccLat 41116.86 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 274.77 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 134.68 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 274.94 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 134.68 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.busUtil 3.20 # Data bus utilization in percentage
system.physmem.busUtilRead 2.15 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 1.05 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.83 # Average write queue length when enqueuing
system.physmem.readRowHits 905849 # Number of row buffer hits during reads
system.physmem.writeRowHits 414601 # Number of row buffer hits during writes
system.physmem.readRowHitRate 40.34 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 37.67 # Row buffer hit rate for writes
system.physmem.avgGap 156240.38 # Average gap between requests
system.physmem.pageHitRate 39.46 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 94741058000 # Time in different power states
system.physmem.memoryStateTime::REF 17466020000 # Time in different power states
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.memoryStateTime::ACT 410854630500 # Time in different power states
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.membus.throughput 409625031 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 1419612 # Transaction distribution
system.membus.trans_dist::ReadResp 1419611 # Transaction distribution
system.membus.trans_dist::Writeback 1100744 # Transaction distribution
system.membus.trans_dist::ReadExReq 827456 # Transaction distribution
system.membus.trans_dist::ReadExResp 827456 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5594879 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 5594879 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214259904 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 214259904 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 214259904 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.membus.reqLayer0.occupancy 12872956000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.5 # Layer utilization (%)
system.membus.respLayer1.occupancy 21034966500 # Layer occupancy (ticks)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.membus.respLayer1.utilization 4.0 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.branchPred.lookups 310041872 # Number of BP lookups
system.cpu.branchPred.condPredicted 254951905 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 15242132 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 177250182 # Number of BTB lookups
system.cpu.branchPred.BTBHits 164623168 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.branchPred.BTBHitPct 92.876163 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 17905906 # Number of times the RAS was used to get a target.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.branchPred.RASInCorrect 206 # Number of incorrect RAS predictions.
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.numCycles 1046127010 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.fetch.icacheStallCycles 304406506 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2237155990 # Number of instructions fetch has processed
system.cpu.fetch.Branches 310041872 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 182529074 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 444747763 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 93800973 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 104367517 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 63 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 295060555 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 6266924 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 929205544 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.663579 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.245143 # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.fetch.rateDist::0 484458019 52.14% 52.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 25667204 2.76% 54.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 39962445 4.30% 59.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 49351933 5.31% 64.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 44527866 4.79% 69.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 47023403 5.06% 74.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 39036338 4.20% 78.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 19508250 2.10% 80.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 179670086 19.34% 100.00% # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.fetch.rateDist::total 929205544 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.296371 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.138513 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 323230837 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 95973570 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 424273226 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 10044892 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 75683019 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 46957126 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 712 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 2419092576 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 2470 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 75683019 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 338590369 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 36235131 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 20070 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 418478079 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 60198876 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2357219159 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 486871 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 10439342 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 39865193 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 9487400 # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents 108 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 2332621614 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 10887738442 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 9980989966 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 478 # Number of floating rename lookups
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.rename.UndoneMaps 626301684 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1665 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1662 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 62763220 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 637377073 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 224726985 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 97022139 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 86012676 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2244793752 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1629 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2031991177 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 6410093 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 517307509 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1273036014 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1459 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 929205544 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.186805 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.944442 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.iq.issued_per_cycle::0 266904218 28.72% 28.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 128322549 13.81% 42.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 158977129 17.11% 59.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 117185502 12.61% 72.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 128428514 13.82% 86.08% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 72785870 7.83% 93.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 42669642 4.59% 98.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 10960354 1.18% 99.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 2971766 0.32% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.iq.issued_per_cycle::total 929205544 # Number of insts issued each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.iq.fu_full::IntAlu 1285844 5.85% 5.85% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 5675 0.03% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.88% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 18368199 83.62% 89.50% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 2306433 10.50% 100.00% # attempts to use FU when none available
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.iq.FU_type_0::IntAlu 1245462856 61.29% 61.29% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 947392 0.05% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 51 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 9 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.34% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 592199391 29.14% 90.48% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 193381454 9.52% 100.00% # Type of FU issued
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.iq.FU_type_0::total 2031991177 # Type of FU issued
system.cpu.iq.rate 1.942394 # Inst issue rate
system.cpu.iq.fu_busy_cnt 21966151 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.010810 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 5021563817 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2762296727 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1969035141 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 325 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 660 # Number of floating instruction queue writes
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.iq.fp_inst_queue_wakeup_accesses 139 # Number of floating instruction queue wakeup accesses
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.iq.int_alu_accesses 2053957167 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 161 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 66315008 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 151450304 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 182572 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 197144 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 49879940 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 4648682 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.iew.iewSquashCycles 75683019 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 13889446 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 17402817 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2244795480 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 7970371 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 637377073 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 224726985 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1567 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 551835 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 16641279 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 197144 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 8164855 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 9718586 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 17883441 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 2000301565 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 577561658 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 31689612 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.iew.exec_nop 99 # number of nop insts executed
system.cpu.iew.exec_refs 768256899 # number of memory reference insts executed
system.cpu.iew.exec_branches 239583236 # Number of branches executed
system.cpu.iew.exec_stores 190695241 # Number of stores executed
system.cpu.iew.exec_rate 1.912102 # Inst execution rate
system.cpu.iew.wb_sent 1977910575 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1969035280 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1321133911 # num instructions producing a value
system.cpu.iew.wb_consumers 2129107129 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.iew.wb_rate 1.882214 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.620511 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.commit.commitSquashedInsts 522107871 # The number of squashed insts skipped by commit
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.commit.branchMispredicts 15241473 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 853522525 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.018780 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.777115 # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.commit.committed_per_cycle::0 375117315 43.95% 43.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 185477330 21.73% 65.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 70116011 8.21% 73.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 33059312 3.87% 77.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 18836055 2.21% 79.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 30683416 3.59% 83.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 20461939 2.40% 85.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 11515545 1.35% 87.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 108255602 12.68% 100.00% # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.commit.committed_per_cycle::total 853522525 # Number of insts commited each cycle
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.committedInsts 1544563041 # Number of instructions committed
system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.refs 660773814 # Number of memory references committed
system.cpu.commit.loads 485926769 # Number of loads committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.membars 62 # Number of memory barriers committed
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.branches 213462426 # Number of branches committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 1061599714 61.61% 61.61% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.65% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 485926769 28.20% 89.85% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 174847045 10.15% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1723073853 # Class of committed instruction
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.commit.bw_lim_events 108255602 # number cycles where commit BW limit reached
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.rob.rob_reads 2990448048 # The number of ROB reads
system.cpu.rob.rob_writes 4566229463 # The number of ROB writes
system.cpu.timesIdled 1335234 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 116921466 # Total number of cycles that the CPU has spent unscheduled due to idling
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.committedInsts 1544563023 # Number of Instructions Simulated
system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.cpi 0.677296 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.677296 # CPI: Total CPI of All Threads
system.cpu.ipc 1.476458 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.476458 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 10016037678 # number of integer regfile reads
system.cpu.int_regfile_writes 1949973157 # number of integer regfile writes
system.cpu.fp_regfile_reads 144 # number of floating regfile reads
system.cpu.fp_regfile_writes 144 # number of floating regfile writes
system.cpu.misc_regfile_reads 741547581 # number of misc regfile reads
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.misc_regfile_writes 124 # number of misc regfile writes
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.toL2Bus.throughput 1637500473 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 7708273 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 7708272 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 3780671 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1894131 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1894131 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1564 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22983914 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 22985478 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50048 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856466688 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 856516736 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 856516736 # Total data (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.toL2Bus.reqLayer0.occupancy 10472370339 # Layer occupancy (ticks)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%)
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 1301749 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 14750464244 # Layer occupancy (ticks)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.toL2Bus.respLayer1.utilization 2.8 # Layer utilization (%)
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.icache.tags.replacements 21 # number of replacements
system.cpu.icache.tags.tagsinuse 633.135504 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 295059337 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 782 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 377313.730179 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.icache.tags.occ_blocks::cpu.inst 633.135504 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.309148 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.309148 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 761 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::4 732 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.371582 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 590121892 # Number of tag accesses
system.cpu.icache.tags.data_accesses 590121892 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 295059337 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 295059337 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 295059337 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 295059337 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 295059337 # number of overall hits
system.cpu.icache.overall_hits::total 295059337 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1218 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1218 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1218 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1218 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1218 # number of overall misses
system.cpu.icache.overall_misses::total 1218 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 82722999 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 82722999 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 82722999 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 82722999 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 82722999 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 82722999 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 295060555 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 295060555 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 295060555 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 295060555 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 295060555 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 295060555 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67917.076355 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 67917.076355 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 67917.076355 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 67917.076355 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 67917.076355 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 67917.076355 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 292 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 48.666667 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 436 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 436 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 436 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 436 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 436 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 436 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 782 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 782 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 782 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 782 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 782 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 782 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55396751 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 55396751 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55396751 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 55396751 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55396751 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 55396751 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70839.835038 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70839.835038 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70839.835038 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 70839.835038 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70839.835038 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 70839.835038 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.tags.replacements 2214381 # number of replacements
system.cpu.l2cache.tags.tagsinuse 31528.028759 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 9244052 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 2244157 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 4.119165 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 21499673750 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 14271.586690 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.657217 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 17235.784852 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.435534 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000630 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.525994 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.962159 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 81 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1924 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 23845 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3832 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 111202888 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 111202888 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 30 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 6288624 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 6288654 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3780671 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 3780671 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1066675 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1066675 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 30 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 7355299 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7355329 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 30 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 7355299 # number of overall hits
system.cpu.l2cache.overall_hits::total 7355329 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 752 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 1418867 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1419619 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 827456 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 827456 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 752 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2246323 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 2247075 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 752 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2246323 # number of overall misses
system.cpu.l2cache.overall_misses::total 2247075 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 54308250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 119156229500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 119210537750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70981342750 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 70981342750 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 54308250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 190137572250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 190191880500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 54308250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 190137572250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 190191880500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 782 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7707491 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7708273 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 3780671 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 3780671 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1894131 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1894131 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 782 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9601622 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9602404 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 782 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9601622 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9602404 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.961637 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184089 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.184168 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436853 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.436853 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.961637 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.233952 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.234012 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961637 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.233952 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.234012 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72218.417553 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83979.844129 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 83973.613871 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85782.618955 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85782.618955 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72218.417553 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84643.914633 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 84639.756350 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72218.417553 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84643.914633 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 84639.756350 # average overall miss latency
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.writebacks::writebacks 1100744 # number of writebacks
system.cpu.l2cache.writebacks::total 1100744 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 751 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1418861 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1419612 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 827456 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 827456 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 751 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2246317 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 2247068 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 751 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2246317 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2247068 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 44796750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 101386052500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 101430849250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60631607750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60631607750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44796750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 162017660250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 162062457000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44796750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 162017660250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 162062457000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960358 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184089 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184167 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436853 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436853 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960358 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233952 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.234011 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960358 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233952 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.234011 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59649.467377 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71455.944240 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71449.698404 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73274.721254 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73274.721254 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59649.467377 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72125.911102 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72121.741309 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59649.467377 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72125.911102 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72121.741309 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.dcache.tags.replacements 9597525 # number of replacements
system.cpu.dcache.tags.tagsinuse 4087.935639 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 657806876 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9601621 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 68.509981 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 3523864250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.935639 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.998031 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.998031 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 660 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2418 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1017 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.dcache.tags.tag_accesses 1359744661 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1359744661 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 490891096 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 490891096 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 166915657 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 166915657 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.dcache.demand_hits::cpu.data 657806753 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 657806753 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 657806753 # number of overall hits
system.cpu.dcache.overall_hits::total 657806753 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 11594251 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 11594251 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5670390 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5670390 # number of WriteReq misses
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.dcache.demand_misses::cpu.data 17264641 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 17264641 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 17264641 # number of overall misses
system.cpu.dcache.overall_misses::total 17264641 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 353287122740 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 353287122740 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 298200381062 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 298200381062 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 243250 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 243250 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 651487503802 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 651487503802 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 651487503802 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 651487503802 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 502485347 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 502485347 # number of ReadReq accesses(hits+misses)
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 65 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 65 # number of LoadLockedReq accesses(hits+misses)
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.dcache.demand_accesses::cpu.data 675071394 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 675071394 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 675071394 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 675071394 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023074 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.023074 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032855 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.032855 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046154 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046154 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.025575 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.025575 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.025575 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.025575 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30470.887920 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 30470.887920 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52589.042564 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 52589.042564 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 81083.333333 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 81083.333333 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37735.363498 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 37735.363498 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 37735.363498 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 37735.363498 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 22798709 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 4000734 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1307566 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 65131 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.435991 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 61.425957 # average number of cycles each access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.dcache.writebacks::writebacks 3780671 # number of writebacks
system.cpu.dcache.writebacks::total 3780671 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3886759 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 3886759 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3776260 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3776260 # number of WriteReq MSHR hits
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.dcache.demand_mshr_hits::cpu.data 7663019 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 7663019 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 7663019 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 7663019 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7707492 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7707492 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894130 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1894130 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9601622 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9601622 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9601622 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9601622 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 191674058756 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 191674058756 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84036609462 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 84036609462 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 275710668218 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 275710668218 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 275710668218 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 275710668218 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015339 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015339 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010975 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010975 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.014223 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.014223 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24868.538139 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24868.538139 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44366.864715 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44366.864715 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28715.009633 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28715.009633 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28715.009633 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28715.009633 # average overall mshr miss latency
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- End Simulation Statistics ----------
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