2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2011-04-12 22:09:20 +02:00
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host_inst_rate 189685 # Simulator instruction rate (inst/s)
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host_mem_usage 258720 # Number of bytes of host memory used
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host_seconds 9083.85 # Real time elapsed on the host
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host_tick_rate 70772893 # Simulator tick rate (ticks/s)
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-04-04 18:42:31 +02:00
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sim_insts 1723073854 # Number of instructions simulated
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sim_seconds 0.642891 # Number of seconds simulated
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sim_ticks 642890553000 # Number of ticks simulated
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2011-01-18 23:30:06 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-04-04 18:42:31 +02:00
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system.cpu.BPredUnit.BTBHits 223193937 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 259593204 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 340 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 18005065 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 242843937 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 296310364 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 17771313 # Number of times the RAS was used to get a target.
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system.cpu.commit.COM:branches 213462366 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 57604302 # number cycles where commit BW limit reached
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2011-01-18 23:30:06 +01:00
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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2011-04-04 18:42:31 +02:00
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system.cpu.commit.COM:committed_per_cycle::samples 1166659925 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 1.476929 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 2.106061 # Number of insts commited each cycle
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2011-01-18 23:30:06 +01:00
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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2011-04-04 18:42:31 +02:00
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system.cpu.commit.COM:committed_per_cycle::0 510754561 43.78% 43.78% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1 303447125 26.01% 69.79% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2 123940356 10.62% 80.41% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3 73811223 6.33% 86.74% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4 36743344 3.15% 89.89% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5 32005168 2.74% 92.63% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6 15998188 1.37% 94.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7 12355658 1.06% 95.06% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 57604302 4.94% 100.00% # Number of insts commited each cycle
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2011-01-18 23:30:06 +01:00
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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2011-04-04 18:42:31 +02:00
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system.cpu.commit.COM:committed_per_cycle::total 1166659925 # Number of insts commited each cycle
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system.cpu.commit.COM:count 1723073872 # Number of instructions committed
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2011-02-08 04:23:13 +01:00
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system.cpu.commit.COM:fp_insts 36 # Number of committed floating point instructions.
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2011-03-18 01:20:22 +01:00
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system.cpu.commit.COM:function_calls 13665177 # Number of function calls committed.
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2011-04-04 18:42:31 +02:00
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system.cpu.commit.COM:int_insts 1536941857 # Number of committed integer instructions.
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system.cpu.commit.COM:loads 485926772 # Number of loads committed
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2011-03-18 01:20:22 +01:00
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system.cpu.commit.COM:membars 62 # Number of memory barriers committed
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2011-04-04 18:42:31 +02:00
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system.cpu.commit.COM:refs 660773819 # Number of memory references committed
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2011-01-18 23:30:06 +01:00
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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2011-04-04 18:42:31 +02:00
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system.cpu.commit.branchMispredicts 18004568 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 1723073872 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 458 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 488146148 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 1723073854 # Number of Instructions Simulated
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system.cpu.committedInsts_total 1723073854 # Number of Instructions Simulated
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system.cpu.cpi 0.746214 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.746214 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses 65 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_avg_miss_latency 27333.333333 # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_hits 62 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_miss_latency 82000 # number of LoadLockedReq miss cycles
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system.cpu.dcache.LoadLockedReq_miss_rate 0.046154 # miss rate for LoadLockedReq accesses
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.ReadReq_accesses 501584612 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 15160.364798 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11507.023204 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 493452712 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 123282570500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.016212 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 8131900 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 482613 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 88020523000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.015250 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 7649287 # number of ReadReq MSHR misses
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system.cpu.dcache.StoreCondReq_accesses 63 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_hits 63 # number of StoreCondReq hits
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2011-03-18 01:20:22 +01:00
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system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses)
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.WriteReq_avg_miss_latency 23758.689113 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20868.683162 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 168021895 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 108438268431 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.026446 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 4564152 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 2672149 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 39483611148 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.010963 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 1892003 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs 3136.287441 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets 20750 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 69.327600 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 24979 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 78341324 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 166000 # number of cycles access was blocked
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.demand_accesses 674170659 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 18251.409094 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 13363.406222 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 661474607 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 231720838931 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.018832 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 12696052 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 3154762 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 127504134148 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.014153 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 9541290 # number of demand (read+write) MSHR misses
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.occ_%::0 0.997826 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 4087.096656 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 674170659 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 18251.409094 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 13363.406222 # average overall mshr miss latency
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.overall_hits 661474607 # number of overall hits
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system.cpu.dcache.overall_miss_latency 231720838931 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.018832 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 12696052 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 3154762 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 127504134148 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.014153 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 9541290 # number of overall MSHR misses
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.replacements 9537194 # number of replacements
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system.cpu.dcache.sampled_refs 9541290 # Sample count of references to valid blocks.
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2011-01-18 23:30:06 +01:00
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2011-04-04 18:42:31 +02:00
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system.cpu.dcache.tagsinuse 4087.096656 # Cycle average of tags in use
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system.cpu.dcache.total_refs 661474732 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 5035189000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 3122149 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 127119222 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 630 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 46145837 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 2344585205 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 578307676 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 449658106 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 70439042 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 2261 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 11574920 # Number of cycles decode is unblocking
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-04-04 18:42:31 +02:00
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system.cpu.fetch.Branches 296310364 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 276394619 # Number of cache lines fetched
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system.cpu.fetch.Cycles 469857260 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 5099612 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 2155595751 # Number of instructions fetch has processed
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system.cpu.fetch.MiscStallCycles 63 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.SquashCycles 18544487 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.230452 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 276394619 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 240965250 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 1.676487 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist::samples 1237098966 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.930612 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.884681 # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-04-04 18:42:31 +02:00
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system.cpu.fetch.rateDist::0 767241756 62.02% 62.02% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 33244799 2.69% 64.71% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 58987586 4.77% 69.47% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 61314807 4.96% 74.43% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 46983054 3.80% 78.23% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 54993105 4.45% 82.67% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 53020195 4.29% 86.96% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 18334456 1.48% 88.44% # Number of instructions fetched each cycle (Total)
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|
|
system.cpu.fetch.rateDist::8 142979208 11.56% 100.00% # Number of instructions fetched each cycle (Total)
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.fetch.rateDist::total 1237098966 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fp_regfile_reads 39 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 31 # number of floating regfile writes
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 276394619 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 34658.288770 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34406.030856 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_hits 276393684 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 32405500 # number of ReadReq miss cycles
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.ReadReq_misses 935 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 222 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 24531500 # number of ReadReq MSHR miss cycles
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses 713 # number of ReadReq MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.avg_refs 387648.925666 # Average number of references to valid blocks.
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.demand_accesses 276394619 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 34658.288770 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 34406.030856 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 276393684 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 32405500 # number of demand (read+write) miss cycles
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.demand_misses 935 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 222 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 24531500 # number of demand (read+write) MSHR miss cycles
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.demand_mshr_misses 713 # number of demand (read+write) MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.occ_%::0 0.281945 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_blocks::0 577.423416 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.overall_accesses 276394619 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 34658.288770 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 34406.030856 # average overall mshr miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.overall_hits 276393684 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 32405500 # number of overall miss cycles
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.overall_misses 935 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 222 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 24531500 # number of overall MSHR miss cycles
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.overall_mshr_misses 713 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.icache.replacements 8 # number of replacements
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.sampled_refs 713 # Sample count of references to valid blocks.
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.icache.tagsinuse 577.423416 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 276393684 # Total number of references to valid blocks.
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.idleCycles 48682141 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 233410057 # Number of branches executed
|
|
|
|
|
system.cpu.iew.EXEC:nop 371 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.EXEC:rate 1.517006 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 747857641 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:stores 187754946 # Number of stores executed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iew.WB:consumers 2256424150 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 1928710637 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.551017 # average fanout of values written-back
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iew.WB:producers 1243327288 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 1.500030 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 1934940770 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 19351943 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewBlockCycles 24201668 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 626078428 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 573 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 5945884 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 225252424 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 2211114719 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 560102695 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 21129397 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 1950537549 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 1433857 # Number of times the IQ has become full, causing a stall
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 76087 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewSquashCycles 70439042 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 2509999 # Number of cycles IEW is unblocking
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 185300 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 54506765 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 584812 # Number of memory responses ignored because the instruction is squashed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 734835 # Number of memory ordering violations
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 2 # Number of loads that were rescheduled
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 140151655 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 50405377 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 734835 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 3232685 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 16119258 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.int_regfile_reads 5040549881 # number of integer regfile reads
|
2011-04-12 22:09:20 +02:00
|
|
|
system.cpu.int_regfile_writes 1533135927 # number of integer regfile writes
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.ipc 1.340099 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.340099 # IPC: Total IPC of All Threads
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1212590834 61.50% 61.50% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntMult 1140241 0.06% 61.56% # Type of FU issued
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 61.56% # Type of FU issued
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 6 0.00% 61.56% # Type of FU issued
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 1 0.00% 61.56% # Type of FU issued
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 7 0.00% 61.56% # Type of FU issued
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 61.56% # Type of FU issued
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemRead 568540639 28.84% 90.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemWrite 189395216 9.61% 100.00% # Type of FU issued
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::total 1971666946 # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 20875026 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.010588 # FU busy rate (busy events/executed inst)
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::IntAlu 491210 2.35% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntMult 2 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemRead 19087912 91.44% 93.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemWrite 1295902 6.21% 100.00% # attempts to use FU when none available
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 1237098966 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.593783 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.635374 # Number of insts issued each cycle
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0 418606363 33.84% 33.84% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1 277983689 22.47% 56.31% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2 220653980 17.84% 74.14% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3 149807025 12.11% 86.25% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4 89527255 7.24% 93.49% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5 51723580 4.18% 97.67% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6 17902939 1.45% 99.12% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7 8343412 0.67% 99.79% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 2550723 0.21% 100.00% # Number of insts issued each cycle
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 1237098966 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:rate 1.533439 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 63 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 120 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 51 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 94 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.int_alu_accesses 1992541909 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 5201971393 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1928710586 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 2696699928 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.iqInstsAdded 2211113711 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 1971666946 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 637 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 484979968 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 663629 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 179 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 843902514 # Number of squashed operands that are examined and possibly removed from graph
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
|
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 1892006 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34501.539320 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31341.195670 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 979915 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 31468543500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.482076 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 912091 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 28586022500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482076 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 912091 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 7649997 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34318.289104 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31128.516872 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 5630330 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 69311516000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.264009 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 2019667 # number of ReadReq misses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 62868927000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.264008 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 2019657 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 3122149 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 3122149 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3935.335196 # average number of cycles each access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.avg_refs 2.653954 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.blocked::no_mshrs 3580 # number of cycles access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 14088500 # number of cycles access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 9542003 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34375.299564 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31194.683001 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_hits 6610245 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 100780059500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.307248 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 2931758 # number of demand (read+write) misses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 91454949500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.307247 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 2931748 # number of demand (read+write) MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.occ_%::0 0.487988 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_%::1 0.329914 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_blocks::0 15990.396178 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 10810.627507 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.overall_accesses 9542003 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34375.299564 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.683001 # average overall mshr miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.overall_hits 6610245 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 100780059500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.307248 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 2931758 # number of overall misses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 91454949500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.307247 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 2931748 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.replacements 2919341 # number of replacements
|
|
|
|
|
system.cpu.l2cache.sampled_refs 2946667 # Sample count of references to valid blocks.
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 26801.023686 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 7820318 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 143319905000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 1216305 # number of writebacks
|
|
|
|
|
system.cpu.memDep0.conflictingLoads 95681801 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 90040335 # Number of conflicting stores.
|
|
|
|
|
system.cpu.memDep0.insertedLoads 626078428 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 225252424 # Number of stores inserted to the mem dependence unit.
|
2011-04-12 22:09:20 +02:00
|
|
|
system.cpu.misc_regfile_reads 2884001507 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 128 # number of misc regfile writes
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.numCycles 1285781107 # number of cpu cycles simulated
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
2011-04-04 18:42:31 +02:00
|
|
|
system.cpu.rename.RENAME:BlockCycles 67172415 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.RENAME:CommittedMaps 1360917377 # Number of HB maps that are committed
|
|
|
|
|
system.cpu.rename.RENAME:IQFullEvents 14851346 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.RENAME:IdleCycles 600335413 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 40774846 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RENAME:ROBFullEvents 10242 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu.rename.RENAME:RenameLookups 6331353991 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 2292668273 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 1803116545 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 438383597 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 70439042 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 60752889 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 442199165 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:fp_rename_lookups 393 # Number of floating rename lookups
|
|
|
|
|
system.cpu.rename.RENAME:int_rename_lookups 6331353598 # Number of integer rename lookups
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 15610 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RENAME:serializingInsts 650 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.RENAME:skidInsts 118137729 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 645 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.rob.rob_reads 3320275044 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 4492885352 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 1544733 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
